1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2022 NXP 4 */ 5 6#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__ 7#define __ASM_ARCH_IMX9_CCM_REGS_H__ 8#define IMX93_CLK_ROOT_MAX 95 9#define IMX93_CLK_CCGR_MAX 127 10 11#define ARM_A55_PERIPH_CLK_ROOT 0 12#define ARM_A55_MTR_BUS_CLK_ROOT 1 13#define ARM_A55_CLK_ROOT 2 14#define M33_CLK_ROOT 3 15#define ELE_CLK_ROOT 4 16#define BUS_WAKEUP_CLK_ROOT 5 17#define BUS_AON_CLK_ROOT 6 18#define WAKEUP_AXI_CLK_ROOT 7 19#define SWO_TRACE_CLK_ROOT 8 20#define M33_SYSTICK_CLK_ROOT 9 21#define FLEXIO1_CLK_ROOT 10 22#define FLEXIO2_CLK_ROOT 11 23#define LPIT1_CLK_ROOT 12 24#define LPIT2_CLK_ROOT 13 25#define LPTMR1_CLK_ROOT 14 26#define LPTMR2_CLK_ROOT 15 27#define TPM1_CLK_ROOT 16 28#define TPM2_CLK_ROOT 17 29#define TPM3_CLK_ROOT 18 30#define TPM4_CLK_ROOT 19 31#define TPM5_CLK_ROOT 20 32#define TPM6_CLK_ROOT 21 33#define FLEXSPI1_CLK_ROOT 22 34#define CAN1_CLK_ROOT 23 35#define CAN2_CLK_ROOT 24 36#define LPUART1_CLK_ROOT 25 37#define LPUART2_CLK_ROOT 26 38#define LPUART3_CLK_ROOT 27 39#define LPUART4_CLK_ROOT 28 40#define LPUART5_CLK_ROOT 29 41#define LPUART6_CLK_ROOT 30 42#define LPUART7_CLK_ROOT 31 43#define LPUART8_CLK_ROOT 32 44#define LPI2C1_CLK_ROOT 33 45#define LPI2C2_CLK_ROOT 34 46#define LPI2C3_CLK_ROOT 35 47#define LPI2C4_CLK_ROOT 36 48#define LPI2C5_CLK_ROOT 37 49#define LPI2C6_CLK_ROOT 38 50#define LPI2C7_CLK_ROOT 39 51#define LPI2C8_CLK_ROOT 40 52#define LPSPI1_CLK_ROOT 41 53#define LPSPI2_CLK_ROOT 42 54#define LPSPI3_CLK_ROOT 43 55#define LPSPI4_CLK_ROOT 44 56#define LPSPI5_CLK_ROOT 45 57#define LPSPI6_CLK_ROOT 46 58#define LPSPI7_CLK_ROOT 47 59#define LPSPI8_CLK_ROOT 48 60#define I3C1_CLK_ROOT 49 61#define I3C2_CLK_ROOT 50 62#define USDHC1_CLK_ROOT 51 63#define USDHC2_CLK_ROOT 52 64#define USDHC3_CLK_ROOT 53 65#define SAI1_CLK_ROOT 54 66#define SAI2_CLK_ROOT 55 67#define SAI3_CLK_ROOT 56 68#define CCM_CKO1_CLK_ROOT 57 69#define CCM_CKO2_CLK_ROOT 58 70#define CCM_CKO3_CLK_ROOT 59 71#define CCM_CKO4_CLK_ROOT 60 72#define HSIO_CLK_ROOT 61 73#define HSIO_USB_TEST_60M_CLK_ROOT 62 74#define HSIO_ACSCAN_80M_CLK_ROOT 63 75#define HSIO_ACSCAN_480M_CLK_ROOT 64 76#define NIC_CLK_ROOT 65 77#define NIC_APB_CLK_ROOT 66 78#define ML_APB_CLK_ROOT 67 79#define ML_CLK_ROOT 68 80#define MEDIA_AXI_CLK_ROOT 69 81#define MEDIA_APB_CLK_ROOT 70 82#define MEDIA_LDB_CLK_ROOT 71 83#define MEDIA_DISP_PIX_CLK_ROOT 72 84#define CAM_PIX_CLK_ROOT 73 85#define MIPI_TEST_BYTE_CLK_ROOT 74 86#define MIPI_PHY_CFG_CLK_ROOT 75 87#define DRAM_ALT_CLK_ROOT 76 88#define DRAM_APB_CLK_ROOT 77 89#define ADC_CLK_ROOT 78 90#define PDM_CLK_ROOT 79 91#define TSTMR1_CLK_ROOT 80 92#define TSTMR2_CLK_ROOT 81 93#define MQS1_CLK_ROOT 82 94#define MQS2_CLK_ROOT 83 95#define AUDIO_XCVR_CLK_ROOT 84 96#define SPDIF_CLK_ROOT 85 97#define ENET_CLK_ROOT 86 98#define ENET_TIMER1_CLK_ROOT 87 99#define ENET_TIMER2_CLK_ROOT 88 100#define ENET_REF_CLK_ROOT 89 101#define ENET_REF_PHY_CLK_ROOT 90 102#define I3C1_SLOW_CLK_ROOT 91 103#define I3C2_SLOW_CLK_ROOT 92 104#define USB_PHY_BURUNIN_CLK_ROOT 93 105#define PAL_CAME_SCAN_CLK_ROOT 94 106#define CLK_ROOT_NUM 95 107 108#define CCGR_A55 0 109#define CCGR_CM33 1 110#define CCGR_ARMTROUT 2 111#define CCGR_SENT 3 112#define CCGR_BUSM 4 113#define CCGR_BUS7 5 114#define CCGR_BUSD 6 115#define CCGR_ANAD 7 116#define CCGR_SRC 8 117#define CCGR_CCM 9 118#define CCGR_GPC 10 119#define CCGR_ADC 11 120#define CCGR_WDG1 12 121#define CCGR_WDG2 13 122#define CCGR_WDG3 14 123#define CCGR_WDG4 15 124#define CCGR_WDG5 16 125#define CCGR_SEM1 17 126#define CCGR_SEM2 18 127#define CCGR_MUA 19 128#define CCGR_MUB 20 129#define CCGR_DMA1 21 130#define CCGR_DMA2 22 131#define CCGR_ROMCA55 23 132#define CCGR_ROMCM33 24 133#define CCGR_QSP1 25 134#define CCGR_AONRDC 26 135#define CCGR_WKUPRDC 27 136#define CCGR_FUSE 28 137#define CCGR_SNVH 29 138#define CCGR_SNVS 30 139#define CCGR_TRAC 31 140#define CCGR_SWO 32 141#define CCGR_IOCG 33 142#define CCGR_PIO1 34 143#define CCGR_PIO2 35 144#define CCGR_PIO3 36 145#define CCGR_PIO4 37 146#define CCGR_FIO1 38 147#define CCGR_FIO2 39 148#define CCGR_PIT1 40 149#define CCGR_PIT2 41 150#define CCGR_GPT1 42 151#define CCGR_GPT2 43 152#define CCGR_TPM1 44 153#define CCGR_TPM2 45 154#define CCGR_TPM3 46 155#define CCGR_TPM4 47 156#define CCGR_TPM5 48 157#define CCGR_TPM6 49 158#define CCGR_CAN1 50 159#define CCGR_CAN2 51 160#define CCGR_URT1 52 161#define CCGR_URT2 53 162#define CCGR_URT3 54 163#define CCGR_URT4 55 164#define CCGR_URT5 56 165#define CCGR_URT6 57 166#define CCGR_URT7 58 167#define CCGR_URT8 59 168#define CCGR_I2C1 60 169#define CCGR_I2C2 61 170#define CCGR_I2C3 62 171#define CCGR_I2C4 63 172#define CCGR_I2C5 64 173#define CCGR_I2C6 65 174#define CCGR_I2C7 66 175#define CCGR_I2C8 67 176#define CCGR_SPI1 68 177#define CCGR_SPI2 69 178#define CCGR_SPI3 70 179#define CCGR_SPI4 71 180#define CCGR_SPI5 72 181#define CCGR_SPI6 73 182#define CCGR_SPI7 74 183#define CCGR_SPI8 75 184#define CCGR_I3C1 76 185#define CCGR_I3C2 77 186#define CCGR_USDHC1 78 187#define CCGR_USDHC2 79 188#define CCGR_USDHC3 80 189#define CCGR_SAI1 81 190#define CCGR_SAI2 82 191#define CCGR_SAI3 83 192#define CCGR_W2AO 84 193#define CCGR_AO2W 85 194#define CCGR_MIPIC 86 195#define CCGR_MIPID 87 196#define CCGR_LVDS 88 197#define CCGR_LCDIF 89 198#define CCGR_PXP 90 199#define CCGR_ISI 91 200#define CCGR_NMED 92 201#define CCGR_DFI 93 202#define CCGR_DDRC 94 203#define CCGR_DFIC 95 204#define CCGR_DSSI 96 205#define CCGR_DBYP 97 206#define CCGR_DAPB 98 207#define CCGR_DRAMP 99 208#define CCGR_DCLKC 100 209#define CCGR_NCTL 101 210#define CCGR_GIC 102 211#define CCGR_NICAPB 103 212#define CCGR_USBC 104 213#define CCGR_USBT 105 214#define CCGR_HSIO 106 215#define CCGR_PDM 107 216#define CCGR_MQS1 108 217#define CCGR_MQS2 109 218#define CCGR_AXCVR 110 219#define CCGR_MECC 111 220#define CCGR_SPDIF 112 221#define CCGR_ML2NIC 113 222#define CCGR_MED2NIC 114 223#define CCGR_HSIO2NIC 115 224#define CCGR_W2NIC 116 225#define CCGR_NIC2W 117 226#define CCGR_NIC2DDR 118 227#define CCGR_HSIO32K 119 228#define CCGR_ENET1 120 229#define CCGR_ENETQOS 121 230#define CCGR_SYSCNT 122 231#define CCGR_TSTMR1 123 232#define CCGR_TSTMR2 124 233#define CCGR_TMC 125 234#define CCGR_PMRO 126 235#define CCGR_NUM 127 236 237#define SHARED_GPR_EXT_CLK 0 238#define SHARED_GPR_EXT_CLK_SEL_EXT1 0 239#define SHARED_GPR_EXT_CLK_SEL_EXT2 BIT(0) 240#define SHARED_GPR_EXT_CLK_SEL_EXT3 BIT(1) 241#define SHARED_GPR_EXT_CLK_SEL_EXT4 GENMASK(1, 0) 242 243#define SHARED_GPR_A55_CLK 1 244#define SHARED_GPR_A55_CLK_SEL_CCM 0 245#define SHARED_GPR_A55_CLK_SEL_PLL BIT(0) 246 247#define SHARED_GPR_DRAM_CLK 2 248#define SHARED_GPR_DRAM_CLK_SEL_PLL 0 249#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0) 250 251#define SHARED_GPR_NUM 8 252#define PRIVATE_GPR_NUM 8 253 254#define CLK_ROOT_STATUS_OFF BIT(24) 255#define CLK_ROOT_STATUS_CHANGING BIT(31) 256#define CLK_ROOT_MUX_MASK GENMASK(9, 8) 257#define CLK_ROOT_MUX_SHIFT 8 258#define CLK_ROOT_DIV_MASK GENMASK(7, 0) 259 260#define CCM_AUTHEN_LOCK_TZ BIT(11) 261#define CCM_AUTHEN_TZ_NS BIT(9) 262#define CCM_AUTHEN_TZ_USER BIT(8) 263#define CCM_AUTHEN_CPULPM_MODE BIT(2) 264#define CCM_AUTHEN_AUTO_CTRL BIT(3) 265 266#endif 267