1if ARM64
2
3config CMO_BY_VA_ONLY
4	bool "Force cache maintenance to be exclusively by VA"
5	depends on !SYS_DISABLE_DCACHE_OPS
6
7config ARMV8_SPL_EXCEPTION_VECTORS
8	bool "Install crash dump exception vectors"
9	depends on SPL
10	help
11	  The default exception vector table is only used for the crash
12	  dump, but still takes quite a lot of space in the image size.
13
14	  Say N here if you are running out of code space in the image
15	  and want to save some space at the cost of less debugging info.
16
17config ARMV8_MULTIENTRY
18        bool "Enable multiple CPUs to enter into U-Boot"
19
20config ARMV8_SET_SMPEN
21        bool "Enable data coherency with other cores in cluster"
22        help
23	  Say Y here if there is not any trust firmware to set
24	  CPUECTLR_EL1.SMPEN bit before U-Boot.
25
26	  For A53, it enables data coherency with other cores in the
27	  cluster, and for A57/A72, it enables receiving of instruction
28	  cache and TLB maintenance operations.
29	  Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
30	  for single core systems. Unfortunately write access to this
31	  register may be controlled by EL3/EL2 firmware. To be more
32	  precise, by default (if there is EL2/EL3 firmware running)
33	  this register is RO for NS EL1.
34	  This switch can be used to avoid writing to CPUECTLR_EL1,
35	  it can be safely enabled when EL2/EL3 initialized SMPEN bit
36	  or when CPU implementation doesn't include that register.
37
38config ARMV8_SWITCH_TO_EL1
39	bool "Enable switching to running in EL1"
40	help
41	  In some circumstances we need to switch to running in EL1.
42	  Enable this option to have U-Boot switch to EL1.
43
44config ARMV8_SPIN_TABLE
45	bool "Support spin-table enable method"
46	depends on ARMV8_MULTIENTRY && OF_LIBFDT
47	help
48	  Say Y here to support "spin-table" enable method for booting Linux.
49
50	  To use this feature, you must do:
51	    - Specify enable-method = "spin-table" in each CPU node in the
52	      Device Tree you are using to boot the kernel
53	    - Bring secondary CPUs into U-Boot proper in a board specific
54	      manner.  This must be done *after* relocation.  Otherwise, the
55	      secondary CPUs will spin in unprotected memory area because the
56	      master CPU protects the relocated spin code.
57
58	  U-Boot automatically does:
59	    - Set "cpu-release-addr" property of each CPU node
60	      (overwrites it if already exists).
61	    - Reserve the code for the spin-table and the release address
62	      via a /memreserve/ region in the Device Tree.
63
64menu "ARMv8 secure monitor firmware"
65config ARMV8_SEC_FIRMWARE_SUPPORT
66	bool "Enable ARMv8 secure monitor firmware framework support"
67	select FIT
68	select OF_LIBFDT
69	help
70	  This framework is aimed at making secure monitor firmware load
71	  process brief.
72	  Note: Only FIT format image is supported.
73	  You should prepare and provide the below information:
74	    - Address of secure firmware.
75	    - Address to hold the return address from secure firmware.
76	    - Secure firmware FIT image related information.
77	      Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME
78	    - The target exception level that secure monitor firmware will
79	      return to.
80
81config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
82	bool "Enable ARMv8 secure monitor firmware framework support for SPL"
83	depends on SPL
84	select SPL_FIT
85	select SPL_OF_LIBFDT
86	help
87	  Say Y here to support this framework in SPL phase.
88
89config SPL_RECOVER_DATA_SECTION
90	bool "save/restore SPL data section"
91	depends on SPL
92	help
93	  Say Y here to save SPL data section for cold boot, and restore
94	  at warm boot in SPL phase.
95
96config SEC_FIRMWARE_ARMV8_PSCI
97	bool "PSCI implementation in secure monitor firmware"
98	depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
99	depends on ARMV8_PSCI=n
100	help
101	  This config enables the ARMv8 PSCI implementation in secure monitor
102	  firmware. This is a private PSCI implementation and different from
103	  those implemented under the common ARMv8 PSCI framework.
104
105config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
106	bool "ARMv8 secure monitor firmware ERET address byteorder swap"
107	depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
108	help
109	  Say Y here when the endianness of the register or memory holding the
110	  Secure firmware exception return address is different with core's.
111
112endmenu
113
114config PSCI_RESET
115	bool "Use PSCI for reset and shutdown"
116	default y
117	select ARM_SMCCC if OF_CONTROL
118	depends on !ARCH_APPLE && !ARCH_BCM283X && !ARCH_EXYNOS7 && \
119		   !TARGET_LS2080AQDS && \
120		   !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
121		   !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
122		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
123		   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
124		   !TARGET_LS1012AFRWY && \
125		   !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
126		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
127		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
128		   !TARGET_LS1046AFRWY && \
129		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
130		   !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
131		   !ARCH_UNIPHIER
132	help
133	  Most armv8 systems have PSCI support enabled in EL3, either through
134	  ARM Trusted Firmware or other firmware.
135
136	  On these systems, we do not need to implement system reset manually,
137	  but can instead rely on higher level firmware to deal with it.
138
139	  Select Y here to make use of PSCI calls for system reset
140
141config SYS_HAS_ARMV8_SECURE_BASE
142	bool
143
144config ARMV8_PSCI
145	bool "Enable PSCI support" if EXPERT
146	help
147	  PSCI is Power State Coordination Interface defined by ARM.
148	  The PSCI in U-Boot provides a general framework and each platform
149	  can implement their own specific PSCI functions.
150	  Say Y here to enable PSCI support on ARMv8 platform.
151
152config ARMV8_PSCI_NR_CPUS
153	int "Maximum supported CPUs for PSCI"
154	depends on ARMV8_PSCI
155	default 4
156	help
157	  The maximum number of CPUs supported in the PSCI firmware.
158	  It is no problem to set a larger value than the number of CPUs in
159	  the actual hardware implementation.
160
161config ARMV8_PSCI_CPUS_PER_CLUSTER
162	int "Number of CPUs per cluster"
163	depends on ARMV8_PSCI
164	default 0
165	help
166	  The number of CPUs per cluster, suppose each cluster has same number
167	  of CPU cores, platforms with asymmetric clusters don't apply here.
168	  A value 0 or no definition of it works for single cluster system.
169	  System with multi-cluster should difine their own exact value.
170
171config ARMV8_PSCI_RELOCATE
172	bool "Relocate PSCI code"
173	depends on ARMV8_PSCI
174	depends on SYS_HAS_ARMV8_SECURE_BASE
175	help
176	  Relocate PSCI code, for example to a secure memory on the SoC. If not
177	  set, the PSCI sections are placed together with the u-boot and the
178	  regions will be marked as reserved before linux is started.
179
180config ARMV8_SECURE_BASE
181	hex "Secure address for PSCI image"
182	depends on ARMV8_PSCI_RELOCATE
183	default 0x18000000 if ARCH_LS1028A
184	help
185	  Address for placing the PSCI text, data and stack sections.
186
187
188config ARMV8_EA_EL3_FIRST
189	bool "External aborts and SError interrupt exception are taken in EL3"
190	help
191	  Exception handling at all exception levels for External Abort and
192	  SError interrupt exception are taken in EL3.
193
194menuconfig ARMV8_CRYPTO
195	bool "ARM64 Accelerated Cryptographic Algorithms"
196
197if ARMV8_CRYPTO
198
199config ARMV8_CE_SHA1
200	bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)"
201	default y if SHA1
202
203config ARMV8_CE_SHA256
204	bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)"
205	default y if SHA256
206
207endif
208
209endif
210