1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * ARM Cortex M3/M4/M7 SysTick timer driver 4 * (C) Copyright 2017 Renesas Electronics Europe Ltd 5 * 6 * Based on arch/arm/mach-stm32/stm32f1/timer.c 7 * (C) Copyright 2015 8 * Kamil Lulko, <kamil.lulko@gmail.com> 9 * 10 * Copyright 2015 ATS Advanced Telematics Systems GmbH 11 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> 12 * 13 * The SysTick timer is a 24-bit count down timer. The clock can be either the 14 * CPU clock or a reference clock. Since the timer will wrap around very quickly 15 * when using the CPU clock, and we do not handle the timer interrupts, it is 16 * expected that this driver is only ever used with a slow reference clock. 17 * 18 * The number of reference clock ticks that correspond to 10ms is normally 19 * defined in the SysTick Calibration register's TENMS field. However, on some 20 * devices this is wrong, so this driver allows the clock rate to be defined 21 * using CFG_SYS_HZ_CLOCK. 22 */ 23 24#include <common.h> 25#include <init.h> 26#include <time.h> 27#include <asm/global_data.h> 28#include <asm/io.h> 29#include <linux/bitops.h> 30 31DECLARE_GLOBAL_DATA_PTR; 32 33/* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */ 34#define SYSTICK_BASE 0xE000E010 35 36struct cm3_systick { 37 uint32_t ctrl; 38 uint32_t reload_val; 39 uint32_t current_val; 40 uint32_t calibration; 41}; 42 43#define TIMER_MAX_VAL 0x00FFFFFF 44#define SYSTICK_CTRL_EN BIT(0) 45/* Clock source: 0 = Ref clock, 1 = CPU clock */ 46#define SYSTICK_CTRL_CPU_CLK BIT(2) 47#define SYSTICK_CAL_NOREF BIT(31) 48#define SYSTICK_CAL_SKEW BIT(30) 49#define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF 50 51/* read the 24-bit timer */ 52static ulong read_timer(void) 53{ 54 struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE; 55 56 /* The timer counts down, therefore convert to an incrementing timer */ 57 return TIMER_MAX_VAL - readl(&systick->current_val); 58} 59 60int timer_init(void) 61{ 62 struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE; 63 u32 cal; 64 65 writel(TIMER_MAX_VAL, &systick->reload_val); 66 /* Any write to current_val reg clears it to 0 */ 67 writel(0, &systick->current_val); 68 69 cal = readl(&systick->calibration); 70 if (cal & SYSTICK_CAL_NOREF) 71 /* Use CPU clock, no interrupts */ 72 writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, &systick->ctrl); 73 else 74 /* Use external clock, no interrupts */ 75 writel(SYSTICK_CTRL_EN, &systick->ctrl); 76 77 /* 78 * If the TENMS field is inexact or wrong, specify the clock rate using 79 * CFG_SYS_HZ_CLOCK. 80 */ 81#if defined(CFG_SYS_HZ_CLOCK) 82 gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK; 83#else 84 gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100; 85#endif 86 87 gd->arch.tbl = 0; 88 gd->arch.tbu = 0; 89 gd->arch.lastinc = read_timer(); 90 91 return 0; 92} 93 94/* return milli-seconds timer value */ 95ulong get_timer(ulong base) 96{ 97 unsigned long long t = get_ticks() * 1000; 98 99 return (ulong)((t / gd->arch.timer_rate_hz)) - base; 100} 101 102unsigned long long get_ticks(void) 103{ 104 u32 now = read_timer(); 105 106 if (now >= gd->arch.lastinc) 107 gd->arch.tbl += (now - gd->arch.lastinc); 108 else 109 gd->arch.tbl += (TIMER_MAX_VAL - gd->arch.lastinc) + now; 110 111 gd->arch.lastinc = now; 112 113 return gd->arch.tbl; 114} 115 116ulong get_tbclk(void) 117{ 118 return gd->arch.timer_rate_hz; 119} 120