1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#include <autoconf.h> 14#include <platsupport/gen_config.h> 15 16#include <stdio.h> 17#include <assert.h> 18#include <errno.h> 19#include <stdlib.h> 20#include <utils/util.h> 21#include <utils/arith.h> 22#include <utils/stringify.h> 23#include <utils/attribute.h> 24 25#include <platsupport/io.h> 26#include <platsupport/mux.h> 27#include <platsupport/plat/mux.h> 28#include <platsupport/gpio.h> 29#include <platsupport/plat/gpio.h> 30 31#include "mux_gpio_priv.h" 32#include "../../services.h" 33 34/** @file TK1 Mux driver. 35 * 36 * This file contains routines that manipulate the TK1 mux controller and set 37 * up the signals on pins. 38 * 39 * PREREQUISITES: 40 * This driver currently assumes that the MMIO registers it accesses are mapped 41 * as strongly ordered and uncached. The driver makes no attempts whatsoever at 42 * managing the write buffer or managing ordering of reads and writes. 43 */ 44 45#define MUX_REG_LOCK_SHIFT (7) 46#define MUX_REG_OPEN_DRAIN_SHIFT (6) 47#define MUX_REG_ENABLE_SHIFT (5) 48#define MUX_REG_TRISTATE_SHIFT (4) 49#define MUX_REG_PUPD_SHIFT (2) 50#define MUX_REG_PUPD_MASK (0x3) 51#define MUX_REG_SFIO_SELECT_SHIFT (0) 52#define MUX_REG_SFIO_SELECT_MASK (0x3) 53 54#define MUX_REG_PUPD_NORMAL (0) 55#define MUX_REG_PUPD_PULLDOWN (1) 56#define MUX_REG_PUPD_PULLUP (2) 57 58#define MUX_REG_TRISTATE_NORMAL (0) 59#define MUX_REG_TRISTATE_TRISTATE (1) 60 61/* Throughout this driver, the terms "pad" and "pin" are interchangeable. 62 * 63 * Each pin's input and output buffers are distinct and can be enabled 64 * separately and operated concurrently (to support bidirectional signals). 65 * 66 * So we need to specify for each pin whether one, or both (or neither) of the 67 * buffers needs to be enabled. 68 * 69 * Furthermore, each pin's output buffer can be driven by one of several output 70 * drivers: push-pull, open-drain, high-z, weak-pullup, weak-pulldown. 71 */ 72#define P_IN BIT(0) 73#define P_PUSHPULL BIT(6) 74#define P_BOTH (P_IN | P_PUSHPULL) 75#define P_OPEN_DRAIN BIT(2) 76#define P_TRISTATE BIT(3) 77#define P_PULLUP BIT(4) 78#define P_PULLDOWN BIT(5) 79 80#ifdef CONFIG_DEBUG_BUILD 81#define PINMAP_COMPOSE_NAME(_name) .name = STRINGIFY(_n), 82#else 83#define PINMAP_COMPOSE_NAME(_name) 84#endif 85 86#define PINMAP_PINDESC(_gp, _mro, _msv, _in_out) \ 87 { \ 88 .gpio_pin = _gp, .mux_reg_index = _mro, .mux_sfio_value = _msv, \ 89 .flags = _in_out \ 90 } 91 92#define PINMAP_NULLDESC PINMAP_PINDESC(-1, -1, 0xF, 0) 93 94#define PINMAP_1PIN(_n, _gp0, _mro0, _msv0, _io0) \ 95 [_n] = { \ 96 PINMAP_COMPOSE_NAME(_n) \ 97 { \ 98 PINMAP_PINDESC(_gp0, _mro0, _msv0, _io0), \ 99 PINMAP_NULLDESC, PINMAP_NULLDESC, PINMAP_NULLDESC, PINMAP_NULLDESC, \ 100 PINMAP_NULLDESC, PINMAP_NULLDESC, PINMAP_NULLDESC \ 101 } \ 102 } 103 104#define PINMAP_2PIN(_n, _gp0, _mro0, _msv0, _io0, _gp1, _mro1, _msv1, _io1) \ 105 [_n] = { \ 106 PINMAP_COMPOSE_NAME(_n) \ 107 { \ 108 PINMAP_PINDESC(_gp0, _mro0, _msv0, _io0), \ 109 PINMAP_PINDESC(_gp1, _mro1, _msv1, _io1), \ 110 PINMAP_NULLDESC, PINMAP_NULLDESC, PINMAP_NULLDESC, PINMAP_NULLDESC, \ 111 PINMAP_NULLDESC, PINMAP_NULLDESC \ 112 } \ 113 } 114 115#define PINMAP_3PIN(_n, _gp0, _mro0, _msv0, _io0, _gp1, _mro1, _msv1, _io1, _gp2, _mro2, _msv2, _io2) \ 116 [_n] = { \ 117 PINMAP_COMPOSE_NAME(_n) \ 118 { \ 119 PINMAP_PINDESC(_gp0, _mro0, _msv0, _io0), \ 120 PINMAP_PINDESC(_gp1, _mro1, _msv1, _io1), \ 121 PINMAP_PINDESC(_gp2, _mro2, _msv2, _io2), \ 122 PINMAP_NULLDESC, PINMAP_NULLDESC, PINMAP_NULLDESC, PINMAP_NULLDESC, \ 123 PINMAP_NULLDESC \ 124 } \ 125 } 126 127#define PINMAP_4PIN(_n, _gp0, _mro0, _msv0, _io0, _gp1, _mro1, _msv1, _io1, _gp2, _mro2, _msv2, _io2, _gp3, _mro3, _msv3, _io3) \ 128 [_n] = { \ 129 PINMAP_COMPOSE_NAME(_n) \ 130 { \ 131 PINMAP_PINDESC(_gp0, _mro0, _msv0, _io0), \ 132 PINMAP_PINDESC(_gp1, _mro1, _msv1, _io1), \ 133 PINMAP_PINDESC(_gp2, _mro2, _msv2, _io2), \ 134 PINMAP_PINDESC(_gp3, _mro3, _msv3, _io3), \ 135 PINMAP_NULLDESC, PINMAP_NULLDESC, PINMAP_NULLDESC, PINMAP_NULLDESC \ 136 } \ 137 } 138 139typedef struct tk1_mux_feature_pinmap_ { 140#ifdef CONFIG_DEBUG_BUILD 141 const char *name; 142#endif 143 struct tk1_mux_pin_desc { 144 uint32_t flags; 145 int16_t gpio_pin, mux_reg_index; 146 uint8_t mux_sfio_value; 147 } pins[8]; 148} tk1_mux_feature_pinmap_t; 149 150static inline const char *get_feature_name_string(tk1_mux_feature_pinmap_t *var) 151{ 152#ifdef CONFIG_DEBUG_BUILD 153 return var->name; 154#else 155 return "<Unknown>"; 156#endif 157} 158 159/* Array of descriptors for each controller that we may want to enable. 160 * 161 * Each descriptor has a list of pins that the controller sends and receives 162 * signals on. Each of the pins' required configuration parameters is also 163 * given. 164 * 165 * Basically, to add support for a new mux feature, just fill out a new entry 166 * in this list. 167 */ 168tk1_mux_feature_pinmap_t pinmaps[NMUX_FEATURES] = { 169 /* UARTs are a 2 or 4 signal pinout: RTS, CTS, TX, RX. */ 170 PINMAP_2PIN(MUX_FEATURE_UARTA, GPIO_PS1, MUX_PAD_KB_ROW9_PS1, 3, P_BOTH, GPIO_PS2, MUX_PAD_KB_ROW10_PS2, 3, P_BOTH), 171 PINMAP_4PIN(MUX_FEATURE_UARTB, GPIO_PC3, MUX_PAD_UART2_RXD_PC3, 0, P_BOTH, 172 GPIO_PC2, MUX_PAD_UART2_TXD_PC2, 0, P_BOTH, 173 GPIO_PJ6, MUX_PAD_UART2_RTS_N_PJ6, 1, P_BOTH, 174 GPIO_PJ5, MUX_PAD_UART2_CTS_N_PJ5, 1, P_BOTH), 175 PINMAP_4PIN(MUX_FEATURE_UARTC, GPIO_PW6, MUX_PAD_UART3_TXD_PW6, 0, P_BOTH, 176 GPIO_PW7, MUX_PAD_UART3_RXD_PW7, 0, P_BOTH, 177 GPIO_PA1, MUX_PAD_UART3_CTS_N_PA1, 0, P_BOTH, 178 GPIO_PC0, MUX_PAD_UART3_RTS_N_PC0, 0, P_BOTH), 179 PINMAP_4PIN(MUX_FEATURE_UARTD, GPIO_PJ7, MUX_PAD_PJ7, 0, P_BOTH, 180 GPIO_PB0, MUX_PAD_PB0, 0, P_BOTH, 181 GPIO_PB1, MUX_PAD_PB1, 0, P_BOTH, 182 GPIO_PK7, MUX_PAD_PK7, 0, P_BOTH), 183 184 /* SPI is a 4 signal pinout: CS, SCLK, MOSI, MISO. 185 * SPI1 is a special case, though I don't recall why. 186 */ 187 PINMAP_3PIN(MUX_FEATURE_SPI1, 188 GPIO_PY0, MUX_PAD_ULPI_CLK_PY0, 0, P_BOTH, 189 GPIO_PY1, MUX_PAD_ULPI_DIR_PY1, 0, P_BOTH, 190 GPIO_PY2, MUX_PAD_ULPI_NXT_PY2, 0, P_BOTH), 191 PINMAP_4PIN(MUX_FEATURE_SPI2, GPIO_PO5, MUX_PAD_ULPI_DATA4_PO5, 0, P_BOTH, 192 GPIO_PO6, MUX_PAD_ULPI_DATA5_PO6, 0, P_BOTH, 193 GPIO_PO7, MUX_PAD_ULPI_DATA6_PO7, 0, P_BOTH, 194 GPIO_PO0, MUX_PAD_ULPI_DATA7_PO0, 0, P_BOTH), 195 PINMAP_4PIN(MUX_FEATURE_SPI3, GPIO_PO1, MUX_PAD_ULPI_DATA0_PO1, 0, P_BOTH, 196 GPIO_PO2, MUX_PAD_ULPI_DATA1_PO2, 0, P_BOTH, 197 GPIO_PO3, MUX_PAD_ULPI_DATA2_PO3, 0, P_BOTH, 198 GPIO_PO4, MUX_PAD_ULPI_DATA3_PO4, 0, P_BOTH), 199 PINMAP_4PIN(MUX_FEATURE_SPI4, GPIO_PG4, MUX_PAD_PG4, 3, P_BOTH, 200 GPIO_PG5, MUX_PAD_PG5, 3, P_BOTH, 201 GPIO_PG6, MUX_PAD_PG6, 3, P_BOTH, 202 GPIO_PG7, MUX_PAD_PG7, 3, P_BOTH), 203 204 /* These are being mux settings to be used to configure the pins in GPIO 205 * mode, which means that the SFIO function we select is irrelevant. 206 * 207 * Just enable both the input and output buffers, and select the SFIO 208 * function that the firmware places the pin into by default upon #RESET. 209 */ 210 PINMAP_1PIN(MUX_FEATURE_GPIO_PS3, GPIO_PS3, MUX_PAD_KB_ROW11_PS3, 0, P_BOTH), 211 PINMAP_1PIN(MUX_FEATURE_GPIO_PS4, GPIO_PS4, MUX_PAD_KB_ROW12_PS4, 0, P_BOTH), 212 PINMAP_1PIN(MUX_FEATURE_GPIO_PR0, GPIO_PR0, MUX_PAD_KB_ROW0_PR0, 0, P_BOTH), 213 PINMAP_1PIN(MUX_FEATURE_GPIO_PR6, GPIO_PR6, MUX_PAD_KB_ROW6_PR6, 0, P_BOTH), 214 215 PINMAP_1PIN(MUX_FEATURE_GPIO_PS5, GPIO_PS5, MUX_PAD_KB_ROW13_PS5, 0, P_BOTH), 216 PINMAP_1PIN(MUX_FEATURE_GPIO_PT0, GPIO_PT0, MUX_PAD_KB_ROW16_PT0, 0, P_BOTH), 217 PINMAP_1PIN(MUX_FEATURE_GPIO_PS6, GPIO_PS6, MUX_PAD_KB_ROW14_PS6, 0, P_BOTH), 218 PINMAP_1PIN(MUX_FEATURE_GPIO_PS2, GPIO_PS2, MUX_PAD_KB_ROW10_PS2, 0, P_BOTH), 219 220 PINMAP_1PIN(MUX_FEATURE_GPIO_PA3, GPIO_PA3, MUX_PAD_DAP2_SCLK_PA3, 0, P_IN), 221 222 PINMAP_2PIN(MUX_FEATURE_I2C0, GPIO_PC4, MUX_PAD_GEN1_I2C_SCL_PC4, 0, P_IN | P_OPEN_DRAIN, 223 GPIO_PC5, MUX_PAD_GEN1_I2C_SDA_PC5, 0, P_IN | P_OPEN_DRAIN), 224 PINMAP_2PIN(MUX_FEATURE_I2C1, GPIO_PT5, MUX_PAD_GEN2_I2C_SCL_PT5, 0, P_IN | P_OPEN_DRAIN, 225 GPIO_PT6, MUX_PAD_GEN2_I2C_SDA_PT6, 0, P_IN | P_OPEN_DRAIN), 226 PINMAP_2PIN(MUX_FEATURE_I2C2, GPIO_PBB1, MUX_PAD_CAM_I2C_SCL_PBB1, 1, P_IN | P_OPEN_DRAIN, 227 GPIO_PBB2, MUX_PAD_CAM_I2C_SDA_PBB2, 1, P_IN | P_OPEN_DRAIN), 228 PINMAP_2PIN(MUX_FEATURE_I2C3, GPIO_PV4, MUX_PAD_DDC_SCL_PV4, 0, P_IN, 229 GPIO_PV5, MUX_PAD_DDC_SDA_PV5, 0, P_IN), 230 231 PINMAP_1PIN(MUX_FEATURE_GPIO_PC4, GPIO_PC4, MUX_PAD_GEN1_I2C_SCL_PC4, 0, P_BOTH), 232 PINMAP_1PIN(MUX_FEATURE_GPIO_PC5, GPIO_PC5, MUX_PAD_GEN1_I2C_SDA_PC5, 0, P_BOTH), 233 PINMAP_1PIN(MUX_FEATURE_GPIO_PBB1, GPIO_PBB1, MUX_PAD_GEN2_I2C_SCL_PT5, 0, P_BOTH), 234 PINMAP_1PIN(MUX_FEATURE_GPIO_PBB2, GPIO_PBB2, MUX_PAD_GEN2_I2C_SDA_PT6, 0, P_BOTH), 235 236 /* This is a configuration that overloads UARTB's RTS and CTS pins to allow 237 * us to use them as GPIO outputs. 238 * 239 * I was using them so I could sample measure the IRQ incoming and ACK times 240 * of the PPM IRQ in the quadcopter repo. This can be removed, but it also 241 * doesn't harm anything by being here. 242 */ 243 PINMAP_2PIN(MUX_FEATURE_PPM_MIRROR, 244 GPIO_PJ6, MUX_PAD_UART2_RTS_N_PJ6, 1, P_PUSHPULL, 245 GPIO_PJ5, MUX_PAD_UART2_CTS_N_PJ5, 1, P_PUSHPULL) 246}; 247 248typedef struct tegra_mux_state { 249 volatile uint32_t *pinmux_misc; 250 volatile uint32_t *pinmux_aux; 251 gpio_sys_t *gpio_sys; 252} tegra_mux_state_t; 253 254static const tegra_mux_state_t *tk1_mux_get_priv(const mux_sys_t *mux_sys) 255{ 256 assert(mux_sys != NULL); 257 return (const tegra_mux_state_t *)mux_sys->priv; 258} 259 260static volatile uint32_t *tk1_mux_get_group_reg_handle_for_pin(const mux_sys_t *ms, int mux_reg_index) 261{ 262 volatile uint32_t *ret; 263 int group_offset; 264 265 ret = tk1_mux_get_priv(ms)->pinmux_misc; 266 assert(ret != NULL); 267 group_offset = tk1_mux_get_group_offset_for_pin(mux_reg_index); 268 assert(group_offset > 0); 269 return &ret[group_offset / sizeof(uint32_t)]; 270} 271 272static void tk1_mux_set_drive_strength_for_pin(const mux_sys_t *ms, 273 int mux_reg_index, 274 uint8_t drive_up_strength, 275 uint8_t drive_down_strength) 276{ 277 volatile uint32_t *reg; 278 int group_offset; 279 uint32_t drup_mask, drup_shift, drdown_mask, drdown_shift; 280 281 reg = tk1_mux_get_group_reg_handle_for_pin(ms, mux_reg_index); 282 group_offset = tk1_mux_get_group_offset_for_pin(mux_reg_index); 283 if (group_offset < 0) { 284 /* Return early if there is no group configuration register for this 285 * pin. 286 */ 287 return; 288 } 289 ZF_LOGD("Group off 0x%x: previous val: 0x%x.", group_offset, *reg); 290 291 drup_shift = tk1_mux_get_bitinfo_for_group(group_offset, BITOFF_DRIVEUP); 292 drup_mask = tk1_mux_get_bitinfo_for_group(group_offset, BITMASK_DRIVEUP); 293 drdown_shift = tk1_mux_get_bitinfo_for_group(group_offset, BITOFF_DRIVEDOWN); 294 drdown_mask = tk1_mux_get_bitinfo_for_group(group_offset, BITMASK_DRIVEDOWN); 295 296 *reg &= ~(drup_mask << drup_shift); 297 *reg &= ~(drdown_mask << drdown_shift); 298 299 *reg |= (drive_up_strength & drup_mask) << drup_shift; 300 *reg |= (drive_down_strength & drdown_mask) << drdown_shift; 301 ZF_LOGD("Group off 0x%x: new val: 0x%x.", group_offset, *reg); 302} 303 304static int tk1_mux_set_pin_params(const mux_sys_t *mux, struct tk1_mux_pin_desc *desc, 305 enum mux_gpio_dir mux_gpio_dir) 306{ 307 uint32_t regval, requiredval; 308 const tegra_mux_state_t *s = tk1_mux_get_priv(mux); 309 310 regval = s->pinmux_aux[desc->mux_reg_index] & 0xFF; 311 312 /* There is a "lock" bit in each of the mux registers. This lock bit 313 * prevents us from modifying the configuration of the pads. 314 * 315 * If the lock bit is UNSET, we can just reconfigure the pad. 316 * If the lock bit is SET however, we can't reconfigure the pad. 317 */ 318 requiredval = ((desc->mux_sfio_value & MUX_REG_SFIO_SELECT_MASK) << MUX_REG_SFIO_SELECT_SHIFT); 319 320 /* Enable input buffer if P_IN */ 321 if (desc->flags & P_IN) { 322 requiredval |= BIT(MUX_REG_ENABLE_SHIFT); 323 } 324 /* Set output driver to pushpull if P_PUSHPULL. */ 325 if (desc->flags & P_PUSHPULL) { 326 if (desc->flags & P_OPEN_DRAIN) { 327 ZF_LOGE("Can't enable both pushpull and open-drain output drivers."); 328 return -1; 329 } 330 if (desc->flags & P_TRISTATE) { 331 ZF_LOGE("Can't enable both pushpull and tristate output drivers."); 332 return -1; 333 } 334 if (desc->flags & P_PULLUP || desc->flags & P_PULLDOWN) { 335 ZF_LOGE("Can't enable both pushpull and pull-resistor output drivers."); 336 return -1; 337 } 338 requiredval &= ~BIT(MUX_REG_TRISTATE_SHIFT); 339 } 340 if (desc->flags & P_TRISTATE) { 341 if (desc->flags & P_OPEN_DRAIN) { 342 ZF_LOGE("Can't enable both tristate and open-drain output drivers."); 343 return -1; 344 } 345 if (desc->flags & P_PUSHPULL) { 346 ZF_LOGE("Can't enable both tristate and pushpull output drivers."); 347 return -1; 348 } 349 if (desc->flags & P_PULLUP || desc->flags & P_PULLDOWN) { 350 ZF_LOGE("Can't enable both tristate and pull-resistor output drivers."); 351 return -1; 352 } 353 requiredval |= BIT(MUX_REG_TRISTATE_SHIFT); 354 } 355 if (desc->flags & P_PULLUP || desc->flags & P_PULLDOWN) { 356 if ((desc->flags & P_PULLUP) && (desc->flags & P_PULLDOWN)) { 357 ZF_LOGE("Can't enable both pullup and pulldown at once."); 358 return -1; 359 } 360 if (desc->flags & P_OPEN_DRAIN) { 361 ZF_LOGE("Can't enable both pullup and opendrain output drivers."); 362 return -1; 363 } 364 if (desc->flags & P_TRISTATE) { 365 ZF_LOGE("Can't enable both pullup and tristate output drivers."); 366 return -1; 367 } 368 requiredval &= ~(MUX_REG_PUPD_MASK << MUX_REG_PUPD_SHIFT); 369 requiredval |= ((desc->flags & P_PULLUP) 370 ? MUX_REG_PUPD_PULLUP 371 : MUX_REG_PUPD_PULLDOWN) 372 << MUX_REG_PUPD_SHIFT; 373 } 374 if (desc->flags & P_OPEN_DRAIN) { 375 if (desc->flags & P_PUSHPULL) { 376 ZF_LOGE("Can't enable both open-drain and pushpull output drivers."); 377 return -1; 378 } 379 if (desc->flags & P_TRISTATE) { 380 ZF_LOGE("Can't enable both open-drain and tristate output drivers."); 381 return -1; 382 } 383 if (desc->flags & P_PULLUP || desc->flags & P_PULLDOWN) { 384 ZF_LOGE("Can't enable both open-drain and pullup/pulldown output drivers."); 385 return -1; 386 } 387 requiredval |= BIT(MUX_REG_OPEN_DRAIN_SHIFT); 388 } 389 390 if (regval == requiredval) { 391 return 0; 392 } 393 394 if (regval & BIT(MUX_REG_LOCK_SHIFT)) { 395 /* IF the lock bit is set, we can't change it */ 396 ZF_LOGE("Failed to change pin SFIO function to %d: Bit is locked.", 397 desc->mux_sfio_value); 398 return -1; 399 } 400 401 s->pinmux_aux[desc->mux_reg_index] = requiredval; 402 /* Just in case the writes are being silently ignored. */ 403 assert(s->pinmux_aux[desc->mux_reg_index] == requiredval); 404 return 0; 405} 406 407static bool pin_is_pull_up_by_default(int mux_reg_index) 408{ 409 /* This is a list of the pins whose default state on #RESET is Pull-up. */ 410 const uint16_t pull_up_pin_indexes[] = { 411 MUX_PAD_ULPI_DATA0_PO1, MUX_PAD_ULPI_DATA1_PO2, MUX_PAD_ULPI_DATA2_PO3, 412 MUX_PAD_ULPI_DATA3_PO4, MUX_PAD_ULPI_DATA4_PO5, MUX_PAD_ULPI_DATA5_PO6, 413 MUX_PAD_ULPI_DATA6_PO7, MUX_PAD_ULPI_DATA7_PO0, MUX_PAD_SDMMC1_CMD_PZ1, 414 MUX_PAD_SDMMC1_DAT3_PY4, MUX_PAD_SDMMC1_DAT2_PY5, MUX_PAD_SDMMC1_DAT1_PY6, 415 MUX_PAD_SDMMC1_DAT0_PY7, 416 MUX_PAD_UART2_RXD_PC3, MUX_PAD_UART2_TXD_PC2, MUX_PAD_UART2_RTS_N_PJ6, 417 MUX_PAD_UART2_CTS_N_PJ5, MUX_PAD_UART3_TXD_PW6, MUX_PAD_UART3_RXD_PW7, 418 MUX_PAD_UART3_RTS_N_PC0, MUX_PAD_UART3_RTS_N_PC0, 419 MUX_PAD_PC7, MUX_PAD_PI5, MUX_PAD_PI7, MUX_PAD_PK0, MUX_PAD_PJ0, 420 MUX_PAD_PJ2, MUX_PAD_PK3, MUX_PAD_PK4, MUX_PAD_PK2, MUX_PAD_PI3, 421 MUX_PAD_PI6, MUX_PAD_PH4, MUX_PAD_PH6, MUX_PAD_PH7, MUX_PAD_PI0, 422 MUX_PAD_PI1, MUX_PAD_PI2, MUX_PAD_SDMMC4_CMD_PT7, MUX_PAD_SDMMC4_DAT0_PAA0, 423 MUX_PAD_SDMMC4_DAT1_PAA1, MUX_PAD_SDMMC4_DAT2_PAA2, MUX_PAD_SDMMC4_DAT3_PAA3, 424 MUX_PAD_SDMMC4_DAT4_PAA4, MUX_PAD_SDMMC4_DAT5_PAA5, MUX_PAD_SDMMC4_DAT6_PAA6, 425 MUX_PAD_SDMMC4_DAT7_PAA7, 426 MUX_PAD_CAM_MCLK_PCC0, 427 MUX_PAD_PCC1, MUX_PAD_PCC2, MUX_PAD_JTAG_RTCK, 428 MUX_PAD_KB_COL0_PQ0, MUX_PAD_KB_COL1_PQ1, MUX_PAD_KB_COL2_PQ2, 429 MUX_PAD_KB_COL3_PQ3, MUX_PAD_KB_COL4_PQ4, MUX_PAD_KB_COL5_PQ5, 430 MUX_PAD_KB_COL6_PQ6, MUX_PAD_KB_COL7_PQ7, 431 MUX_PAD_SPDIF_OUT_PK5, 432 MUX_PAD_GPIO_X3_AUD_PX3, 433 MUX_PAD_DVFS_CLK_PX2, 434 MUX_PAD_GPIO_X5_AUD_PX5, MUX_PAD_GPIO_X6_AUD_PX6, 435 MUX_PAD_SDMMC1_CMD_PZ1, MUX_PAD_SDMMC3_DAT0_PB7, MUX_PAD_SDMMC3_DAT1_PB6, 436 MUX_PAD_SDMMC3_DAT2_PB5, MUX_PAD_SDMMC3_DAT3_PB4, 437 MUX_PAD_SDMMC1_WP_N_PV3, MUX_PAD_SDMMC3_CD_N_PV2, 438 MUX_PAD_GPIO_W2_AUD_PW2, MUX_PAD_GPIO_W3_AUD_PW3 439 }; 440 441 for (int i = 0; i < ARRAY_SIZE(pull_up_pin_indexes); i++) { 442 /* Each register is 32 bits, so indexes need to be multiplied by 4 to 443 * get the byte-offset from the base. 444 */ 445 if (pull_up_pin_indexes[i] == mux_reg_index * 4) { 446 return true; 447 } 448 } 449 return false; 450} 451 452static void tk1_mux_set_pin_unused(volatile uint32_t *regs, uint16_t mux_reg_index, 453 bool enable_input_buffer) 454{ 455 int pupd_val; 456 457 /* TK1 TRM, sec 8.10.3 "Unused Pins": 458 * "For each unused MPIO, assert its tristate and disable its input " 459 * buffer. For pins whose internal pull-up is enabled during power- 460 * on-reset, assert the internal pull-up. Otherwise, assert the internal 461 * pull-down." 462 * 463 * Furthermore: 464 * 465 * TK1 TRM, sec 8.4.1 "Per Pad Options": 466 * "Tristate (high-z) option: Disables or enables the pad���s output driver. 467 * This setting overrides any other functional setting and also whether pad 468 * is selected for SFIO or GPIO. Can be used when the pad direction changes 469 * or the pad is assigned to different SFIO to avoid glitches." 470 * 471 * So this function will set a given pin to its unused state by enabling 472 * its tristate mode (which is its output mode), and then either asserting 473 * pull-up or pull-down. 474 * 475 * This function will be used both to disable pins that are not being used, 476 * and also as an intermediate transition when changing the mux settings 477 * for a pin (as advised by the manual, in sec 8.4.1). 478 */ 479 480 /* See sec 8.10.3 above: if the pin is pull up on #RESET, then assert 481 * pull-up, else assert pull-down. 482 */ 483 if (pin_is_pull_up_by_default(mux_reg_index)) { 484 pupd_val = MUX_REG_PUPD_PULLUP; 485 } else { 486 pupd_val = MUX_REG_PUPD_PULLDOWN; 487 } 488 489 regs[mux_reg_index] = 0 490 /* Tristate on */ 491 | MUX_REG_TRISTATE_TRISTATE << MUX_REG_TRISTATE_SHIFT 492 /* Enable/disable the input buffer. 493 * 494 * We should disable it, but the problem is that if we 495 * disable the input buffer on the pin, and then later 496 * on somebody wants to use the pin as an GPIO input pin, 497 * it would mean that the GPIO driver would have to call 498 * down into the mux driver (this driver). 499 * 500 * But this driver already depends on the GPIO driver, so 501 * that would create a circular dependency. 502 * 503 * Thankfully, leaving the input buffer on shouldn't be 504 * detrimental because, according to the TRM sec 8.4.1, 505 * the tristate option overrides all other options. 506 */ 507 | (!!enable_input_buffer) << MUX_REG_ENABLE_SHIFT 508 /* Assert either pull-up or pull-down. */ 509 | pupd_val << MUX_REG_PUPD_SHIFT; 510} 511 512static int tk1_mux_feature_enable(const mux_sys_t *mux, mux_feature_t feat, 513 enum mux_gpio_dir mux_gpio_dir) 514{ 515 int error; 516 tk1_mux_feature_pinmap_t *map; 517 const tegra_mux_state_t *s = tk1_mux_get_priv(mux); 518 519 assert(feat < NMUX_FEATURES); 520 521 map = &pinmaps[feat]; 522 for (int i = 0; i < ARRAY_SIZE(map->pins); i++) { 523 /* Pin list is terminated by -1 as pin number. */ 524 if (map->pins[i].gpio_pin == -1) { 525 break; 526 } 527 528 ZF_LOGD("Feature enable: feat %d, Mux pad index 0x%x(offset 0x%x), GPIO %d. Reg state before 0x%x.", 529 feat, 530 map->pins[i].mux_reg_index, 531 map->pins[i].mux_reg_index * sizeof(uint32_t), 532 map->pins[i].gpio_pin, 533 s->pinmux_aux[map->pins[i].mux_reg_index]); 534 535 if (mux_gpio_dir == MUX_DIR_NOT_A_GPIO) { 536 /* According to TK1 TRM sec 8.4.1, we should set the pin to default 537 * values (asserting tristate) when we're reconfiguring it to a 538 * different SFIO, to prevent glitches during the configuration 539 * transition. 540 * 541 * If the SFIO function being changed to is the same though, 542 * we shouldn't call set_pin_unused() because that has to potential 543 * to unnecessarily pull the pin up or down according to its 544 * default #RESET voltage level. 545 */ 546 if ((s->pinmux_aux[map->pins[i].mux_reg_index] 547 & MUX_REG_SFIO_SELECT_MASK) != map->pins[i].mux_sfio_value) { 548 tk1_mux_set_pin_unused(s->pinmux_aux, 549 map->pins[i].mux_reg_index, true); 550 } 551 552 /* First, attempt to set the pin into SFIO mode IF it's going to be 553 * used to bring out an SFIO signal. 554 * 555 * If it'll be used to bring out a GPIO signal, leave it alone in 556 * whatever mode it was in, and let the GPIO driver set it up when 557 * the user tells it to. 558 */ 559 error = gpio_set_pad_mode(s->gpio_sys, map->pins[i].gpio_pin, 560 SFIO_MODE, 561 0 /* Doesn't matter for SFIO mode. */); 562 if (error) { 563 ZF_LOGE("Failed to set pin %d for feature %s. Aborting.", 564 i, get_feature_name_string(map)); 565 return -1; 566 } 567 } 568 569 /* Next set up the rest of the parameters. */ 570 error = tk1_mux_set_pin_params(mux, &map->pins[i], mux_gpio_dir); 571 if (error) { 572 ZF_LOGE("Failed to pinmux params for pin %d of feature %s. " 573 "Aborting.", 574 i, get_feature_name_string(map)); 575 return -1; 576 } 577 578 /* Set the drive strength divisor to 8 for moderate drive strength. */ 579 tk1_mux_set_drive_strength_for_pin(mux, 580 map->pins[i].mux_reg_index, 581 8, 8); 582 ZF_LOGD("Feature enable: feat %d, Mux pad index 0x%x(offset 0x%x), GPIO %d. Reg state AFTER 0x%x.", 583 feat, 584 map->pins[i].mux_reg_index, 585 map->pins[i].mux_reg_index * sizeof(uint32_t), 586 map->pins[i].gpio_pin, 587 s->pinmux_aux[map->pins[i].mux_reg_index]); 588 } 589 590 return 0; 591} 592 593static int tk1_mux_feature_disable(const mux_sys_t *mux, mux_feature_t feat) 594{ 595 tk1_mux_feature_pinmap_t *map; 596 const tegra_mux_state_t *s = tk1_mux_get_priv(mux); 597 598 assert(feat < NMUX_FEATURES); 599 600 map = &pinmaps[feat]; 601 for (int i = 0; i < ARRAY_SIZE(map->pins); i++) { 602 /* Pin list is terminated by -1 as pin number. */ 603 if (map->pins[i].gpio_pin == -1) { 604 break; 605 } 606 607 tk1_mux_set_pin_unused(s->pinmux_aux, map->pins[i].mux_reg_index, false); 608 } 609 610 return 0; 611} 612 613static void tk1_mux_set_all_pins_to_default_state(volatile uint32_t *mux_regs) 614{ 615 /* TODO: 616 * We should cycle through all valid pins here and call 617 * tk1_mux_set_pin_unused() on each one. 618 */ 619} 620 621int tegra_mux_init(volatile void *pinmux_misc, volatile void *pinmux_aux, 622 ps_io_ops_t *io_ops, 623 gpio_sys_t *gpio_sys, mux_sys_t *self) 624{ 625 int error; 626 tegra_mux_state_t *state; 627 628 if (!gpio_sys_valid(gpio_sys)) { 629 ZF_LOGE("Invalid GPIO driver instance handle."); 630 return -EINVAL; 631 }; 632 633 error = ps_malloc(&io_ops->malloc_ops, sizeof(*state), (void **)&state); 634 if (error != 0 || state == NULL) { 635 ZF_LOGE("Failed to alloc TK1 Mux instance internal state."); 636 return -1; 637 } 638 639 state->pinmux_misc = pinmux_misc; 640 state->pinmux_aux = pinmux_aux; 641 state->gpio_sys = gpio_sys; 642 643 self->priv = state; 644 self->feature_enable = &tk1_mux_feature_enable; 645 self->feature_disable = &tk1_mux_feature_disable; 646 647 tk1_mux_set_all_pins_to_default_state(tk1_mux_get_priv(self)->pinmux_aux); 648 649 ZF_LOGE("Mux misc for dbgcfg @vaddrs 0x%p, 0x%p: values 0x%x, 0x%x (offsets are 0x%x, 0x%x).", 650 tk1_mux_get_group_reg_handle_for_pin(self, MUX_PAD_GEN1_I2C_SCL_PC4), 651 tk1_mux_get_group_reg_handle_for_pin(self, MUX_PAD_CAM_I2C_SCL_PBB1), 652 *tk1_mux_get_group_reg_handle_for_pin(self, MUX_PAD_GEN1_I2C_SCL_PC4), 653 *tk1_mux_get_group_reg_handle_for_pin(self, MUX_PAD_CAM_I2C_SCL_PBB1), 654 tk1_mux_get_group_offset_for_pin(MUX_PAD_GEN1_I2C_SCL_PC4), 655 tk1_mux_get_group_offset_for_pin(MUX_PAD_CAM_I2C_SCL_PBB1)); 656 return 0; 657} 658 659int mux_sys_init(ps_io_ops_t *io_ops, void *dependencies, mux_sys_t *mux) 660{ 661 void *pinmux_misc_vaddr = NULL, *pinmux_aux_vaddr = NULL; 662 gpio_sys_t *gpio_sys = (gpio_sys_t *)dependencies; 663 664 pinmux_misc_vaddr = RESOURCE(io_ops, TK1_MUX_MISC); 665 if (pinmux_misc_vaddr == NULL) { 666 ZF_LOGE("Failed to map in pinmux_misc frame."); 667 return -1; 668 } 669 pinmux_aux_vaddr = RESOURCE(io_ops, TK1_MUX_AUX); 670 if (pinmux_aux_vaddr == NULL) { 671 ZF_LOGE("Failed to map in pinmux_aux frame."); 672 return -1; 673 } 674 675 return tegra_mux_init(pinmux_misc_vaddr, pinmux_aux_vaddr, io_ops, 676 gpio_sys, mux); 677} 678