1/*
2 * Copyright 2017, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12#pragma once
13
14#include <platsupport/timer.h>
15#include <platsupport/ltimer.h>
16
17#define DMTIMER2_PATH "/ocp/timer@48040000"
18#define DMTIMER3_PATH "/ocp/timer@48042000"
19
20#define DMT_REG_CHOICE 0
21#define DMT_IRQ_CHOICE 0
22
23static UNUSED timer_properties_t dmt_properties = {
24    .upcounter = false,
25    .timeouts = true,
26    .relative_timeouts = true,
27    .periodic_timeouts = true,
28    .bit_width = 32,
29    .irqs = 1
30};
31
32typedef struct {
33    char *fdt_path;
34    ltimer_callback_fn_t user_cb_fn;
35    void *user_cb_token;
36    ltimer_event_t user_cb_event;
37} dmt_config_t;
38
39struct dmt_map {
40    uint32_t tidr; // 00h TIDR Identification Register
41    uint32_t padding1[3];
42    uint32_t cfg; // 10h TIOCP_CFG Timer OCP Configuration Register
43    uint32_t padding2[3];
44    uint32_t tieoi; // 20h IRQ_EOI Timer IRQ End-Of-Interrupt Register
45    uint32_t tisrr; // 24h IRQSTATUS_RAW Timer IRQSTATUS Raw Register
46    uint32_t tisr; // 28h IRQSTATUS Timer IRQSTATUS Register
47    uint32_t tier; // 2Ch IRQENABLE_SET Timer IRQENABLE Set Register
48    uint32_t ticr; // 30h IRQENABLE_CLR Timer IRQENABLE Clear Register
49    uint32_t twer; // 34h IRQWAKEEN Timer IRQ Wakeup Enable Register
50    uint32_t tclr; // 38h TCLR Timer Control Register
51    uint32_t tcrr; // 3Ch TCRR Timer Counter Register
52    uint32_t tldr; // 40h TLDR Timer Load Register
53    uint32_t ttgr; // 44h TTGR Timer Trigger Register
54    uint32_t twps; // 48h TWPS Timer Write Posted Status Register
55    uint32_t tmar; // 4Ch TMAR Timer Match Register
56    uint32_t tcar1; // 50h TCAR1 Timer Capture Register
57    uint32_t tsicr; // 54h TSICR Timer Synchronous Interface Control Register
58    uint32_t tcar2; // 58h TCAR2 Timer Capture Register
59};
60
61typedef struct dmt {
62    /* set in init */
63    ps_io_ops_t ops;
64    ltimer_callback_fn_t user_cb_fn;
65    void *user_cb_token;
66    ltimer_event_t user_cb_event;  /* what are we being used for? */
67
68    /* set in fdt helper */
69    volatile struct dmt_map *hw;
70    pmem_region_t pmem;
71    irq_id_t irq_id;
72
73    /* set in setup */
74    uint32_t time_h;
75} dmt_t;
76
77int dmt_init(dmt_t *dmt, ps_io_ops_t ops, dmt_config_t config);
78int dmt_start(dmt_t *dmt);
79int dmt_stop(dmt_t *dmt);
80/* configure a timeout */
81int dmt_set_timeout(dmt_t *dmt, uint64_t ns, bool periodic);
82/* start the ticking timer */
83int dmt_start_ticking_timer(dmt_t *dmt);
84void dmt_handle_irq(void *data, ps_irq_acknowledge_fn_t acknowledge_fn, void *ack_data);
85/* return true if an overflow is pending */
86bool dmt_pending_overflow(dmt_t *dmt);
87/* return time */
88uint64_t dmt_get_time(dmt_t *dmt);
89void dmt_destroy(dmt_t *dmt);
90