1/*
2 * Copyright 2020, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the GNU General Public License version 2. Note that NO WARRANTY is provided.
8 * See "LICENSE_GPLv2.txt" for details.
9 *
10 * @TAG(DATA61_GPL)
11 */
12
13#pragma once
14
15#include "common.h"
16
17#define CONFIG_SYS_CACHELINE_SIZE 64
18
19#ifdef CONFIG_SYS_CACHELINE_SIZE
20#define ARCH_DMA_MINALIGN   CONFIG_SYS_CACHELINE_SIZE
21#else
22#define ARCH_DMA_MINALIGN   16
23#endif
24
25#define CONFIG_LIB_ETHDRIVER_RX_DESC_COUNT 128
26#define CONFIG_LIB_ETHDRIVER_TX_DESC_COUNT 128
27
28#define FDT_ADDR_T_NONE (-1U)
29
30#define GPIOD_REQUESTED     (1 << 0)    /* Requested/claimed */
31#define GPIOD_IS_OUT        (1 << 1)    /* GPIO is an output */
32#define GPIOD_IS_IN         (1 << 2)    /* GPIO is an input */
33#define GPIOD_ACTIVE_LOW    (1 << 3)    /* value has active low */
34#define GPIOD_IS_OUT_ACTIVE (1 << 4)    /* set output active */
35
36#define TX2_PADDR 0x02490000
37#define TX2_DEFAULT_MAC "\x00\x04\x4b\xc5\x67\x70"
38// #define TX2_DEFAULT_MAC "\x00\x04\x4b\xa5\x90\xeb"
39
40
41/* descriptor 0, 1 and 2 need to be written to in order to trigger dma */
42struct eqos_desc {
43    uint32_t des0; /* address of the packet */
44    uint32_t des1;
45    uint32_t des2; /* length of packet */
46    uint32_t des3; /* flags (interrupt, own, ld, etc) and length of packet */
47};
48
49#define EQOS_DESCRIPTORS_TX 256
50#define EQOS_DESCRIPTORS_RX 256
51
52/* descriptor flags */
53#define EQOS_DESC2_IOC      BIT(31)
54#define EQOS_DESC3_OWN      BIT(31)
55#define EQOS_DESC3_FD       BIT(29)
56#define EQOS_DESC3_LD       BIT(28)
57#define EQOS_DESC3_BUF1V    BIT(24)
58#define DWCEQOS_DMA_RDES3_INTE    BIT(30)
59
60#define EQOS_ALIGN(x,a)      __ALIGN_MASK((x),(typeof(x))(a)-1)
61#define EQOS_MAX_PACKET_SIZE    EQOS_ALIGN(1568, ARCH_DMA_MINALIGN)
62
63struct tx2_eth_data {
64    void *eth_dev;
65    uintptr_t tx_ring_phys;
66    uintptr_t rx_ring_phys;
67    volatile struct eqos_desc *tx_ring;
68    volatile struct eqos_desc *rx_ring;
69    unsigned int rx_size;
70    unsigned int tx_size;
71    void **rx_cookies;
72    unsigned int rx_remain;
73    unsigned int tx_remain;
74    void **tx_cookies;
75    unsigned int *tx_lengths;
76    /* track where the head and tail of the queues are for
77     * enqueueing buffers / checking for completions */
78    unsigned int rdt, rdh, tdt, tdh;
79};
80