1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#pragma once 14//PMC event definitions 15/* Note: there are lots of these. Only seemingly interesting ones -- that is, 16 * either core sel4bench events, or ones closely related -- are included here. 17 * Note2: events numbers are 32 bits long, and are divided into a cmask, flags 18 * umask and event ID bytes (see intel software developer manual for details), 19 * though most events will have cmask and flags equal to 0. Events with the same 20 * cmask, flags and ID, but differing masks, can usually be ORed together, in 21 * which case they'll be counted together. 22 * The USR and OS flags are set in sel4bench_set_count_event() regardless of the 23 * value in the event. 24 */ 25 26//Arch 27#define SEL4BENCH_EVENT_CYCLE_CORE 0x003C 28#define SEL4BENCH_EVENT_CYCLE_BUS 0x013C 29#define SEL4BENCH_EVENT_CACHE_LLC_ACCESS 0x4F2E 30#define SEL4BENCH_EVENT_CACHE_LLC_MISS 0x412E 31#define SEL4BENCH_EVENT_EXECUTE_INSTRUCTION 0x00C0 32#define SEL4BENCH_EVENT_EXECUTE_BRANCH 0x00C4 33#define SEL4BENCH_EVENT_BRANCH_MISPREDICT 0x00C5 34//event modifiers 35#define SEL4BENCH_IA32_MESI(X, EVENT) ((EVENT) | ((X) << 8)) 36#define SEL4BENCH_IA32_CORE(X, EVENT) ((EVENT) | ((X) << 14)) 37#define SEL4BENCH_IA32_PREFETCH(X, EVENT) ((EVENT) | ((X) << 12)) 38#define SEL4BENCH_IA32_CORE_SELF 0x1 39#define SEL4BENCH_IA32_CORE_ALL 0x3 40#define SEL4BENCH_IA32_PREFETCH_NONE 0x0 41#define SEL4BENCH_IA32_PREFETCH_ONLY 0x1 42#define SEL4BENCH_IA32_PREFETCH_ALL 0x3 43#define SEL4BENCH_IA32_M BIT(3) 44#define SEL4BENCH_IA32_E BIT(2) 45#define SEL4BENCH_IA32_S BIT(1) 46#define SEL4BENCH_IA32_I BIT(0) 47#define SEL4BENCH_IA32_CACHEMISS SEL4BENCH_IA32_I 48#define SEL4BENCH_IA32_CACHEHIT (SEL4BENCH_IA32_M | SEL4BENCH_IA32_E | SEL4BENCH_IA32_S) 49 50//Skylake uArch 51#define SEL4BENCH_IA32_SKYLAKE_EVENT_LD_BLOCKS 0xFF03 52#define SEL4BENCH_IA32_SKYLAKE_EVENT_LD_BLOCKS_PARTIAL 0xFF07 53#define SEL4BENCH_IA32_SKYLAKE_EVENT_DTLB_LOAD_MISSES 0xFF08 54#define SEL4BENCH_IA32_SKYLAKE_EVENT_INT_MISC_RECOVERY_CYCLES 0x010D 55#define SEL4BENCH_IA32_SKYLAKE_EVENT_INT_MISC_CLEAR_RESTEER_CYCLES 0x800D 56#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_ISSUED_ANY 0x010E 57#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_ISSUED_SLOW_LEA 0x200E 58#define SEL4BENCH_IA32_SKYLAKE_EVENT_ARITH_FPU_DIV_ACTIVE 0x0114 59#define SEL4BENCH_IA32_SKYLAKE_EVENT_L2_RQSTS 0xFF24 60#define SEL4BENCH_IA32_SKYLAKE_EVENT_L2_RQSTS_MISS 0x3F24 61#define SEL4BENCH_IA32_SKYLAKE_EVENT_DTLB_STORE_MISSES 0xFF49 62#define SEL4BENCH_IA32_SKYLAKE_EVENT_L1D_REPLACEMENT 0x0151 63#define SEL4BENCH_IA32_SKYLAKE_EVENT_RS_EVENTS_EMPTY_CYCLES 0x015E 64#define SEL4BENCH_IA32_SKYLAKE_EVENT_LOCK_CYCLES 0xFF63 65#define SEL4BENCH_IA32_SKYLAKE_EVENT_IDQ_MITE_UOPS 0x0479 66#define SEL4BENCH_IA32_SKYLAKE_EVENT_IDQ_DSB_UOPS 0x0879 67#define SEL4BENCH_IA32_SKYLAKE_EVENT_IDQ_MS_UOPS 0x3079 68#define SEL4BENCH_IA32_SKYLAKE_EVENT_ICACHE_IFDATA_STALL 0x0480 69#define SEL4BENCH_IA32_SKYLAKE_EVENT_ICACHE_64B_IFTAG_MISS 0x0283 70#define SEL4BENCH_IA32_SKYLAKE_EVENT_ITLB_MISSES 0xFF85 71#define SEL4BENCH_IA32_SKYLAKE_EVENT_ILD_STALL 0xFF87 72#define SEL4BENCH_IA32_SKYLAKE_EVENT_IDQ_UOPS_NOT_DELIVERED_CORE 0x019C 73#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_PORT_0 0x01A1 74#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_PORT_1 0x02A1 75#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_PORT_2 0x04A1 76#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_PORT_3 0x08A1 77#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_PORT_4 0x10A1 78#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_PORT_5 0x20A1 79#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_PORT_6 0x40A1 80#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_PORT_7 0x80A1 81#define SEL4BENCH_IA32_SKYLAKE_EVENT_RESOURCE_STALLS_ANY 0x01A2 82#define SEL4BENCH_IA32_SKYLAKE_EVENT_RESOURCE_STALLS_SB 0x08A2 83#define SEL4BENCH_IA32_SKYLAKE_EVENT_CYCLE_ACTIVITY_STALLS_TOTAL 0x040004A3 84#define SEL4BENCH_IA32_SKYLAKE_EVENT_CYCLE_ACTIVITY_STALLS_L1D_MISS 0x0C000CA3 85#define SEL4BENCH_IA32_SKYLAKE_EVENT_EXE_ACTIVITY_EXE_BOUND_0_PORTS 0x01A6 86#define SEL4BENCH_IA32_SKYLAKE_EVENT_EXE_ACTIVITY_1_PORTS_UTIL 0x02A6 87#define SEL4BENCH_IA32_SKYLAKE_EVENT_EXE_ACTIVITY_2_PORTS_UTIL 0x04A6 88#define SEL4BENCH_IA32_SKYLAKE_EVENT_EXE_ACTIVITY_3_PORTS_UTIL 0x08A6 89#define SEL4BENCH_IA32_SKYLAKE_EVENT_EXE_ACTIVITY_4_PORTS_UTIL 0x10A6 90#define SEL4BENCH_IA32_SKYLAKE_EVENT_EXE_ACTIVITY_BOUND_ON_STORES 0x40A6 91#define SEL4BENCH_IA32_SKYLAKE_EVENT_LSD_UOPS 0x01A8 92#define SEL4BENCH_IA32_SKYLAKE_EVENT_LSD_CYCLES_ACTIVE 0x010001A8 93#define SEL4BENCH_IA32_SKYLAKE_EVENT_LSD_CYCLES_4_UOPS 0x040001A8 94#define SEL4BENCH_IA32_SKYLAKE_EVENT_DSB2MITE_SWITCHES_PENALTY_CYCLES 0x02AB 95#define SEL4BENCH_IA32_SKYLAKE_EVENT_OFFCORE_REQUESTS 0xFFB0 96#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_CORE 0x02B1 97#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_CORE_CYCLES_GE_1 0x010002B1 98#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_CORE_CYCLES_GE_2 0x020002B1 99#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_EXECUTED_x87 0x10B1 100#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_OTHERS_ASSISTS_ANY 0x3FC1 101#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_RETIRED_ALL 0x01C2 102#define SEL4BENCH_IA32_SKYLAKE_EVENT_UOPS_RETIRED_RETIRE_SLOTS 0x02C2 103#define SEL4BENCH_IA32_SKYLAKE_EVENT_MACHINE_CLEARS 0xFFC3 104#define SEL4BENCH_IA32_SKYLAKE_EVENT_FP_ASSIST_ANY 0xFFCA 105#define SEL4BENCH_IA32_SKYLAKE_EVENT_HW_INTERRUPTS_RECEIVED 0x01CB 106#define SEL4BENCH_IA32_SKYLAKE_EVENT_MEM_INST_RETIRED_ALL 0xFFD0 107#define SEL4BENCH_IA32_SKYLAKE_EVENT_MEM_INST_RETIRED_ALL_LOADS 0xF1D0 108#define SEL4BENCH_IA32_SKYLAKE_EVENT_MEM_INST_RETIRED_ALL_STORES 0xF2D0 109#define SEL4BENCH_IA32_SKYLAKE_EVENT_MEM_LOAD_RETIRED_L1_HIT 0x01D1 110 111//Haswell uArch 112#define SEL4BENCH_IA32_HASWELL_EVENT_LD_BLOCKS 0xFF03 113#define SEL4BENCH_IA32_HASWELL_EVENT_MISALIGN_MEM 0xFF05 114#define SEL4BENCH_IA32_HASWELL_EVENT_DTLB_LOAD_MISSES 0xFF08 115#define SEL4BENCH_IA32_HASWELL_EVENT_INT_MISC_RECOVERY_CYCLES 0x0100030D 116#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_ISSUED_ANY 0x010E 117#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_ISSUED_FLAGS_MERGE 0x100E 118#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_ISSUED_SLOW_LEA 0x200E 119#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_ISSUED_SINGLE_MUL 0x400E 120#define SEL4BENCH_IA32_HASWELL_EVENT_L2_RQSTS 0xFF24 121#define SEL4BENCH_IA32_HASWELL_EVENT_L2_RQSTS_MISS 0x3F24 122#define SEL4BENCH_IA32_HASWELL_EVENT_DTLB_STORE_MISSES 0xFF49 123#define SEL4BENCH_IA32_HASWELL_EVENT_L1D_REPLACEMENT 0x0151 124#define SEL4BENCH_IA32_HASWELL_EVENT_MOVE_ELIMINATION_INT_NOT_ELIMINATED 0x0458 125#define SEL4BENCH_IA32_HASWELL_EVENT_MOVE_ELIMINATION_INT_ELIMINATED 0x0158 126#define SEL4BENCH_IA32_HASWELL_EVENT_CPL_CYCLES_RING0 0x015C 127#define SEL4BENCH_IA32_HASWELL_EVENT_CPL_CYCLES_RING123 0x025C 128#define SEL4BENCH_IA32_HASWELL_EVENT_RS_EVENTS_EMPTY_CYCLES 0x015E 129#define SEL4BENCH_IA32_HASWELL_EVENT_IDQ_EMPTY 0x0279 130#define SEL4BENCH_IA32_HASWELL_EVENT_IDQ_MITE_UOPS 0x0479 131#define SEL4BENCH_IA32_HASWELL_EVENT_IDQ_DSB_UOPS 0x0879 132#define SEL4BENCH_IA32_HASWELL_EVENT_IDQ_MS_UOPS 0x3079 133#define SEL4BENCH_IA32_HASWELL_EVENT_ICACHE_MISSES 0x0280 134#define SEL4BENCH_IA32_HASWELL_EVENT_ITLB_MISSES 0xFF85 135#define SEL4BENCH_IA32_HASWELL_EVENT_ILD_STALL_LCP 0x0187 136#define SEL4BENCH_IA32_HASWELL_EVENT_ILD_STALL_IQ_FULL 0x0487 137#define SEL4BENCH_IA32_HASWELL_EVENT_IDQ_UOPS_NOT_DELIVERED_CORE 0x019C 138#define SEL4BENCH_IA32_HASWELL_EVENT_IDQ_UOPS_NOT_DELIVERED_CORE_CYCLES_GE_1 0x0100019C 139#define SEL4BENCH_IA32_HASWELL_EVENT_IDQ_UOPS_NOT_DELIVERED_CORE_CYCLES_GE_2 0x0200019C 140#define SEL4BENCH_IA32_HASWELL_EVENT_IDQ_UOPS_NOT_DELIVERED_CORE_CYCLES_GE_3 0x0300019C 141#define SEL4BENCH_IA32_HASWELL_EVENT_IDQ_UOPS_NOT_DELIVERED_CORE_CYCLES_GE_4 0x0400019C 142#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_PORT_0 0x01A1 143#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_PORT_1 0x02A1 144#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_PORT_2 0x04A1 145#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_PORT_3 0x08A1 146#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_PORT_4 0x10A1 147#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_PORT_5 0x20A1 148#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_PORT_6 0x40A1 149#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_PORT_7 0x80A1 150#define SEL4BENCH_IA32_HASWELL_EVENT_RESOURCE_STALLS_ANY 0x01A2 151#define SEL4BENCH_IA32_HASWELL_EVENT_RESOURCE_STALLS_RS 0x04A2 152#define SEL4BENCH_IA32_HASWELL_EVENT_RESOURCE_STALLS_SB 0x08A2 153#define SEL4BENCH_IA32_HASWELL_EVENT_RESOURCE_STALLS_ROB 0x10A2 154#define SEL4BENCH_IA32_HASWELL_EVENT_LSD_UOPS 0x01A8 155#define SEL4BENCH_IA32_HASWELL_EVENT_CYCLE_ACTIVITY_CYCLES_LDM_PENDING 0x020002A3 156#define SEL4BENCH_IA32_HASWELL_EVENT_CYCLE_ACTIVITY_CYCLES_NO_EXECUTE 0x040004A3 157#define SEL4BENCH_IA32_HASWELL_EVENT_CYCLE_ACTIVITY_STALLS_LDM_PENDING 0x060005A3 158#define SEL4BENCH_IA32_HASWELL_EVENT_CYCLE_ACTIVITY_STALLS_L1D_PENDING 0x0C000CA3 // PMC2 only 159#define SEL4BENCH_IA32_HASWELL_EVENT_OFFCORE_REQUESTS 0xFFB0 160#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_CORE 0x02B1 161#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_CORE_CYCLES_GE_1 0x010002B1 162#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_CORE_CYCLES_GE_2 0x020002B1 163#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_CORE_CYCLES_GE_3 0x030002B1 164#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_EXECUTED_CORE_CYCLES_GE_4 0x040002B1 165#define SEL4BENCH_IA32_HASWELL_EVENT_OTHER_ASSISTS 0xFFC1 166#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_RETIRED_ALL 0x01C2 167#define SEL4BENCH_IA32_HASWELL_EVENT_UOPS_RETIRED_RETIRE_SLOTS 0x02C2 168#define SEL4BENCH_IA32_HASWELL_EVENT_MACHINE_CLEARS 0xFFC3 169#define SEL4BENCH_IA32_HASWELL_EVENT_FP_ASSIST_ANY 0xFFCA 170#define SEL4BENCH_IA32_HASWELL_EVENT_ROB_MISC_EVENTS_LBR_INSERTS 0x20CC 171#define SEL4BENCH_IA32_HASWELL_EVENT_MEM_UOPS_RETIRED_ALL 0xFFD0 172#define SEL4BENCH_IA32_HASWELL_EVENT_MEM_UOPS_RETIRED_ALL_LOADS 0xF1D0 173#define SEL4BENCH_IA32_HASWELL_EVENT_MEM_UOPS_RETIRED_ALL_STORES 0xF2D0 174#define SEL4BENCH_IA32_HASWELL_EVENT_MEM_LOAD_UOPS_RETIRED_L1_HIT 0x01D1 175 176#define SEL4BENCH_IA32_HASWELL_EVENT_TX_MEM_ABORT_CONFLICT 0x0154 177#define SEL4BENCH_IA32_HASWELL_EVENT_TX_MEM_ABORT_CAPACITY_WRITE 0x0154 178/* Counts the number of times a class of instructions that may cause a 179 transactional abort was executed. Since this is the count of execution, 180 it may not always cause a transactional abort. */ 181#define SEL4BENCH_IA32_HASWELL_EVENT_TX_EXEC_MISC1 0x015D 182/* Counts the number of times a class of instructions (e.g. vzeroupper) that 183 may cause a transactional abort was executed inside a transactional region */ 184#define SEL4BENCH_IA32_HASWELL_EVENT_TX_EXEC_MISC2 0x025D 185#define SEL4BENCH_IA32_HASWELL_EVENT_TX_EXEC_NEST_EXCEEDED 0x045D 186#define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_START 0x01C9 187#define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_COMMIT 0x02C9 188#define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED 0x04C9 189#define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_MEM_EVENT 0x08C9 190#define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_RARE 0x10C9 191#define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_HLE 0x20C9 192#define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_MEM_TYPE 0x40C9 193#define SEL4BENCH_IA32_HASWELL_EVENT_RTM_RETIRED_ABORTED_OTHER 0x80C9 194 195//Sandy Bridge uArch 196#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_LD_BLOCKS 0xFF03 197#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_MISALIGN_MEM 0xFF05 198#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_LD_BLOCKS_PARTIAL 0xFF07 199#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_DTLB_LOAD_MISSES 0xFF08 200#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_INT_MISC_RECOVERY_CYCLES 0x0100030D 201#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_ISSUED_ANY 0x010E 202#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_FP_COMP_OPS_EXE 0xFF10 203#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_SIMP_FP_256 0xFF11 204#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_ARITH_FPU_DIV_ACTIVE 0x0114 205#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_L2_RQSTS 0xFF24 206#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_L1_L1D_WB_RQSTS_ALL 0xFF28 207#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_DTLB_STORE_MISSES 0xFF49 208#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_L1D_REPLACEMENT 0x0151 209#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RESOURCE_STALLS2_ALL_FL_EMPTY 0x0C5B 210#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RESOURCE_STALLS2_ALL_PRF_CONTROL 0x0F5B 211#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RESOURCE_STALLS2_BOB_FULL 0x405B 212#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_CPL_CYCLES_RING0 0x015C 213#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_CPL_CYCLES_RING123 0x025C 214#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RS_EVENTS_EMPTY_CYCLES 0x015E 215#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_LOCK_CYCLES 0xFF63 216#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_IDQ_EMPTY 0x0279 217#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_IDQ_MITE_UOPS 0x0479 218#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_IDQ_DSB_UOPS 0x0879 219#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_IDQ_MS_UOPS 0x3079 220#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_ICACHE_MISSES 0x0280 221#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_ITLB_MISSES 0xFF85 222#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_ILD_STALL 0xFF87 223#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_IDQ_UOPS_NOT_DELIVERED_CORE 0x019C 224#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_DISPATCHED_PORT_0 0x01A1 225#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_DISPATCHED_PORT_1 0x02A1 226#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_DISPATCHED_PORT_2 0x0CA1 227#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_DISPATCHED_PORT_3 0x30A1 228#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_DISPATCHED_PORT_4 0x40A1 229#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_DISPATCHED_PORT_5 0x80A1 230#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RESOURCE_STALLS_ANY 0x01A2 231#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RESOURCE_STALLS_LB 0x02A2 232#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RESOURCE_STALLS_RS 0x04A2 233#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RESOURCE_STALLS_SB 0x08A2 234#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RESOURCE_STALLS_ROB 0x10A2 235#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_RESOURCE_STALLS_FCSW 0x20A2 236#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_OFFCORE_REQUESTS 0xFFB0 237#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_DISPATCHED_THREAD 0x01B1 238#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_DISPATCHED_CORE 0x02B1 239#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_AGU_BYPASS_CANCEL_COUNT 0x01B6 240#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_TLB_FLUSH 0xFFBD 241#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_L1D_BLOCKS_BANK_CONFLICT_CYCLES 0x05BF 242#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_RETIRED_ALL 0x01C2 243#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_UOPS_RETIRED_RETIRE_SLOTS 0x02C2 244#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_MACHINE_CLEARS 0xFFC3 245#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_FP_ASSIST_ANY 0xFFCA 246#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_ROB_MISC_EVENTS_LBR_INSERTS 0x20CC 247#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_MEM_UOPS_RETIRED_ALL 0xFFD0 248#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_MEM_UOPS_RETIRED_ALL_LOADS 0xF1D0 249#define SEL4BENCH_IA32_SANDYBRIDGE_EVENT_MEM_UOPS_RETIRED_ALL_STORES 0xF2D0 250 251//Westmere uArch 252#define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_DMISS_READ 0x0208 253#define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_DHIT_READ 0x1008 254#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_READ_HIT 0x0124 255#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_READ_MISS 0x0224 256#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_WRITE_HIT 0x0424 257#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_WRITE_MISS 0x0824 258#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_IFETCH_HIT 0x1024 259#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_IFETCH_MISS 0x2024 260#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_PFETCH_HIT 0x4024 261#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_PFETCH_MISS 0x8024 262#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_ACCESS 0x0026 //modifiers: MESI (demand), MESI << 4 (prefetch) 263#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_WRITE 0x0027 //modifiers: MESI ( RFO), MESI << 4 ( lock) 264#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3_MISS 0x012E 265#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3_ACCESS 0x022E 266#define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_DMISS 0x0249 267#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L1D_LINES_IN 0x0151 //must use counter 0 or 1 268#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L1I_HIT 0x0180 269#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L1I_MISS 0x0280 270#define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_IHIT_LARGEPAGE 0x0182 271#define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_IMISS 0x0285 272#define SEL4BENCH_IA32_WESTMERE_EVENT_EXECUTE_BRANCH 0x7F88 273#define SEL4BENCH_IA32_WESTMERE_EVENT_BRANCH_MISPREDICT 0x7F89 274#define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_IFLUSH 0x01AE 275#define SEL4BENCH_IA32_WESTMERE_EVENT_RETIRE_INSTRUCTION 0x00C0 276#define SEL4BENCH_IA32_WESTMERE_EVENT_SELF_MODIFYING_CODE 0x04C3 277#define SEL4BENCH_IA32_WESTMERE_EVENT_RETIRE_BRANCH 0x00C4 278#define SEL4BENCH_IA32_WESTMERE_EVENT_BRANCH_MISPREDICT_R 0x00C5 279#define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_IMISS_R 0x20C8 280#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L1D_HIT_R 0x01CB 281#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L2_HIT_R 0x02CB 282#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3P_HIT_R 0x04CB 283#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3_HIT_R 0x08CB 284#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_L3_MISS_R 0x10CB 285#define SEL4BENCH_IA32_WESTMERE_EVENT_CACHE_LFB_HIT_R 0x40CB 286#define SEL4BENCH_IA32_WESTMERE_EVENT_TLB_DMISS_R 0x80CB 287 288//Nehalem uArch 289#define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_DMISS_READ 0x0208 290#define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_DHIT_READ 0x1008 291#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_READ_HIT 0x0124 292#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_READ_MISS 0x0224 293#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_WRITE_HIT 0x0424 294#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_WRITE_MISS 0x0824 295#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_IFETCH_HIT 0x1024 296#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_IFETCH_MISS 0x2024 297#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_PFETCH_HIT 0x4024 298#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_PFETCH_MISS 0x8024 299#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_ACCESS 0x0026 //modifiers: MESI (demand), MESI << 4 (prefetch) 300#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_WRITE 0x0027 //modifiers: MESI ( RFO), MESI << 4 ( lock) 301#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3_MISS 0x412E 302#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3_ACCESS 0x4F2E 303#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_READ 0x0040 //modifiers: MESI; must use counter 0 or 1 304#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_WRITE 0x0041 //modifiers: MESI; must use counter 0 or 1 305#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_READ_LOCK 0x0042 //modifiers: MESI; must use counter 0 or 1 306#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_ACCESS 0x0143 //must use counter 0 or 1 307#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_ACCESS_C 0x0243 //must use counter 0 or 1 308#define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_DMISS 0x0249 309#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_LINES_IN 0x0151 //must use counter 0 or 1 310#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1I_HIT 0x0180 311#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1I_MISS 0x0280 312#define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_IHIT_LARGEPAGE 0x0182 313#define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_IMISS 0x0285 314#define SEL4BENCH_IA32_NEHALEM_EVENT_EXECUTE_BRANCH 0x7F88 315#define SEL4BENCH_IA32_NEHALEM_EVENT_BRANCH_MISPREDICT 0x7F89 316#define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_IFLUSH 0x01AE 317#define SEL4BENCH_IA32_NEHALEM_EVENT_RETIRE_INSTRUCTION 0x00C0 318#define SEL4BENCH_IA32_NEHALEM_EVENT_SELF_MODIFYING_CODE 0x04C3 319#define SEL4BENCH_IA32_NEHALEM_EVENT_RETIRE_BRANCH 0x00C4 320#define SEL4BENCH_IA32_NEHALEM_EVENT_BRANCH_MISPREDICT_R 0x00C5 321#define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_IMISS_R 0x20C8 322#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L1D_HIT_R 0x01CB 323#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L2_HIT_R 0x02CB 324#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3P_HIT_R 0x04CB 325#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3_HIT_R 0x08CB 326#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_L3_MISS_R 0x10CB 327#define SEL4BENCH_IA32_NEHALEM_EVENT_CACHE_LFB_HIT_R 0x40CB 328#define SEL4BENCH_IA32_NEHALEM_EVENT_TLB_DMISS_R 0x80CB 329 330//Core2 series (aka Core uArch) 331//events are subject to modifiers above, as commented 332#define SEL4BENCH_IA32_CORE2_EVENT_SEGMENT_LOAD 0x0006 333#define SEL4BENCH_IA32_CORE2_EVENT_TLB_DMISS 0x0108 334#define SEL4BENCH_IA32_CORE2_EVENT_TLB_DMISS_READ 0x0208 335#define SEL4BENCH_IA32_CORE2_EVENT_TLB_L0D_MISS_READ 0x0408 336#define SEL4BENCH_IA32_CORE2_EVENT_TLB_DMISS_WRITE 0x0808 337#define SEL4BENCH_IA32_CORE2_EVENT_PAGETABLE_WALK 0x010C 338#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_MISS 0x0024 //modifiers: CORE, PREFETCH 339#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_EVICT 0x0026 //modifiers: CORE, PREFETCH 340#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_IFETCH 0x0028 //modifiers: CORE, MESI 341#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_READ 0x0029 //modifiers: CORE, PREFETCH, MESI 342#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_WRITE 0x002A //modifiers: CORE, MESI 343#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_LOCK 0x002B //modifiers: CORE, MESI 344#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_ACCESS 0x002E //modifiers: CORE, PREFETCH, MESI 345#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_READ 0x0040 //modifiers: MESI 346#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_WRITE 0x0041 //modifiers: MESI 347#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_READ_LOCK 0x0042 //modifiers: MESI 348#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_ACCESS 0x0143 349#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_ACCESS_C 0x0243 350#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_READ_SPLIT 0x0149 351#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_WRITE_SPLIT 0x0249 352#define SEL4BENCH_IA32_CORE2_EVENT_INSTRUCTION_FETCH 0x0080 353#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1I_MISS 0x0081 354#define SEL4BENCH_IA32_CORE2_EVENT_TLB_IMISS_SMALLPAGE 0x0282 355#define SEL4BENCH_IA32_CORE2_EVENT_TLB_IMISS_LARGEPAGE 0x1082 356#define SEL4BENCH_IA32_CORE2_EVENT_TLB_IFLUSH 0x4082 357#define SEL4BENCH_IA32_CORE2_EVENT_TLB_IMISS 0x1282 358#define SEL4BENCH_IA32_CORE2_EVENT_EXECUTE_BRANCH 0x0088 359#define SEL4BENCH_IA32_CORE2_EVENT_BRANCH_MISPREDICT 0x0089 360#define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_INSTRUCTION 0x00C0 361#define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_MEMORY_READ 0x01C0 362#define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_MEMORY_WRITE 0x02C0 363#define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_NONMEMORY 0x04C0 364#define SEL4BENCH_IA32_CORE2_EVENT_SELF_MODIFYING_CODE 0x01C3 365#define SEL4BENCH_IA32_CORE2_EVENT_RETIRE_BRANCH 0x00C4 366#define SEL4BENCH_IA32_CORE2_EVENT_BRANCH_MISPREDICT_R 0x00C5 367#define SEL4BENCH_IA32_CORE2_EVENT_HARDWARE_INTERRUPT 0x00C8 368#define SEL4BENCH_IA32_CORE2_EVENT_TLB_IMISS_R 0x00C9 369#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_MISS_R 0x01CB //must use counter 0 370#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L1D_MISS_LINE_R 0x02CB //must use counter 0 371#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_MISS_R 0x04CB //must use counter 0 372#define SEL4BENCH_IA32_CORE2_EVENT_CACHE_L2_MISS_LINE_R 0x08CB //must use counter 0 373#define SEL4BENCH_IA32_CORE2_EVENT_TLB_DMISS_R 0x10CB //must use counter 0 374 375//Core Solo / Core Duo processors 376//events are subject to modifiers above, as commented 377#define SEL4BENCH_IA32_CORE_EVENT_SEGMENT_LOAD 0x0006 378#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_ALLOC 0x0024 379#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_ALLOC_DIRTY 0x0025 380#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_EVICT 0x0026 381#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_EVICT_DIRTY 0x0027 382#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_IFETCH 0x0028 //modifiers: MESI 383#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_READ 0x0029 //modifiers: MESI 384#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_WRITE 0x002A //modifiers: MESI 385#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L2_ACCESS 0x002E //modifiers: MESI 386#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_READ 0x0040 //modifiers: MESI 387#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_WRITE 0x0041 //modifiers: MESI 388#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_READ_LOCK 0x0042 //modifiers: MESI 389#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_ACCESS 0x0143 390#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_ACCESS_C 0x0243 391#define SEL4BENCH_IA32_CORE_EVENT_CACHED_MEMORY_ACCESS 0x0244 392#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_EVICT 0x0F45 393#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_ALLOC_DIRTY 0x0046 394#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1D_EVICT_DIRTY 0x0047 395#define SEL4BENCH_IA32_CORE_EVENT_TLB_DMISS 0x0049 396#define SEL4BENCH_IA32_CORE_EVENT_INSTRUCTION_FETCH 0x0080 397#define SEL4BENCH_IA32_CORE_EVENT_CACHE_L1I_MISS 0x0081 398#define SEL4BENCH_IA32_CORE_EVENT_TLB_IMISS 0x0085 399#define SEL4BENCH_IA32_CORE_EVENT_EXECUTE_BRANCH 0x0088 400#define SEL4BENCH_IA32_CORE_EVENT_BRANCH_MISPREDICT 0x0089 401#define SEL4BENCH_IA32_CORE_EVENT_RETIRE_INSTRUCTION 0x00C0 402#define SEL4BENCH_IA32_CORE_EVENT_SELF_MODIFYING_CODE 0x00C3 403#define SEL4BENCH_IA32_CORE_EVENT_RETIRE_BRANCH 0x00C4 404#define SEL4BENCH_IA32_CORE_EVENT_BRANCH_MISPREDICT_R 0x00C5 405#define SEL4BENCH_IA32_CORE_EVENT_HARDWARE_INTERRUPT 0x00C8 406#define SEL4BENCH_IA32_CORE_EVENT_RETIRE_BRANCH_TRUE 0x00C9 407#define SEL4BENCH_IA32_CORE_EVENT_BRANCH_MISPREDICT_TRUE_R 0x00C5 408#define SEL4BENCH_IA32_CORE_EVENT_BTB_MISS 0x00E2 409 410//P6 family (PM, P3) 411//new (or modified) in PM -- note, branch prediction events include speculative execution 412#define SEL4BENCH_IA32_P6_EVENT_EXECUTE_BRANCH 0x0088 413#define SEL4BENCH_IA32_P6_EVENT_BRANCH_MISPREDICT 0x0089 414//all P6 processors 415#define SEL4BENCH_IA32_P6_EVENT_CACHE_L2_LINES_IN 0x0024 //modifiers: PREFETCH, MESI 416#define SEL4BENCH_IA32_P6_EVENT_CACHE_L2_IFETCH 0x0028 //modifiers: MESI 417#define SEL4BENCH_IA32_P6_EVENT_CACHE_L2_READ 0x0029 //modifiers: PREFETCH, MESI 418#define SEL4BENCH_IA32_P6_EVENT_CACHE_L2_WRITE 0x002A //modifiers: MESI 419#define SEL4BENCH_IA32_P6_EVENT_MAIN_MEMORY_ACCESS 0x0043 420#define SEL4BENCH_IA32_P6_EVENT_CACHE_L1D_LINES_IN 0x0045 421#define SEL4BENCH_IA32_P6_EVENT_INSTRUCTION_FETCH 0x0080 422#define SEL4BENCH_IA32_P6_EVENT_CACHE_L1I_MISS 0x0081 423#define SEL4BENCH_IA32_P6_EVENT_TLB_IMISS 0x0085 424#define SEL4BENCH_IA32_P6_EVENT_RETIRE_INSTRUCTION 0x00C0 425#define SEL4BENCH_IA32_P6_EVENT_RETIRE_BRANCH 0x00C4 426#define SEL4BENCH_IA32_P6_EVENT_BRANCH_MISPREDICT_R 0x00C5 427#define SEL4BENCH_IA32_P6_EVENT_HARDWARE_INTERRUPT 0x00C8 428#define SEL4BENCH_IA32_P6_EVENT_BTB_MISS 0x00E2 429 430//generification layer 431#define SEL4BENCH_EVENT_GENERIC_MASK 0xFFFF0000 432#define SEL4BENCH_EVENT_CACHE_L1I_MISS (0 | SEL4BENCH_EVENT_GENERIC_MASK) 433#define SEL4BENCH_EVENT_CACHE_L1D_MISS (1u | SEL4BENCH_EVENT_GENERIC_MASK) 434#define SEL4BENCH_EVENT_TLB_L1I_MISS (2u | SEL4BENCH_EVENT_GENERIC_MASK) 435#define SEL4BENCH_EVENT_TLB_L1D_MISS (3u | SEL4BENCH_EVENT_GENERIC_MASK) 436#define SEL4BENCH_EVENT_MEMORY_ACCESS (4u | SEL4BENCH_EVENT_GENERIC_MASK) 437#define SEL4BENCH_EVENT_BRANCH_MISPREDICT 0x00C5 438#define SEL4BENCH_EVENT_EXECUTE_INSTRUCTION 0x00C0 439