1/*
2 * Copyright Linux Kernel Team
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * This file is derived from an intermediate build stage of the
7 * Linux kernel. The licenses of all input files to this process
8 * are compatible with GPL-2.0-only.
9 */
10
11/dts-v1/;
12
13/ {
14	#address-cells = < 0x01 >;
15	#size-cells = < 0x01 >;
16	model = "Wandboard i.MX6 Quad Board revD1";
17	compatible = "wand,imx6q-wandboard\0fsl,imx6q";
18
19	chosen {
20		stdout-path = "/soc/aips-bus@2000000/spba-bus@2000000/serial@2020000";
21	};
22
23	memory {
24		device_type = "memory";
25	};
26
27	aliases {
28		ethernet0 = "/soc/aips-bus@2100000/ethernet@2188000";
29		can0 = "/soc/aips-bus@2000000/flexcan@2090000";
30		can1 = "/soc/aips-bus@2000000/flexcan@2094000";
31		gpio0 = "/soc/aips-bus@2000000/gpio@209c000";
32		gpio1 = "/soc/aips-bus@2000000/gpio@20a0000";
33		gpio2 = "/soc/aips-bus@2000000/gpio@20a4000";
34		gpio3 = "/soc/aips-bus@2000000/gpio@20a8000";
35		gpio4 = "/soc/aips-bus@2000000/gpio@20ac000";
36		gpio5 = "/soc/aips-bus@2000000/gpio@20b0000";
37		gpio6 = "/soc/aips-bus@2000000/gpio@20b4000";
38		i2c0 = "/soc/aips-bus@2100000/i2c@21a0000";
39		i2c1 = "/soc/aips-bus@2100000/i2c@21a4000";
40		i2c2 = "/soc/aips-bus@2100000/i2c@21a8000";
41		ipu0 = "/soc/ipu@2400000";
42		mmc0 = "/soc/aips-bus@2100000/usdhc@2190000";
43		mmc1 = "/soc/aips-bus@2100000/usdhc@2194000";
44		mmc2 = "/soc/aips-bus@2100000/usdhc@2198000";
45		mmc3 = "/soc/aips-bus@2100000/usdhc@219c000";
46		serial0 = "/soc/aips-bus@2000000/spba-bus@2000000/serial@2020000";
47		serial1 = "/soc/aips-bus@2100000/serial@21e8000";
48		serial2 = "/soc/aips-bus@2100000/serial@21ec000";
49		serial3 = "/soc/aips-bus@2100000/serial@21f0000";
50		serial4 = "/soc/aips-bus@2100000/serial@21f4000";
51		spi0 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@2008000";
52		spi1 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@200c000";
53		spi2 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@2010000";
54		spi3 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@2014000";
55		usbphy0 = "/soc/aips-bus@2000000/usbphy@20c9000";
56		usbphy1 = "/soc/aips-bus@2000000/usbphy@20ca000";
57		ipu1 = "/soc/ipu@2800000";
58		spi4 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@2018000";
59	};
60
61	clocks {
62
63		ckil {
64			compatible = "fsl,imx-ckil\0fixed-clock";
65			#clock-cells = < 0x00 >;
66			clock-frequency = < 0x8000 >;
67		};
68
69		ckih1 {
70			compatible = "fsl,imx-ckih1\0fixed-clock";
71			#clock-cells = < 0x00 >;
72			clock-frequency = < 0x00 >;
73		};
74
75		osc {
76			compatible = "fsl,imx-osc\0fixed-clock";
77			#clock-cells = < 0x00 >;
78			clock-frequency = < 0x16e3600 >;
79		};
80	};
81
82	tempmon {
83		compatible = "fsl,imx6q-tempmon";
84		interrupt-parent = < 0x01 >;
85		interrupts = < 0x00 0x31 0x04 >;
86		fsl,tempmon = < 0x02 >;
87		fsl,tempmon-data = < 0x03 >;
88		clocks = < 0x04 0xac >;
89	};
90
91	ldb {
92		#address-cells = < 0x01 >;
93		#size-cells = < 0x00 >;
94		compatible = "fsl,imx6q-ldb\0fsl,imx53-ldb";
95		gpr = < 0x05 >;
96		status = "disabled";
97		clocks = < 0x04 0x21 0x04 0x22 0x04 0x27 0x04 0x28 0x04 0x29 0x04 0x2a 0x04 0x87 0x04 0x88 >;
98		clock-names = "di0_pll\0di1_pll\0di0_sel\0di1_sel\0di2_sel\0di3_sel\0di0\0di1";
99
100		lvds-channel@0 {
101			#address-cells = < 0x01 >;
102			#size-cells = < 0x00 >;
103			reg = < 0x00 >;
104			status = "disabled";
105
106			port@0 {
107				reg = < 0x00 >;
108
109				endpoint {
110					remote-endpoint = < 0x06 >;
111					phandle = < 0x44 >;
112				};
113			};
114
115			port@1 {
116				reg = < 0x01 >;
117
118				endpoint {
119					remote-endpoint = < 0x07 >;
120					phandle = < 0x48 >;
121				};
122			};
123
124			port@2 {
125				reg = < 0x02 >;
126
127				endpoint {
128					remote-endpoint = < 0x08 >;
129					phandle = < 0x4e >;
130				};
131			};
132
133			port@3 {
134				reg = < 0x03 >;
135
136				endpoint {
137					remote-endpoint = < 0x09 >;
138					phandle = < 0x52 >;
139				};
140			};
141		};
142
143		lvds-channel@1 {
144			#address-cells = < 0x01 >;
145			#size-cells = < 0x00 >;
146			reg = < 0x01 >;
147			status = "disabled";
148
149			port@0 {
150				reg = < 0x00 >;
151
152				endpoint {
153					remote-endpoint = < 0x0a >;
154					phandle = < 0x45 >;
155				};
156			};
157
158			port@1 {
159				reg = < 0x01 >;
160
161				endpoint {
162					remote-endpoint = < 0x0b >;
163					phandle = < 0x49 >;
164				};
165			};
166
167			port@2 {
168				reg = < 0x02 >;
169
170				endpoint {
171					remote-endpoint = < 0x0c >;
172					phandle = < 0x4f >;
173				};
174			};
175
176			port@3 {
177				reg = < 0x03 >;
178
179				endpoint {
180					remote-endpoint = < 0x0d >;
181					phandle = < 0x53 >;
182				};
183			};
184		};
185	};
186
187	pmu {
188		compatible = "arm,cortex-a9-pmu";
189		interrupt-parent = < 0x01 >;
190		interrupts = < 0x00 0x5e 0x04 >;
191	};
192
193	soc {
194		#address-cells = < 0x01 >;
195		#size-cells = < 0x01 >;
196		compatible = "simple-bus";
197		interrupt-parent = < 0x01 >;
198		ranges;
199
200		dma-apbh@110000 {
201			compatible = "fsl,imx6q-dma-apbh\0fsl,imx28-dma-apbh";
202			reg = < 0x110000 0x2000 >;
203			interrupts = < 0x00 0x0d 0x04 0x00 0x0d 0x04 0x00 0x0d 0x04 0x00 0x0d 0x04 >;
204			interrupt-names = "gpmi0\0gpmi1\0gpmi2\0gpmi3";
205			#dma-cells = < 0x01 >;
206			dma-channels = < 0x04 >;
207			clocks = < 0x04 0x6a >;
208			phandle = < 0x0e >;
209		};
210
211		gpmi-nand@112000 {
212			compatible = "fsl,imx6q-gpmi-nand";
213			#address-cells = < 0x01 >;
214			#size-cells = < 0x01 >;
215			reg = < 0x112000 0x2000 0x114000 0x2000 >;
216			reg-names = "gpmi-nand\0bch";
217			interrupts = < 0x00 0x0f 0x04 >;
218			interrupt-names = "bch";
219			clocks = < 0x04 0x98 0x04 0x99 0x04 0x97 0x04 0x96 0x04 0x95 >;
220			clock-names = "gpmi_io\0gpmi_apb\0gpmi_bch\0gpmi_bch_apb\0per1_bch";
221			dmas = < 0x0e 0x00 >;
222			dma-names = "rx-tx";
223			status = "disabled";
224		};
225
226		hdmi@120000 {
227			#address-cells = < 0x01 >;
228			#size-cells = < 0x00 >;
229			reg = < 0x120000 0x9000 >;
230			interrupts = < 0x00 0x73 0x04 >;
231			gpr = < 0x05 >;
232			clocks = < 0x04 0x7b 0x04 0x7c >;
233			clock-names = "iahb\0isfr";
234			status = "okay";
235			compatible = "fsl,imx6q-hdmi";
236			ddc-i2c-bus = < 0x0f >;
237
238			port@0 {
239				reg = < 0x00 >;
240
241				endpoint {
242					remote-endpoint = < 0x10 >;
243					phandle = < 0x42 >;
244				};
245			};
246
247			port@1 {
248				reg = < 0x01 >;
249
250				endpoint {
251					remote-endpoint = < 0x11 >;
252					phandle = < 0x46 >;
253				};
254			};
255
256			port@2 {
257				reg = < 0x02 >;
258
259				endpoint {
260					remote-endpoint = < 0x12 >;
261					phandle = < 0x4c >;
262				};
263			};
264
265			port@3 {
266				reg = < 0x03 >;
267
268				endpoint {
269					remote-endpoint = < 0x13 >;
270					phandle = < 0x50 >;
271				};
272			};
273		};
274
275		gpu@130000 {
276			compatible = "vivante,gc";
277			reg = < 0x130000 0x4000 >;
278			interrupts = < 0x00 0x09 0x04 >;
279			clocks = < 0x04 0x1b 0x04 0x7a 0x04 0x4a >;
280			clock-names = "bus\0core\0shader";
281			power-domains = < 0x14 >;
282		};
283
284		gpu@134000 {
285			compatible = "vivante,gc";
286			reg = < 0x134000 0x4000 >;
287			interrupts = < 0x00 0x0a 0x04 >;
288			clocks = < 0x04 0x1a 0x04 0x79 >;
289			clock-names = "bus\0core";
290			power-domains = < 0x14 >;
291		};
292
293		timer@a00600 {
294			compatible = "arm,cortex-a9-twd-timer";
295			reg = < 0xa00600 0x20 >;
296			interrupts = < 0x01 0x0d 0xf01 >;
297			interrupt-parent = < 0x15 >;
298			clocks = < 0x04 0x0f >;
299		};
300
301		interrupt-controller@a01000 {
302			compatible = "arm,cortex-a9-gic";
303			#interrupt-cells = < 0x03 >;
304			interrupt-controller;
305			reg = < 0xa01000 0x1000 0xa00100 0x100 >;
306			interrupt-parent = < 0x15 >;
307			phandle = < 0x15 >;
308		};
309
310		l2-cache@a02000 {
311			compatible = "arm,pl310-cache";
312			reg = < 0xa02000 0x1000 >;
313			interrupts = < 0x00 0x5c 0x04 >;
314			cache-unified;
315			cache-level = < 0x02 >;
316			arm,tag-latency = < 0x04 0x02 0x03 >;
317			arm,data-latency = < 0x04 0x02 0x03 >;
318			arm,shared-override;
319			phandle = < 0x54 >;
320		};
321
322		pcie@1ffc000 {
323			compatible = "fsl,imx6q-pcie\0snps,dw-pcie";
324			reg = < 0x1ffc000 0x4000 0x1f00000 0x80000 >;
325			reg-names = "dbi\0config";
326			#address-cells = < 0x03 >;
327			#size-cells = < 0x02 >;
328			device_type = "pci";
329			bus-range = < 0x00 0xff >;
330			ranges = < 0x81000000 0x00 0x00 0x1f80000 0x00 0x10000 0x82000000 0x00 0x1000000 0x1000000 0x00 0xf00000 >;
331			num-lanes = < 0x01 >;
332			interrupts = < 0x00 0x78 0x04 >;
333			interrupt-names = "msi";
334			#interrupt-cells = < 0x01 >;
335			interrupt-map-mask = < 0x00 0x00 0x00 0x07 >;
336			interrupt-map = < 0x00 0x00 0x00 0x01 0x01 0x00 0x7b 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x7a 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x79 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x78 0x04 >;
337			clocks = < 0x04 0x90 0x04 0xce 0x04 0xbd >;
338			clock-names = "pcie\0pcie_bus\0pcie_phy";
339			status = "disabled";
340		};
341
342		aips-bus@2000000 {
343			compatible = "fsl,aips-bus\0simple-bus";
344			#address-cells = < 0x01 >;
345			#size-cells = < 0x01 >;
346			reg = < 0x2000000 0x100000 >;
347			ranges;
348
349			spba-bus@2000000 {
350				compatible = "fsl,spba-bus\0simple-bus";
351				#address-cells = < 0x01 >;
352				#size-cells = < 0x01 >;
353				reg = < 0x2000000 0x40000 >;
354				ranges;
355
356				spdif@2004000 {
357					compatible = "fsl,imx35-spdif";
358					reg = < 0x2004000 0x4000 >;
359					interrupts = < 0x00 0x34 0x04 >;
360					dmas = < 0x16 0x0e 0x12 0x00 0x16 0x0f 0x12 0x00 >;
361					dma-names = "rx\0tx";
362					clocks = < 0x04 0xf4 0x04 0x03 0x04 0xc5 0x04 0x6b 0x04 0x00 0x04 0x76 0x04 0x3e 0x04 0x00 0x04 0x00 0x04 0x9c >;
363					clock-names = "core\0rxtx0\0rxtx1\0rxtx2\0rxtx3\0rxtx4\0rxtx5\0rxtx6\0rxtx7\0spba";
364					status = "okay";
365					pinctrl-names = "default";
366					pinctrl-0 = < 0x17 >;
367					phandle = < 0x61 >;
368				};
369
370				spi@2008000 {
371					#address-cells = < 0x01 >;
372					#size-cells = < 0x00 >;
373					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
374					reg = < 0x2008000 0x4000 >;
375					interrupts = < 0x00 0x1f 0x04 >;
376					clocks = < 0x04 0x70 0x04 0x70 >;
377					clock-names = "ipg\0per";
378					dmas = < 0x16 0x03 0x08 0x01 0x16 0x04 0x08 0x02 >;
379					dma-names = "rx\0tx";
380					status = "disabled";
381				};
382
383				spi@200c000 {
384					#address-cells = < 0x01 >;
385					#size-cells = < 0x00 >;
386					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
387					reg = < 0x200c000 0x4000 >;
388					interrupts = < 0x00 0x20 0x04 >;
389					clocks = < 0x04 0x71 0x04 0x71 >;
390					clock-names = "ipg\0per";
391					dmas = < 0x16 0x05 0x08 0x01 0x16 0x06 0x08 0x02 >;
392					dma-names = "rx\0tx";
393					status = "disabled";
394				};
395
396				spi@2010000 {
397					#address-cells = < 0x01 >;
398					#size-cells = < 0x00 >;
399					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
400					reg = < 0x2010000 0x4000 >;
401					interrupts = < 0x00 0x21 0x04 >;
402					clocks = < 0x04 0x72 0x04 0x72 >;
403					clock-names = "ipg\0per";
404					dmas = < 0x16 0x07 0x08 0x01 0x16 0x08 0x08 0x02 >;
405					dma-names = "rx\0tx";
406					status = "disabled";
407				};
408
409				spi@2014000 {
410					#address-cells = < 0x01 >;
411					#size-cells = < 0x00 >;
412					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
413					reg = < 0x2014000 0x4000 >;
414					interrupts = < 0x00 0x22 0x04 >;
415					clocks = < 0x04 0x73 0x04 0x73 >;
416					clock-names = "ipg\0per";
417					dmas = < 0x16 0x09 0x08 0x01 0x16 0x0a 0x08 0x02 >;
418					dma-names = "rx\0tx";
419					status = "disabled";
420				};
421
422				serial@2020000 {
423					compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
424					reg = < 0x2020000 0x4000 >;
425					interrupts = < 0x00 0x1a 0x04 >;
426					clocks = < 0x04 0xa0 0x04 0xa1 >;
427					clock-names = "ipg\0per";
428					dmas = < 0x16 0x19 0x04 0x00 0x16 0x1a 0x04 0x00 >;
429					dma-names = "rx\0tx";
430					status = "okay";
431					pinctrl-names = "default";
432					pinctrl-0 = < 0x18 >;
433				};
434
435				esai@2024000 {
436					#sound-dai-cells = < 0x00 >;
437					compatible = "fsl,imx35-esai";
438					reg = < 0x2024000 0x4000 >;
439					interrupts = < 0x00 0x33 0x04 >;
440					clocks = < 0x04 0xd0 0x04 0xd1 0x04 0x76 0x04 0xd0 0x04 0x9c >;
441					clock-names = "core\0mem\0extal\0fsys\0spba";
442					dmas = < 0x16 0x17 0x15 0x00 0x16 0x18 0x15 0x00 >;
443					dma-names = "rx\0tx";
444					status = "disabled";
445				};
446
447				ssi@2028000 {
448					#sound-dai-cells = < 0x00 >;
449					compatible = "fsl,imx6q-ssi\0fsl,imx51-ssi";
450					reg = < 0x2028000 0x4000 >;
451					interrupts = < 0x00 0x2e 0x04 >;
452					clocks = < 0x04 0xb2 0x04 0x9d >;
453					clock-names = "ipg\0baud";
454					dmas = < 0x16 0x25 0x01 0x00 0x16 0x26 0x01 0x00 >;
455					dma-names = "rx\0tx";
456					fsl,fifo-depth = < 0x0f >;
457					status = "okay";
458					phandle = < 0x5f >;
459				};
460
461				ssi@202c000 {
462					#sound-dai-cells = < 0x00 >;
463					compatible = "fsl,imx6q-ssi\0fsl,imx51-ssi";
464					reg = < 0x202c000 0x4000 >;
465					interrupts = < 0x00 0x2f 0x04 >;
466					clocks = < 0x04 0xb3 0x04 0x9e >;
467					clock-names = "ipg\0baud";
468					dmas = < 0x16 0x29 0x01 0x00 0x16 0x2a 0x01 0x00 >;
469					dma-names = "rx\0tx";
470					fsl,fifo-depth = < 0x0f >;
471					status = "disabled";
472				};
473
474				ssi@2030000 {
475					#sound-dai-cells = < 0x00 >;
476					compatible = "fsl,imx6q-ssi\0fsl,imx51-ssi";
477					reg = < 0x2030000 0x4000 >;
478					interrupts = < 0x00 0x30 0x04 >;
479					clocks = < 0x04 0xb4 0x04 0x9f >;
480					clock-names = "ipg\0baud";
481					dmas = < 0x16 0x2d 0x01 0x00 0x16 0x2e 0x01 0x00 >;
482					dma-names = "rx\0tx";
483					fsl,fifo-depth = < 0x0f >;
484					status = "disabled";
485				};
486
487				asrc@2034000 {
488					compatible = "fsl,imx53-asrc";
489					reg = < 0x2034000 0x4000 >;
490					interrupts = < 0x00 0x32 0x04 >;
491					clocks = < 0x04 0xd2 0x04 0xd3 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x6b 0x04 0x00 0x04 0x00 0x04 0x9c >;
492					clock-names = "mem\0ipg\0asrck_0\0asrck_1\0asrck_2\0asrck_3\0asrck_4\0asrck_5\0asrck_6\0asrck_7\0asrck_8\0asrck_9\0asrck_a\0asrck_b\0asrck_c\0asrck_d\0asrck_e\0asrck_f\0spba";
493					dmas = < 0x16 0x11 0x17 0x01 0x16 0x12 0x17 0x01 0x16 0x13 0x17 0x01 0x16 0x14 0x17 0x01 0x16 0x15 0x17 0x01 0x16 0x16 0x17 0x01 >;
494					dma-names = "rxa\0rxb\0rxc\0txa\0txb\0txc";
495					fsl,asrc-rate = < 0xbb80 >;
496					fsl,asrc-width = < 0x10 >;
497					status = "okay";
498				};
499
500				spba@203c000 {
501					reg = < 0x203c000 0x4000 >;
502				};
503
504				spi@2018000 {
505					#address-cells = < 0x01 >;
506					#size-cells = < 0x00 >;
507					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
508					reg = < 0x2018000 0x4000 >;
509					interrupts = < 0x00 0x23 0x04 >;
510					clocks = < 0x04 0x74 0x04 0x74 >;
511					clock-names = "ipg\0per";
512					dmas = < 0x16 0x0b 0x08 0x01 0x16 0x0c 0x08 0x02 >;
513					dma-names = "rx\0tx";
514					status = "disabled";
515				};
516			};
517
518			vpu@2040000 {
519				compatible = "fsl,imx6q-vpu\0cnm,coda960";
520				reg = < 0x2040000 0x3c000 >;
521				interrupts = < 0x00 0x0c 0x04 0x00 0x03 0x04 >;
522				interrupt-names = "bit\0jpeg";
523				clocks = < 0x04 0xa8 0x04 0x8c >;
524				clock-names = "per\0ahb";
525				power-domains = < 0x14 >;
526				resets = < 0x19 0x01 >;
527				iram = < 0x1a >;
528			};
529
530			aipstz@207c000 {
531				reg = < 0x207c000 0x4000 >;
532			};
533
534			pwm@2080000 {
535				#pwm-cells = < 0x02 >;
536				compatible = "fsl,imx6q-pwm\0fsl,imx27-pwm";
537				reg = < 0x2080000 0x4000 >;
538				interrupts = < 0x00 0x53 0x04 >;
539				clocks = < 0x04 0x3e 0x04 0x91 >;
540				clock-names = "ipg\0per";
541				status = "disabled";
542			};
543
544			pwm@2084000 {
545				#pwm-cells = < 0x02 >;
546				compatible = "fsl,imx6q-pwm\0fsl,imx27-pwm";
547				reg = < 0x2084000 0x4000 >;
548				interrupts = < 0x00 0x54 0x04 >;
549				clocks = < 0x04 0x3e 0x04 0x92 >;
550				clock-names = "ipg\0per";
551				status = "disabled";
552			};
553
554			pwm@2088000 {
555				#pwm-cells = < 0x02 >;
556				compatible = "fsl,imx6q-pwm\0fsl,imx27-pwm";
557				reg = < 0x2088000 0x4000 >;
558				interrupts = < 0x00 0x55 0x04 >;
559				clocks = < 0x04 0x3e 0x04 0x93 >;
560				clock-names = "ipg\0per";
561				status = "disabled";
562			};
563
564			pwm@208c000 {
565				#pwm-cells = < 0x02 >;
566				compatible = "fsl,imx6q-pwm\0fsl,imx27-pwm";
567				reg = < 0x208c000 0x4000 >;
568				interrupts = < 0x00 0x56 0x04 >;
569				clocks = < 0x04 0x3e 0x04 0x94 >;
570				clock-names = "ipg\0per";
571				status = "disabled";
572			};
573
574			flexcan@2090000 {
575				compatible = "fsl,imx6q-flexcan";
576				reg = < 0x2090000 0x4000 >;
577				interrupts = < 0x00 0x6e 0x04 >;
578				clocks = < 0x04 0x6c 0x04 0x6d >;
579				clock-names = "ipg\0per";
580				status = "disabled";
581			};
582
583			flexcan@2094000 {
584				compatible = "fsl,imx6q-flexcan";
585				reg = < 0x2094000 0x4000 >;
586				interrupts = < 0x00 0x6f 0x04 >;
587				clocks = < 0x04 0x6e 0x04 0x6f >;
588				clock-names = "ipg\0per";
589				status = "disabled";
590			};
591
592			gpt@2098000 {
593				compatible = "fsl,imx6q-gpt\0fsl,imx31-gpt";
594				reg = < 0x2098000 0x4000 >;
595				interrupts = < 0x00 0x37 0x04 >;
596				clocks = < 0x04 0x77 0x04 0x78 0x04 0xed >;
597				clock-names = "ipg\0per\0osc_per";
598			};
599
600			gpio@209c000 {
601				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
602				reg = < 0x209c000 0x4000 >;
603				interrupts = < 0x00 0x42 0x04 0x00 0x43 0x04 >;
604				gpio-controller;
605				#gpio-cells = < 0x02 >;
606				interrupt-controller;
607				#interrupt-cells = < 0x02 >;
608				gpio-ranges = < 0x1b 0x00 0x88 0x02 0x1b 0x02 0x8d 0x01 0x1b 0x03 0x8b 0x01 0x1b 0x04 0x8e 0x02 0x1b 0x06 0x8c 0x01 0x1b 0x07 0x90 0x02 0x1b 0x09 0x8a 0x01 0x1b 0x0a 0xd5 0x03 0x1b 0x0d 0x14 0x01 0x1b 0x0e 0x13 0x01 0x1b 0x0f 0x15 0x01 0x1b 0x10 0xd0 0x01 0x1b 0x11 0xcf 0x01 0x1b 0x12 0xd2 0x03 0x1b 0x15 0xd1 0x01 0x1b 0x16 0x74 0x0a >;
609				phandle = < 0x29 >;
610			};
611
612			gpio@20a0000 {
613				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
614				reg = < 0x20a0000 0x4000 >;
615				interrupts = < 0x00 0x44 0x04 0x00 0x45 0x04 >;
616				gpio-controller;
617				#gpio-cells = < 0x02 >;
618				interrupt-controller;
619				#interrupt-cells = < 0x02 >;
620				gpio-ranges = < 0x1b 0x00 0xbf 0x10 0x1b 0x10 0x37 0x0e 0x1b 0x1e 0x23 0x01 0x1b 0x1f 0x2c 0x01 >;
621			};
622
623			gpio@20a4000 {
624				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
625				reg = < 0x20a4000 0x4000 >;
626				interrupts = < 0x00 0x46 0x04 0x00 0x47 0x04 >;
627				gpio-controller;
628				#gpio-cells = < 0x02 >;
629				interrupt-controller;
630				#interrupt-cells = < 0x02 >;
631				gpio-ranges = < 0x1b 0x00 0x45 0x10 0x1b 0x10 0x24 0x08 0x1b 0x18 0x2d 0x08 >;
632				phandle = < 0x2b >;
633			};
634
635			gpio@20a8000 {
636				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
637				reg = < 0x20a8000 0x4000 >;
638				interrupts = < 0x00 0x48 0x04 0x00 0x49 0x04 >;
639				gpio-controller;
640				#gpio-cells = < 0x02 >;
641				interrupt-controller;
642				#interrupt-cells = < 0x02 >;
643				gpio-ranges = < 0x1b 0x05 0x95 0x01 0x1b 0x06 0x7e 0x0a 0x1b 0x10 0x57 0x10 >;
644			};
645
646			gpio@20ac000 {
647				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
648				reg = < 0x20ac000 0x4000 >;
649				interrupts = < 0x00 0x4a 0x04 0x00 0x4b 0x04 >;
650				gpio-controller;
651				#gpio-cells = < 0x02 >;
652				interrupt-controller;
653				#interrupt-cells = < 0x02 >;
654				gpio-ranges = < 0x1b 0x00 0x55 0x01 0x1b 0x02 0x22 0x01 0x1b 0x04 0x35 0x01 0x1b 0x05 0x67 0x0d 0x1b 0x12 0x96 0x0e >;
655			};
656
657			gpio@20b0000 {
658				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
659				reg = < 0x20b0000 0x4000 >;
660				interrupts = < 0x00 0x4c 0x04 0x00 0x4d 0x04 >;
661				gpio-controller;
662				#gpio-cells = < 0x02 >;
663				interrupt-controller;
664				#interrupt-cells = < 0x02 >;
665				gpio-ranges = < 0x1b 0x00 0xa4 0x06 0x1b 0x06 0x36 0x01 0x1b 0x07 0xb5 0x05 0x1b 0x0e 0xba 0x03 0x1b 0x11 0xaa 0x02 0x1b 0x13 0x16 0x0c 0x1b 0x1f 0x56 0x01 >;
666			};
667
668			gpio@20b4000 {
669				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
670				reg = < 0x20b4000 0x4000 >;
671				interrupts = < 0x00 0x4e 0x04 0x00 0x4f 0x04 >;
672				gpio-controller;
673				#gpio-cells = < 0x02 >;
674				interrupt-controller;
675				#interrupt-cells = < 0x02 >;
676				gpio-ranges = < 0x1b 0x00 0xac 0x09 0x1b 0x09 0xbd 0x02 0x1b 0x0b 0x92 0x03 >;
677				phandle = < 0x63 >;
678			};
679
680			kpp@20b8000 {
681				compatible = "fsl,imx6q-kpp\0fsl,imx21-kpp";
682				reg = < 0x20b8000 0x4000 >;
683				interrupts = < 0x00 0x52 0x04 >;
684				clocks = < 0x04 0x3e >;
685				status = "disabled";
686			};
687
688			wdog@20bc000 {
689				compatible = "fsl,imx6q-wdt\0fsl,imx21-wdt";
690				reg = < 0x20bc000 0x4000 >;
691				interrupts = < 0x00 0x50 0x04 >;
692				clocks = < 0x04 0x00 >;
693			};
694
695			wdog@20c0000 {
696				compatible = "fsl,imx6q-wdt\0fsl,imx21-wdt";
697				reg = < 0x20c0000 0x4000 >;
698				interrupts = < 0x00 0x51 0x04 >;
699				clocks = < 0x04 0x00 >;
700				status = "disabled";
701			};
702
703			ccm@20c4000 {
704				compatible = "fsl,imx6q-ccm";
705				reg = < 0x20c4000 0x4000 >;
706				interrupts = < 0x00 0x57 0x04 0x00 0x58 0x04 >;
707				#clock-cells = < 0x01 >;
708				phandle = < 0x04 >;
709			};
710
711			anatop@20c8000 {
712				compatible = "fsl,imx6q-anatop\0syscon\0simple-bus";
713				reg = < 0x20c8000 0x1000 >;
714				interrupts = < 0x00 0x31 0x04 0x00 0x36 0x04 0x00 0x7f 0x04 >;
715				phandle = < 0x02 >;
716
717				regulator-1p1 {
718					compatible = "fsl,anatop-regulator";
719					regulator-name = "vdd1p1";
720					regulator-min-microvolt = < 0xf4240 >;
721					regulator-max-microvolt = < 0x124f80 >;
722					regulator-always-on;
723					anatop-reg-offset = < 0x110 >;
724					anatop-vol-bit-shift = < 0x08 >;
725					anatop-vol-bit-width = < 0x05 >;
726					anatop-min-bit-val = < 0x04 >;
727					anatop-min-voltage = < 0xc3500 >;
728					anatop-max-voltage = < 0x14fb18 >;
729					anatop-enable-bit = < 0x00 >;
730				};
731
732				regulator-3p0 {
733					compatible = "fsl,anatop-regulator";
734					regulator-name = "vdd3p0";
735					regulator-min-microvolt = < 0x2ab980 >;
736					regulator-max-microvolt = < 0x3010b0 >;
737					regulator-always-on;
738					anatop-reg-offset = < 0x120 >;
739					anatop-vol-bit-shift = < 0x08 >;
740					anatop-vol-bit-width = < 0x05 >;
741					anatop-min-bit-val = < 0x00 >;
742					anatop-min-voltage = < 0x280de8 >;
743					anatop-max-voltage = < 0x33e140 >;
744					anatop-enable-bit = < 0x00 >;
745				};
746
747				regulator-2p5 {
748					compatible = "fsl,anatop-regulator";
749					regulator-name = "vdd2p5";
750					regulator-min-microvolt = < 0x225510 >;
751					regulator-max-microvolt = < 0x29f630 >;
752					regulator-always-on;
753					anatop-reg-offset = < 0x130 >;
754					anatop-vol-bit-shift = < 0x08 >;
755					anatop-vol-bit-width = < 0x05 >;
756					anatop-min-bit-val = < 0x00 >;
757					anatop-min-voltage = < 0x200b20 >;
758					anatop-max-voltage = < 0x2bde78 >;
759					anatop-enable-bit = < 0x00 >;
760				};
761
762				regulator-vddcore {
763					compatible = "fsl,anatop-regulator";
764					regulator-name = "vddarm";
765					regulator-min-microvolt = < 0xb1008 >;
766					regulator-max-microvolt = < 0x162010 >;
767					regulator-always-on;
768					anatop-reg-offset = < 0x140 >;
769					anatop-vol-bit-shift = < 0x00 >;
770					anatop-vol-bit-width = < 0x05 >;
771					anatop-delay-reg-offset = < 0x170 >;
772					anatop-delay-bit-shift = < 0x18 >;
773					anatop-delay-bit-width = < 0x02 >;
774					anatop-min-bit-val = < 0x01 >;
775					anatop-min-voltage = < 0xb1008 >;
776					anatop-max-voltage = < 0x162010 >;
777					phandle = < 0x55 >;
778				};
779
780				regulator-vddpu {
781					compatible = "fsl,anatop-regulator";
782					regulator-name = "vddpu";
783					regulator-min-microvolt = < 0xb1008 >;
784					regulator-max-microvolt = < 0x162010 >;
785					regulator-enable-ramp-delay = < 0x96 >;
786					anatop-reg-offset = < 0x140 >;
787					anatop-vol-bit-shift = < 0x09 >;
788					anatop-vol-bit-width = < 0x05 >;
789					anatop-delay-reg-offset = < 0x170 >;
790					anatop-delay-bit-shift = < 0x1a >;
791					anatop-delay-bit-width = < 0x02 >;
792					anatop-min-bit-val = < 0x01 >;
793					anatop-min-voltage = < 0xb1008 >;
794					anatop-max-voltage = < 0x162010 >;
795					phandle = < 0x1d >;
796				};
797
798				regulator-vddsoc {
799					compatible = "fsl,anatop-regulator";
800					regulator-name = "vddsoc";
801					regulator-min-microvolt = < 0xb1008 >;
802					regulator-max-microvolt = < 0x162010 >;
803					regulator-always-on;
804					anatop-reg-offset = < 0x140 >;
805					anatop-vol-bit-shift = < 0x12 >;
806					anatop-vol-bit-width = < 0x05 >;
807					anatop-delay-reg-offset = < 0x170 >;
808					anatop-delay-bit-shift = < 0x1c >;
809					anatop-delay-bit-width = < 0x02 >;
810					anatop-min-bit-val = < 0x01 >;
811					anatop-min-voltage = < 0xb1008 >;
812					anatop-max-voltage = < 0x162010 >;
813					phandle = < 0x56 >;
814				};
815			};
816
817			usbphy@20c9000 {
818				compatible = "fsl,imx6q-usbphy\0fsl,imx23-usbphy";
819				reg = < 0x20c9000 0x1000 >;
820				interrupts = < 0x00 0x2c 0x04 >;
821				clocks = < 0x04 0xb6 >;
822				fsl,anatop = < 0x02 >;
823				phandle = < 0x24 >;
824			};
825
826			usbphy@20ca000 {
827				compatible = "fsl,imx6q-usbphy\0fsl,imx23-usbphy";
828				reg = < 0x20ca000 0x1000 >;
829				interrupts = < 0x00 0x2d 0x04 >;
830				clocks = < 0x04 0xb7 >;
831				fsl,anatop = < 0x02 >;
832				phandle = < 0x28 >;
833			};
834
835			snvs@20cc000 {
836				compatible = "fsl,sec-v4.0-mon\0syscon\0simple-mfd";
837				reg = < 0x20cc000 0x4000 >;
838				phandle = < 0x1c >;
839
840				snvs-rtc-lp {
841					compatible = "fsl,sec-v4.0-mon-rtc-lp";
842					regmap = < 0x1c >;
843					offset = < 0x34 >;
844					interrupts = < 0x00 0x13 0x04 0x00 0x14 0x04 >;
845				};
846
847				snvs-poweroff {
848					compatible = "syscon-poweroff";
849					regmap = < 0x1c >;
850					offset = < 0x38 >;
851					value = < 0x60 >;
852					mask = < 0x60 >;
853					status = "disabled";
854				};
855
856				snvs-lpgpr {
857					compatible = "fsl,imx6q-snvs-lpgpr";
858				};
859			};
860
861			epit@20d0000 {
862				reg = < 0x20d0000 0x4000 >;
863				interrupts = < 0x00 0x38 0x04 >;
864			};
865
866			epit@20d4000 {
867				reg = < 0x20d4000 0x4000 >;
868				interrupts = < 0x00 0x39 0x04 >;
869			};
870
871			src@20d8000 {
872				compatible = "fsl,imx6q-src\0fsl,imx51-src";
873				reg = < 0x20d8000 0x4000 >;
874				interrupts = < 0x00 0x5b 0x04 0x00 0x60 0x04 >;
875				#reset-cells = < 0x01 >;
876				phandle = < 0x19 >;
877			};
878
879			gpc@20dc000 {
880				compatible = "fsl,imx6q-gpc";
881				reg = < 0x20dc000 0x4000 >;
882				interrupt-controller;
883				#interrupt-cells = < 0x03 >;
884				interrupts = < 0x00 0x59 0x04 0x00 0x5a 0x04 >;
885				interrupt-parent = < 0x15 >;
886				clocks = < 0x04 0x3e >;
887				clock-names = "ipg";
888				phandle = < 0x01 >;
889
890				pgc {
891					#address-cells = < 0x01 >;
892					#size-cells = < 0x00 >;
893
894					power-domain@0 {
895						reg = < 0x00 >;
896						#power-domain-cells = < 0x00 >;
897					};
898
899					power-domain@1 {
900						reg = < 0x01 >;
901						#power-domain-cells = < 0x00 >;
902						power-supply = < 0x1d >;
903						clocks = < 0x04 0x7a 0x04 0x4a 0x04 0x79 0x04 0x1a 0x04 0x8f 0x04 0xa8 >;
904						phandle = < 0x14 >;
905					};
906				};
907			};
908
909			iomuxc-gpr@20e0000 {
910				compatible = "fsl,imx6q-iomuxc-gpr\0syscon\0simple-mfd";
911				reg = < 0x20e0000 0x38 >;
912				phandle = < 0x05 >;
913
914				mux-controller {
915					compatible = "mmio-mux";
916					#mux-control-cells = < 0x01 >;
917					mux-reg-masks = < 0x04 0x80000 0x04 0x100000 0x0c 0x0c 0x0c 0xc0 0x0c 0x300 0x28 0x03 0x28 0x0c >;
918					phandle = < 0x1e >;
919				};
920
921				ipu1_csi0_mux {
922					compatible = "video-mux";
923					mux-controls = < 0x1e 0x00 >;
924					#address-cells = < 0x01 >;
925					#size-cells = < 0x00 >;
926
927					port@0 {
928						reg = < 0x00 >;
929
930						endpoint {
931							remote-endpoint = < 0x1f >;
932							phandle = < 0x37 >;
933						};
934					};
935
936					port@1 {
937						reg = < 0x01 >;
938
939						endpoint {
940						};
941					};
942
943					port@2 {
944						reg = < 0x02 >;
945
946						endpoint {
947							remote-endpoint = < 0x20 >;
948							phandle = < 0x40 >;
949						};
950					};
951				};
952
953				ipu2_csi1_mux {
954					compatible = "video-mux";
955					mux-controls = < 0x1e 0x01 >;
956					#address-cells = < 0x01 >;
957					#size-cells = < 0x00 >;
958
959					port@0 {
960						reg = < 0x00 >;
961
962						endpoint {
963							remote-endpoint = < 0x21 >;
964							phandle = < 0x3a >;
965						};
966					};
967
968					port@1 {
969						reg = < 0x01 >;
970
971						endpoint {
972						};
973					};
974
975					port@2 {
976						reg = < 0x02 >;
977
978						endpoint {
979							remote-endpoint = < 0x22 >;
980							phandle = < 0x4b >;
981						};
982					};
983				};
984			};
985
986			iomuxc@20e0000 {
987				compatible = "fsl,imx6q-iomuxc";
988				reg = < 0x20e0000 0x4000 >;
989				pinctrl-names = "default";
990				pinctrl-0 = < 0x23 >;
991				phandle = < 0x1b >;
992
993				imx6qdl-wandboard {
994
995					audmuxgrp {
996						fsl,pins = < 0x274 0x644 0x00 0x04 0x00 0x130b0 0x268 0x638 0x00 0x04 0x00 0x130b0 0x26c 0x63c 0x00 0x04 0x00 0x110b0 0x270 0x640 0x00 0x04 0x00 0x130b0 >;
997						phandle = < 0x36 >;
998					};
999
1000					enetgrp {
1001						fsl,pins = < 0x1d0 0x4e4 0x840 0x01 0x00 0x1b0b0 0x1f4 0x508 0x00 0x01 0x00 0x1b0b0 0x58 0x36c 0x00 0x01 0x00 0x1b030 0x5c 0x370 0x00 0x01 0x00 0x1b030 0x60 0x374 0x00 0x01 0x00 0x1b030 0x64 0x378 0x00 0x01 0x00 0x1b030 0x68 0x37c 0x00 0x01 0x00 0x1b030 0x74 0x388 0x00 0x01 0x00 0x1b030 0x1d4 0x4e8 0x00 0x01 0x00 0x1b0b0 0x84 0x398 0x844 0x01 0x00 0x1b030 0x70 0x384 0x848 0x01 0x00 0x1b030 0x78 0x38c 0x84c 0x01 0x00 0x1b030 0x7c 0x390 0x850 0x01 0x00 0x1b030 0x80 0x394 0x854 0x01 0x00 0x1b030 0x6c 0x380 0x858 0x01 0x00 0x1b030 0x230 0x600 0x3c 0x11 0xff000609 0xb1 >;
1002						phandle = < 0x2a >;
1003					};
1004
1005					i2c1grp {
1006						fsl,pins = < 0xa4 0x3b8 0x898 0x06 0x00 0x4001b8b1 0xc4 0x3d8 0x89c 0x01 0x00 0x4001b8b1 >;
1007						phandle = < 0x30 >;
1008					};
1009
1010					i2c2grp {
1011						fsl,pins = < 0x210 0x5e0 0x8a0 0x04 0x01 0x4001b8b1 0x214 0x5e4 0x8a4 0x04 0x01 0x4001b8b1 >;
1012						phandle = < 0x31 >;
1013					};
1014
1015					mclkgrp {
1016						fsl,pins = < 0x220 0x5f0 0x00 0x00 0x00 0x130b0 >;
1017						phandle = < 0x32 >;
1018					};
1019
1020					spdifgrp {
1021						fsl,pins = < 0x254 0x624 0x00 0x02 0x00 0x1b0b0 >;
1022						phandle = < 0x17 >;
1023					};
1024
1025					uart1grp {
1026						fsl,pins = < 0x280 0x650 0x00 0x03 0x00 0x1b0b1 0x284 0x654 0x920 0x03 0x01 0x1b0b1 >;
1027						phandle = < 0x18 >;
1028					};
1029
1030					uart3grp {
1031						fsl,pins = < 0xb4 0x3c8 0x00 0x02 0x00 0x1b0b1 0xb8 0x3cc 0x930 0x02 0x01 0x1b0b1 0xac 0x3c0 0x00 0x02 0x00 0x1b0b1 0xb0 0x3c4 0x92c 0x02 0x01 0x1b0b1 >;
1032						phandle = < 0x3f >;
1033					};
1034
1035					usbotggrp {
1036						fsl,pins = < 0x224 0x5f4 0x04 0x03 0xff0d0101 0x17059 >;
1037						phandle = < 0x27 >;
1038					};
1039
1040					usbotgvbusgrp {
1041						fsl,pins = < 0xa8 0x3bc 0x00 0x05 0x00 0x130b0 >;
1042						phandle = < 0x62 >;
1043					};
1044
1045					usdhc1grp {
1046						fsl,pins = < 0x348 0x730 0x00 0x00 0x00 0x17059 0x350 0x738 0x00 0x00 0x00 0x10059 0x340 0x728 0x00 0x00 0x00 0x17059 0x33c 0x724 0x00 0x00 0x00 0x17059 0x34c 0x734 0x00 0x00 0x00 0x17059 0x344 0x72c 0x00 0x00 0x00 0x17059 >;
1047						phandle = < 0x2d >;
1048					};
1049
1050					usdhc2grp {
1051						fsl,pins = < 0x358 0x740 0x00 0x00 0x00 0x17059 0x354 0x73c 0x00 0x00 0x00 0x10059 0x54 0x368 0x00 0x00 0x00 0x17059 0x4c 0x360 0x00 0x00 0x00 0x17059 0x50 0x364 0x00 0x00 0x00 0x17059 0x35c 0x744 0x00 0x00 0x00 0x17059 >;
1052						phandle = < 0x2e >;
1053					};
1054
1055					usdhc3grp {
1056						fsl,pins = < 0x2b8 0x6a0 0x00 0x00 0x00 0x17059 0x2bc 0x6a4 0x00 0x00 0x00 0x10059 0x2c0 0x6a8 0x00 0x00 0x00 0x17059 0x2c4 0x6ac 0x00 0x00 0x00 0x17059 0x2c8 0x6b0 0x00 0x00 0x00 0x17059 0x2cc 0x6b4 0x00 0x00 0x00 0x17059 >;
1057						phandle = < 0x2f >;
1058					};
1059
1060					hoggrp {
1061						fsl,pins = < 0xa8 0x3bc 0x00 0x04 0x00 0x80000000 0x234 0x604 0x00 0x05 0x00 0x80000000 0x138 0x44c 0x00 0x05 0x00 0x80000000 0xc8 0x3dc 0x00 0x05 0x00 0x1f0b1 >;
1062						phandle = < 0x23 >;
1063					};
1064
1065					i2c3grp {
1066						fsl,pins = < 0x23c 0x60c 0x8a8 0x06 0x02 0x4001b8b1 0x248 0x618 0x8ac 0x06 0x02 0x4001b8b1 >;
1067						phandle = < 0x35 >;
1068					};
1069				};
1070			};
1071
1072			dcic@20e4000 {
1073				reg = < 0x20e4000 0x4000 >;
1074				interrupts = < 0x00 0x7c 0x04 >;
1075			};
1076
1077			dcic@20e8000 {
1078				reg = < 0x20e8000 0x4000 >;
1079				interrupts = < 0x00 0x7d 0x04 >;
1080			};
1081
1082			sdma@20ec000 {
1083				compatible = "fsl,imx6q-sdma\0fsl,imx35-sdma";
1084				reg = < 0x20ec000 0x4000 >;
1085				interrupts = < 0x00 0x02 0x04 >;
1086				clocks = < 0x04 0x9b 0x04 0x9b >;
1087				clock-names = "ipg\0ahb";
1088				#dma-cells = < 0x03 >;
1089				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
1090				phandle = < 0x16 >;
1091			};
1092		};
1093
1094		aips-bus@2100000 {
1095			compatible = "fsl,aips-bus\0simple-bus";
1096			#address-cells = < 0x01 >;
1097			#size-cells = < 0x01 >;
1098			reg = < 0x2100000 0x100000 >;
1099			ranges;
1100
1101			caam@2100000 {
1102				compatible = "fsl,sec-v4.0";
1103				#address-cells = < 0x01 >;
1104				#size-cells = < 0x01 >;
1105				reg = < 0x2100000 0x10000 >;
1106				ranges = < 0x00 0x2100000 0x10000 >;
1107				clocks = < 0x04 0xf1 0x04 0xf2 0x04 0xf3 0x04 0xc4 >;
1108				clock-names = "mem\0aclk\0ipg\0emi_slow";
1109
1110				jr0@1000 {
1111					compatible = "fsl,sec-v4.0-job-ring";
1112					reg = < 0x1000 0x1000 >;
1113					interrupts = < 0x00 0x69 0x04 >;
1114				};
1115
1116				jr1@2000 {
1117					compatible = "fsl,sec-v4.0-job-ring";
1118					reg = < 0x2000 0x1000 >;
1119					interrupts = < 0x00 0x6a 0x04 >;
1120				};
1121			};
1122
1123			aipstz@217c000 {
1124				reg = < 0x217c000 0x4000 >;
1125			};
1126
1127			usb@2184000 {
1128				compatible = "fsl,imx6q-usb\0fsl,imx27-usb";
1129				reg = < 0x2184000 0x200 >;
1130				interrupts = < 0x00 0x2b 0x04 >;
1131				clocks = < 0x04 0xa2 >;
1132				fsl,usbphy = < 0x24 >;
1133				fsl,usbmisc = < 0x25 0x00 >;
1134				ahb-burst-config = < 0x00 >;
1135				tx-burst-size-dword = < 0x10 >;
1136				rx-burst-size-dword = < 0x10 >;
1137				status = "okay";
1138				vbus-supply = < 0x26 >;
1139				pinctrl-names = "default";
1140				pinctrl-0 = < 0x27 >;
1141				disable-over-current;
1142				dr_mode = "otg";
1143			};
1144
1145			usb@2184200 {
1146				compatible = "fsl,imx6q-usb\0fsl,imx27-usb";
1147				reg = < 0x2184200 0x200 >;
1148				interrupts = < 0x00 0x28 0x04 >;
1149				clocks = < 0x04 0xa2 >;
1150				fsl,usbphy = < 0x28 >;
1151				fsl,usbmisc = < 0x25 0x01 >;
1152				dr_mode = "host";
1153				ahb-burst-config = < 0x00 >;
1154				tx-burst-size-dword = < 0x10 >;
1155				rx-burst-size-dword = < 0x10 >;
1156				status = "okay";
1157			};
1158
1159			usb@2184400 {
1160				compatible = "fsl,imx6q-usb\0fsl,imx27-usb";
1161				reg = < 0x2184400 0x200 >;
1162				interrupts = < 0x00 0x29 0x04 >;
1163				clocks = < 0x04 0xa2 >;
1164				fsl,usbmisc = < 0x25 0x02 >;
1165				dr_mode = "host";
1166				ahb-burst-config = < 0x00 >;
1167				tx-burst-size-dword = < 0x10 >;
1168				rx-burst-size-dword = < 0x10 >;
1169				status = "disabled";
1170			};
1171
1172			usb@2184600 {
1173				compatible = "fsl,imx6q-usb\0fsl,imx27-usb";
1174				reg = < 0x2184600 0x200 >;
1175				interrupts = < 0x00 0x2a 0x04 >;
1176				clocks = < 0x04 0xa2 >;
1177				fsl,usbmisc = < 0x25 0x03 >;
1178				dr_mode = "host";
1179				ahb-burst-config = < 0x00 >;
1180				tx-burst-size-dword = < 0x10 >;
1181				rx-burst-size-dword = < 0x10 >;
1182				status = "disabled";
1183			};
1184
1185			usbmisc@2184800 {
1186				#index-cells = < 0x01 >;
1187				compatible = "fsl,imx6q-usbmisc";
1188				reg = < 0x2184800 0x200 >;
1189				clocks = < 0x04 0xa2 >;
1190				phandle = < 0x25 >;
1191			};
1192
1193			ethernet@2188000 {
1194				compatible = "fsl,imx6q-fec";
1195				reg = < 0x2188000 0x4000 >;
1196				interrupt-names = "int0\0pps";
1197				interrupts-extended = < 0x29 0x06 0x04 0x15 0x00 0x77 0x04 >;
1198				clocks = < 0x04 0x75 0x04 0x75 0x04 0xbe >;
1199				clock-names = "ipg\0ahb\0ptp";
1200				status = "okay";
1201				pinctrl-names = "default";
1202				pinctrl-0 = < 0x2a >;
1203				phy-mode = "rgmii";
1204				phy-reset-gpios = < 0x2b 0x1d 0x01 >;
1205				fsl,err006687-workaround-present;
1206				phy-supply = < 0x2c >;
1207			};
1208
1209			mlb@218c000 {
1210				reg = < 0x218c000 0x4000 >;
1211				interrupts = < 0x00 0x35 0x04 0x00 0x75 0x04 0x00 0x7e 0x04 >;
1212			};
1213
1214			usdhc@2190000 {
1215				compatible = "fsl,imx6q-usdhc";
1216				reg = < 0x2190000 0x4000 >;
1217				interrupts = < 0x00 0x16 0x04 >;
1218				clocks = < 0x04 0xa3 0x04 0xa3 0x04 0xa3 >;
1219				clock-names = "ipg\0ahb\0per";
1220				bus-width = < 0x04 >;
1221				status = "okay";
1222				pinctrl-names = "default";
1223				pinctrl-0 = < 0x2d >;
1224				cd-gpios = < 0x29 0x02 0x01 >;
1225			};
1226
1227			usdhc@2194000 {
1228				compatible = "fsl,imx6q-usdhc";
1229				reg = < 0x2194000 0x4000 >;
1230				interrupts = < 0x00 0x17 0x04 >;
1231				clocks = < 0x04 0xa4 0x04 0xa4 0x04 0xa4 >;
1232				clock-names = "ipg\0ahb\0per";
1233				bus-width = < 0x04 >;
1234				status = "okay";
1235				pinctrl-names = "default";
1236				pinctrl-0 = < 0x2e >;
1237				no-1-8-v;
1238				non-removable;
1239			};
1240
1241			usdhc@2198000 {
1242				compatible = "fsl,imx6q-usdhc";
1243				reg = < 0x2198000 0x4000 >;
1244				interrupts = < 0x00 0x18 0x04 >;
1245				clocks = < 0x04 0xa5 0x04 0xa5 0x04 0xa5 >;
1246				clock-names = "ipg\0ahb\0per";
1247				bus-width = < 0x04 >;
1248				status = "okay";
1249				pinctrl-names = "default";
1250				pinctrl-0 = < 0x2f >;
1251				cd-gpios = < 0x2b 0x09 0x01 >;
1252			};
1253
1254			usdhc@219c000 {
1255				compatible = "fsl,imx6q-usdhc";
1256				reg = < 0x219c000 0x4000 >;
1257				interrupts = < 0x00 0x19 0x04 >;
1258				clocks = < 0x04 0xa6 0x04 0xa6 0x04 0xa6 >;
1259				clock-names = "ipg\0ahb\0per";
1260				bus-width = < 0x04 >;
1261				status = "disabled";
1262			};
1263
1264			i2c@21a0000 {
1265				#address-cells = < 0x01 >;
1266				#size-cells = < 0x00 >;
1267				compatible = "fsl,imx6q-i2c\0fsl,imx21-i2c";
1268				reg = < 0x21a0000 0x4000 >;
1269				interrupts = < 0x00 0x24 0x04 >;
1270				clocks = < 0x04 0x7d >;
1271				status = "okay";
1272				clock-frequency = < 0x186a0 >;
1273				pinctrl-names = "default";
1274				pinctrl-0 = < 0x30 >;
1275			};
1276
1277			i2c@21a4000 {
1278				#address-cells = < 0x01 >;
1279				#size-cells = < 0x00 >;
1280				compatible = "fsl,imx6q-i2c\0fsl,imx21-i2c";
1281				reg = < 0x21a4000 0x4000 >;
1282				interrupts = < 0x00 0x25 0x04 >;
1283				clocks = < 0x04 0x7e >;
1284				status = "okay";
1285				clock-frequency = < 0x186a0 >;
1286				pinctrl-names = "default";
1287				pinctrl-0 = < 0x31 >;
1288				phandle = < 0x0f >;
1289
1290				sgtl5000@a {
1291					pinctrl-names = "default";
1292					pinctrl-0 = < 0x32 >;
1293					compatible = "fsl,sgtl5000";
1294					reg = < 0x0a >;
1295					clocks = < 0x04 0xc9 >;
1296					VDDA-supply = < 0x33 >;
1297					VDDIO-supply = < 0x34 >;
1298					lrclk-strength = < 0x03 >;
1299					phandle = < 0x60 >;
1300				};
1301			};
1302
1303			i2c@21a8000 {
1304				#address-cells = < 0x01 >;
1305				#size-cells = < 0x00 >;
1306				compatible = "fsl,imx6q-i2c\0fsl,imx21-i2c";
1307				reg = < 0x21a8000 0x4000 >;
1308				interrupts = < 0x00 0x26 0x04 >;
1309				clocks = < 0x04 0x7f >;
1310				status = "okay";
1311				clock-frequency = < 0x186a0 >;
1312				pinctrl-names = "default";
1313				pinctrl-0 = < 0x35 >;
1314
1315				pfuze100@8 {
1316					compatible = "fsl,pfuze100";
1317					reg = < 0x08 >;
1318
1319					regulators {
1320
1321						sw1ab {
1322							regulator-min-microvolt = < 0x493e0 >;
1323							regulator-max-microvolt = < 0x1c9c38 >;
1324							regulator-boot-on;
1325							regulator-always-on;
1326							regulator-ramp-delay = < 0x186a >;
1327						};
1328
1329						sw1c {
1330							regulator-min-microvolt = < 0x493e0 >;
1331							regulator-max-microvolt = < 0x1c9c38 >;
1332							regulator-boot-on;
1333							regulator-always-on;
1334							regulator-ramp-delay = < 0x186a >;
1335						};
1336
1337						sw2 {
1338							regulator-min-microvolt = < 0xc3500 >;
1339							regulator-max-microvolt = < 0x325aa0 >;
1340							regulator-boot-on;
1341							regulator-always-on;
1342							regulator-ramp-delay = < 0x186a >;
1343						};
1344
1345						sw3a {
1346							regulator-min-microvolt = < 0x61a80 >;
1347							regulator-max-microvolt = < 0x1e22d8 >;
1348							regulator-boot-on;
1349							regulator-always-on;
1350						};
1351
1352						sw3b {
1353							regulator-min-microvolt = < 0x61a80 >;
1354							regulator-max-microvolt = < 0x1e22d8 >;
1355							regulator-boot-on;
1356							regulator-always-on;
1357						};
1358
1359						sw4 {
1360							regulator-min-microvolt = < 0xc3500 >;
1361							regulator-max-microvolt = < 0x325aa0 >;
1362						};
1363
1364						swbst {
1365							regulator-min-microvolt = < 0x4c4b40 >;
1366							regulator-max-microvolt = < 0x4e9530 >;
1367						};
1368
1369						vsnvs {
1370							regulator-min-microvolt = < 0xf4240 >;
1371							regulator-max-microvolt = < 0x2dc6c0 >;
1372							regulator-boot-on;
1373							regulator-always-on;
1374						};
1375
1376						vrefddr {
1377							regulator-boot-on;
1378							regulator-always-on;
1379						};
1380
1381						vgen1 {
1382							regulator-min-microvolt = < 0xc3500 >;
1383							regulator-max-microvolt = < 0x17a6b0 >;
1384						};
1385
1386						vgen2 {
1387							regulator-min-microvolt = < 0x16e360 >;
1388							regulator-max-microvolt = < 0x16e360 >;
1389							regulator-boot-on;
1390							regulator-always-on;
1391						};
1392
1393						vgen3 {
1394							regulator-min-microvolt = < 0x1b7740 >;
1395							regulator-max-microvolt = < 0x325aa0 >;
1396							regulator-always-on;
1397						};
1398
1399						vgen4 {
1400							regulator-min-microvolt = < 0x1b7740 >;
1401							regulator-max-microvolt = < 0x325aa0 >;
1402							regulator-always-on;
1403						};
1404
1405						vgen5 {
1406							regulator-min-microvolt = < 0x1b7740 >;
1407							regulator-max-microvolt = < 0x325aa0 >;
1408							regulator-always-on;
1409						};
1410
1411						vgen6 {
1412							regulator-min-microvolt = < 0x1b7740 >;
1413							regulator-max-microvolt = < 0x325aa0 >;
1414							regulator-always-on;
1415						};
1416					};
1417				};
1418			};
1419
1420			romcp@21ac000 {
1421				reg = < 0x21ac000 0x4000 >;
1422			};
1423
1424			mmdc@21b0000 {
1425				compatible = "fsl,imx6q-mmdc";
1426				reg = < 0x21b0000 0x4000 >;
1427			};
1428
1429			mmdc@21b4000 {
1430				reg = < 0x21b4000 0x4000 >;
1431			};
1432
1433			weim@21b8000 {
1434				#address-cells = < 0x02 >;
1435				#size-cells = < 0x01 >;
1436				compatible = "fsl,imx6q-weim";
1437				reg = < 0x21b8000 0x4000 >;
1438				interrupts = < 0x00 0x0e 0x04 >;
1439				clocks = < 0x04 0xc4 >;
1440				fsl,weim-cs-gpr = < 0x05 >;
1441				status = "disabled";
1442			};
1443
1444			ocotp@21bc000 {
1445				compatible = "fsl,imx6q-ocotp\0syscon";
1446				reg = < 0x21bc000 0x4000 >;
1447				clocks = < 0x04 0x80 >;
1448				phandle = < 0x03 >;
1449			};
1450
1451			tzasc@21d0000 {
1452				reg = < 0x21d0000 0x4000 >;
1453				interrupts = < 0x00 0x6c 0x04 >;
1454			};
1455
1456			tzasc@21d4000 {
1457				reg = < 0x21d4000 0x4000 >;
1458				interrupts = < 0x00 0x6d 0x04 >;
1459			};
1460
1461			audmux@21d8000 {
1462				compatible = "fsl,imx6q-audmux\0fsl,imx31-audmux";
1463				reg = < 0x21d8000 0x4000 >;
1464				status = "okay";
1465				pinctrl-names = "default";
1466				pinctrl-0 = < 0x36 >;
1467			};
1468
1469			mipi@21dc000 {
1470				compatible = "fsl,imx6-mipi-csi2";
1471				reg = < 0x21dc000 0x4000 >;
1472				#address-cells = < 0x01 >;
1473				#size-cells = < 0x00 >;
1474				interrupts = < 0x00 0x64 0x04 0x00 0x65 0x04 >;
1475				clocks = < 0x04 0x8a 0x04 0xee 0x04 0x61 >;
1476				clock-names = "dphy\0ref\0pix";
1477				status = "disabled";
1478
1479				port@1 {
1480					reg = < 0x01 >;
1481
1482					endpoint {
1483						remote-endpoint = < 0x37 >;
1484						phandle = < 0x1f >;
1485					};
1486				};
1487
1488				port@2 {
1489					reg = < 0x02 >;
1490
1491					endpoint {
1492						remote-endpoint = < 0x38 >;
1493						phandle = < 0x41 >;
1494					};
1495				};
1496
1497				port@3 {
1498					reg = < 0x03 >;
1499
1500					endpoint {
1501						remote-endpoint = < 0x39 >;
1502						phandle = < 0x4a >;
1503					};
1504				};
1505
1506				port@4 {
1507					reg = < 0x04 >;
1508
1509					endpoint {
1510						remote-endpoint = < 0x3a >;
1511						phandle = < 0x21 >;
1512					};
1513				};
1514			};
1515
1516			mipi@21e0000 {
1517				reg = < 0x21e0000 0x4000 >;
1518				status = "disabled";
1519
1520				ports {
1521					#address-cells = < 0x01 >;
1522					#size-cells = < 0x00 >;
1523
1524					port@0 {
1525						reg = < 0x00 >;
1526
1527						endpoint {
1528							remote-endpoint = < 0x3b >;
1529							phandle = < 0x43 >;
1530						};
1531					};
1532
1533					port@1 {
1534						reg = < 0x01 >;
1535
1536						endpoint {
1537							remote-endpoint = < 0x3c >;
1538							phandle = < 0x47 >;
1539						};
1540					};
1541
1542					port@2 {
1543						reg = < 0x02 >;
1544
1545						endpoint {
1546							remote-endpoint = < 0x3d >;
1547							phandle = < 0x4d >;
1548						};
1549					};
1550
1551					port@3 {
1552						reg = < 0x03 >;
1553
1554						endpoint {
1555							remote-endpoint = < 0x3e >;
1556							phandle = < 0x51 >;
1557						};
1558					};
1559				};
1560			};
1561
1562			vdoa@21e4000 {
1563				compatible = "fsl,imx6q-vdoa";
1564				reg = < 0x21e4000 0x4000 >;
1565				interrupts = < 0x00 0x12 0x04 >;
1566				clocks = < 0x04 0xca >;
1567			};
1568
1569			serial@21e8000 {
1570				compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
1571				reg = < 0x21e8000 0x4000 >;
1572				interrupts = < 0x00 0x1b 0x04 >;
1573				clocks = < 0x04 0xa0 0x04 0xa1 >;
1574				clock-names = "ipg\0per";
1575				dmas = < 0x16 0x1b 0x04 0x00 0x16 0x1c 0x04 0x00 >;
1576				dma-names = "rx\0tx";
1577				status = "disabled";
1578			};
1579
1580			serial@21ec000 {
1581				compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
1582				reg = < 0x21ec000 0x4000 >;
1583				interrupts = < 0x00 0x1c 0x04 >;
1584				clocks = < 0x04 0xa0 0x04 0xa1 >;
1585				clock-names = "ipg\0per";
1586				dmas = < 0x16 0x1d 0x04 0x00 0x16 0x1e 0x04 0x00 >;
1587				dma-names = "rx\0tx";
1588				status = "okay";
1589				pinctrl-names = "default";
1590				pinctrl-0 = < 0x3f >;
1591				uart-has-rtscts;
1592			};
1593
1594			serial@21f0000 {
1595				compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
1596				reg = < 0x21f0000 0x4000 >;
1597				interrupts = < 0x00 0x1d 0x04 >;
1598				clocks = < 0x04 0xa0 0x04 0xa1 >;
1599				clock-names = "ipg\0per";
1600				dmas = < 0x16 0x1f 0x04 0x00 0x16 0x20 0x04 0x00 >;
1601				dma-names = "rx\0tx";
1602				status = "disabled";
1603			};
1604
1605			serial@21f4000 {
1606				compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
1607				reg = < 0x21f4000 0x4000 >;
1608				interrupts = < 0x00 0x1e 0x04 >;
1609				clocks = < 0x04 0xa0 0x04 0xa1 >;
1610				clock-names = "ipg\0per";
1611				dmas = < 0x16 0x21 0x04 0x00 0x16 0x22 0x04 0x00 >;
1612				dma-names = "rx\0tx";
1613				status = "disabled";
1614			};
1615		};
1616
1617		ipu@2400000 {
1618			#address-cells = < 0x01 >;
1619			#size-cells = < 0x00 >;
1620			compatible = "fsl,imx6q-ipu";
1621			reg = < 0x2400000 0x400000 >;
1622			interrupts = < 0x00 0x06 0x04 0x00 0x05 0x04 >;
1623			clocks = < 0x04 0x82 0x04 0x83 0x04 0x84 >;
1624			clock-names = "bus\0di0\0di1";
1625			resets = < 0x19 0x02 >;
1626
1627			port@0 {
1628				reg = < 0x00 >;
1629				phandle = < 0x57 >;
1630
1631				endpoint {
1632					remote-endpoint = < 0x40 >;
1633					phandle = < 0x20 >;
1634				};
1635			};
1636
1637			port@1 {
1638				reg = < 0x01 >;
1639				phandle = < 0x58 >;
1640
1641				endpoint {
1642					remote-endpoint = < 0x41 >;
1643					phandle = < 0x38 >;
1644				};
1645			};
1646
1647			port@2 {
1648				#address-cells = < 0x01 >;
1649				#size-cells = < 0x00 >;
1650				reg = < 0x02 >;
1651				phandle = < 0x5b >;
1652
1653				endpoint@0 {
1654					reg = < 0x00 >;
1655				};
1656
1657				endpoint@1 {
1658					reg = < 0x01 >;
1659					remote-endpoint = < 0x42 >;
1660					phandle = < 0x10 >;
1661				};
1662
1663				endpoint@2 {
1664					reg = < 0x02 >;
1665					remote-endpoint = < 0x43 >;
1666					phandle = < 0x3b >;
1667				};
1668
1669				endpoint@3 {
1670					reg = < 0x03 >;
1671					remote-endpoint = < 0x44 >;
1672					phandle = < 0x06 >;
1673				};
1674
1675				endpoint@4 {
1676					reg = < 0x04 >;
1677					remote-endpoint = < 0x45 >;
1678					phandle = < 0x0a >;
1679				};
1680			};
1681
1682			port@3 {
1683				#address-cells = < 0x01 >;
1684				#size-cells = < 0x00 >;
1685				reg = < 0x03 >;
1686				phandle = < 0x5c >;
1687
1688				endpoint@0 {
1689					reg = < 0x00 >;
1690				};
1691
1692				endpoint@1 {
1693					reg = < 0x01 >;
1694					remote-endpoint = < 0x46 >;
1695					phandle = < 0x11 >;
1696				};
1697
1698				endpoint@2 {
1699					reg = < 0x02 >;
1700					remote-endpoint = < 0x47 >;
1701					phandle = < 0x3c >;
1702				};
1703
1704				endpoint@3 {
1705					reg = < 0x03 >;
1706					remote-endpoint = < 0x48 >;
1707					phandle = < 0x07 >;
1708				};
1709
1710				endpoint@4 {
1711					reg = < 0x04 >;
1712					remote-endpoint = < 0x49 >;
1713					phandle = < 0x0b >;
1714				};
1715			};
1716		};
1717
1718		sram@900000 {
1719			compatible = "mmio-sram";
1720			reg = < 0x900000 0x40000 >;
1721			clocks = < 0x04 0x8e >;
1722			phandle = < 0x1a >;
1723		};
1724
1725		sata@2200000 {
1726			compatible = "fsl,imx6q-ahci";
1727			reg = < 0x2200000 0x4000 >;
1728			interrupts = < 0x00 0x27 0x04 >;
1729			clocks = < 0x04 0x9a 0x04 0xbb 0x04 0x69 >;
1730			clock-names = "sata\0sata_ref\0ahb";
1731			status = "okay";
1732		};
1733
1734		gpu@2204000 {
1735			compatible = "vivante,gc";
1736			reg = < 0x2204000 0x4000 >;
1737			interrupts = < 0x00 0x0b 0x04 >;
1738			clocks = < 0x04 0x8f 0x04 0x79 >;
1739			clock-names = "bus\0core";
1740			power-domains = < 0x14 >;
1741		};
1742
1743		ipu@2800000 {
1744			#address-cells = < 0x01 >;
1745			#size-cells = < 0x00 >;
1746			compatible = "fsl,imx6q-ipu";
1747			reg = < 0x2800000 0x400000 >;
1748			interrupts = < 0x00 0x08 0x04 0x00 0x07 0x04 >;
1749			clocks = < 0x04 0x85 0x04 0x86 0x04 0x89 >;
1750			clock-names = "bus\0di0\0di1";
1751			resets = < 0x19 0x04 >;
1752
1753			port@0 {
1754				reg = < 0x00 >;
1755				phandle = < 0x59 >;
1756
1757				endpoint {
1758					remote-endpoint = < 0x4a >;
1759					phandle = < 0x39 >;
1760				};
1761			};
1762
1763			port@1 {
1764				reg = < 0x01 >;
1765				phandle = < 0x5a >;
1766
1767				endpoint {
1768					remote-endpoint = < 0x4b >;
1769					phandle = < 0x22 >;
1770				};
1771			};
1772
1773			port@2 {
1774				#address-cells = < 0x01 >;
1775				#size-cells = < 0x00 >;
1776				reg = < 0x02 >;
1777				phandle = < 0x5d >;
1778
1779				endpoint@0 {
1780					reg = < 0x00 >;
1781				};
1782
1783				endpoint@1 {
1784					reg = < 0x01 >;
1785					remote-endpoint = < 0x4c >;
1786					phandle = < 0x12 >;
1787				};
1788
1789				endpoint@2 {
1790					reg = < 0x02 >;
1791					remote-endpoint = < 0x4d >;
1792					phandle = < 0x3d >;
1793				};
1794
1795				endpoint@3 {
1796					reg = < 0x03 >;
1797					remote-endpoint = < 0x4e >;
1798					phandle = < 0x08 >;
1799				};
1800
1801				endpoint@4 {
1802					reg = < 0x04 >;
1803					remote-endpoint = < 0x4f >;
1804					phandle = < 0x0c >;
1805				};
1806			};
1807
1808			port@3 {
1809				#address-cells = < 0x01 >;
1810				#size-cells = < 0x00 >;
1811				reg = < 0x03 >;
1812				phandle = < 0x5e >;
1813
1814				endpoint@1 {
1815					reg = < 0x01 >;
1816					remote-endpoint = < 0x50 >;
1817					phandle = < 0x13 >;
1818				};
1819
1820				endpoint@2 {
1821					reg = < 0x02 >;
1822					remote-endpoint = < 0x51 >;
1823					phandle = < 0x3e >;
1824				};
1825
1826				endpoint@3 {
1827					reg = < 0x03 >;
1828					remote-endpoint = < 0x52 >;
1829					phandle = < 0x09 >;
1830				};
1831
1832				endpoint@4 {
1833					reg = < 0x04 >;
1834					remote-endpoint = < 0x53 >;
1835					phandle = < 0x0d >;
1836				};
1837			};
1838		};
1839	};
1840
1841	cpus {
1842		#address-cells = < 0x01 >;
1843		#size-cells = < 0x00 >;
1844
1845		cpu@0 {
1846			compatible = "arm,cortex-a9";
1847			device_type = "cpu";
1848			reg = < 0x00 >;
1849			next-level-cache = < 0x54 >;
1850			operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0xee098 >;
1851			fsl,soc-operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x11edd8 >;
1852			clock-latency = < 0xee6c >;
1853			#cooling-cells = < 0x02 >;
1854			clocks = < 0x04 0x68 0x04 0x06 0x04 0x10 0x04 0x11 0x04 0xaa >;
1855			clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys";
1856			arm-supply = < 0x55 >;
1857			pu-supply = < 0x1d >;
1858			soc-supply = < 0x56 >;
1859		};
1860
1861		cpu@1 {
1862			compatible = "arm,cortex-a9";
1863			device_type = "cpu";
1864			reg = < 0x01 >;
1865			next-level-cache = < 0x54 >;
1866			operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0xee098 >;
1867			fsl,soc-operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x11edd8 >;
1868			clock-latency = < 0xee6c >;
1869			clocks = < 0x04 0x68 0x04 0x06 0x04 0x10 0x04 0x11 0x04 0xaa >;
1870			clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys";
1871			arm-supply = < 0x55 >;
1872			pu-supply = < 0x1d >;
1873			soc-supply = < 0x56 >;
1874		};
1875
1876		cpu@2 {
1877			compatible = "arm,cortex-a9";
1878			device_type = "cpu";
1879			reg = < 0x02 >;
1880			next-level-cache = < 0x54 >;
1881			operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0xee098 >;
1882			fsl,soc-operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x11edd8 >;
1883			clock-latency = < 0xee6c >;
1884			clocks = < 0x04 0x68 0x04 0x06 0x04 0x10 0x04 0x11 0x04 0xaa >;
1885			clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys";
1886			arm-supply = < 0x55 >;
1887			pu-supply = < 0x1d >;
1888			soc-supply = < 0x56 >;
1889		};
1890
1891		cpu@3 {
1892			compatible = "arm,cortex-a9";
1893			device_type = "cpu";
1894			reg = < 0x03 >;
1895			next-level-cache = < 0x54 >;
1896			operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0xee098 >;
1897			fsl,soc-operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x11edd8 >;
1898			clock-latency = < 0xee6c >;
1899			clocks = < 0x04 0x68 0x04 0x06 0x04 0x10 0x04 0x11 0x04 0xaa >;
1900			clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys";
1901			arm-supply = < 0x55 >;
1902			pu-supply = < 0x1d >;
1903			soc-supply = < 0x56 >;
1904		};
1905	};
1906
1907	capture-subsystem {
1908		compatible = "fsl,imx-capture-subsystem";
1909		ports = < 0x57 0x58 0x59 0x5a >;
1910	};
1911
1912	display-subsystem {
1913		compatible = "fsl,imx-display-subsystem";
1914		ports = < 0x5b 0x5c 0x5d 0x5e >;
1915	};
1916
1917	sound {
1918		compatible = "fsl,imx6-wandboard-sgtl5000\0fsl,imx-audio-sgtl5000";
1919		model = "imx6-wandboard-sgtl5000";
1920		ssi-controller = < 0x5f >;
1921		audio-codec = < 0x60 >;
1922		audio-routing = "MIC_IN\0Mic Jack\0Mic Jack\0Mic Bias\0Headphone Jack\0HP_OUT";
1923		mux-int-port = < 0x01 >;
1924		mux-ext-port = < 0x03 >;
1925	};
1926
1927	sound-spdif {
1928		compatible = "fsl,imx-audio-spdif";
1929		model = "imx-spdif";
1930		spdif-controller = < 0x61 >;
1931		spdif-out;
1932	};
1933
1934	regulator-2p5v {
1935		compatible = "regulator-fixed";
1936		regulator-name = "2P5V";
1937		regulator-min-microvolt = < 0x2625a0 >;
1938		regulator-max-microvolt = < 0x2625a0 >;
1939		regulator-always-on;
1940		phandle = < 0x33 >;
1941	};
1942
1943	regulator-3p3v {
1944		compatible = "regulator-fixed";
1945		regulator-name = "3P3V";
1946		regulator-min-microvolt = < 0x325aa0 >;
1947		regulator-max-microvolt = < 0x325aa0 >;
1948		regulator-always-on;
1949		phandle = < 0x34 >;
1950	};
1951
1952	regulator-usbotgvbus {
1953		compatible = "regulator-fixed";
1954		regulator-name = "usb_otg_vbus";
1955		regulator-min-microvolt = < 0x4c4b40 >;
1956		regulator-max-microvolt = < 0x4c4b40 >;
1957		pinctrl-names = "default";
1958		pinctrl-0 = < 0x62 >;
1959		gpio = < 0x2b 0x16 0x01 >;
1960		phandle = < 0x26 >;
1961	};
1962
1963	regulator-eth-phy {
1964		compatible = "regulator-fixed";
1965		regulator-name = "ETH_PHY";
1966		regulator-min-microvolt = < 0x325aa0 >;
1967		regulator-max-microvolt = < 0x325aa0 >;
1968		gpio = < 0x63 0x0d 0x01 >;
1969		phandle = < 0x2c >;
1970	};
1971
1972	memory@10000000 {
1973		reg = < 0x10000000 0x80000000 >;
1974	};
1975};
1976