1/*
2 * Copyright Linux Kernel Team
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * This file is derived from an intermediate build stage of the
7 * Linux kernel. The licenses of all input files to this process
8 * are compatible with GPL-2.0-only.
9 */
10
11/dts-v1/;
12
13/ {
14  #address-cells = <0x00000002>;
15  #size-cells = <0x00000002>;
16  compatible = "riscv-virtio";
17  model = "riscv-virtio,qemu";
18  chosen {
19    bootargs = "";
20    stdout-path = <0x2f756172 0x74403130 0x30303030>;
21  };
22  uart@10000000 {
23    interrupts = <0x0000000a>;
24    interrupt-parent = <0x00000002>;
25    clock-frequency = <0x00384000>;
26    reg = <0x00000000 0x10000000 0x00000000 0x00000100>;
27    compatible = "ns16550a";
28  };
29  test@100000 {
30    reg = <0x00000000 0x00100000 0x00000000 0x00001000>;
31    compatible = "sifive,test0";
32  };
33  virtio_mmio@10008000 {
34    interrupts = <0x00000008>;
35    interrupt-parent = <0x00000002>;
36    reg = <0x00000000 0x10008000 0x00000000 0x00001000>;
37    compatible = "virtio,mmio";
38  };
39  virtio_mmio@10007000 {
40    interrupts = <0x00000007>;
41    interrupt-parent = <0x00000002>;
42    reg = <0x00000000 0x10007000 0x00000000 0x00001000>;
43    compatible = "virtio,mmio";
44  };
45  virtio_mmio@10006000 {
46    interrupts = <0x00000006>;
47    interrupt-parent = <0x00000002>;
48    reg = <0x00000000 0x10006000 0x00000000 0x00001000>;
49    compatible = "virtio,mmio";
50  };
51  virtio_mmio@10005000 {
52    interrupts = <0x00000005>;
53    interrupt-parent = <0x00000002>;
54    reg = <0x00000000 0x10005000 0x00000000 0x00001000>;
55    compatible = "virtio,mmio";
56  };
57  virtio_mmio@10004000 {
58    interrupts = <0x00000004>;
59    interrupt-parent = <0x00000002>;
60    reg = <0x00000000 0x10004000 0x00000000 0x00001000>;
61    compatible = "virtio,mmio";
62  };
63  virtio_mmio@10003000 {
64    interrupts = <0x00000003>;
65    interrupt-parent = <0x00000002>;
66    reg = <0x00000000 0x10003000 0x00000000 0x00001000>;
67    compatible = "virtio,mmio";
68  };
69  virtio_mmio@10002000 {
70    interrupts = <0x00000002>;
71    interrupt-parent = <0x00000002>;
72    reg = <0x00000000 0x10002000 0x00000000 0x00001000>;
73    compatible = "virtio,mmio";
74  };
75  virtio_mmio@10001000 {
76    interrupts = <0x00000001>;
77    interrupt-parent = <0x00000002>;
78    reg = <0x00000000 0x10001000 0x00000000 0x00001000>;
79    compatible = "virtio,mmio";
80  };
81  cpus {
82    #address-cells = <0x00000001>;
83    #size-cells = <0x00000000>;
84    timebase-frequency = <0x00989680>;
85    cpu@0 {
86      device_type = "cpu";
87      reg = <0x00000000>;
88      status = "okay";
89      compatible = "riscv";
90      riscv,isa = "rv32imafdcsu";
91      mmu-type = "riscv,sv48";
92      clock-frequency = <0x3b9aca00>;
93      interrupt-controller {
94        #interrupt-cells = <0x00000001>;
95        interrupt-controller;
96        compatible = "riscv,cpu-intc";
97        linux,phandle = <0x00000001>;
98        phandle = <0x00000001>;
99      };
100    };
101  };
102  memory@80000000 {
103    device_type = "memory";
104    reg = <0x00000000 0x80000000 0x00000000 0x7d000000>;
105  };
106  soc {
107    #address-cells = <0x00000002>;
108    #size-cells = <0x00000002>;
109    compatible = "simple-bus";
110    ranges;
111    interrupt-controller@c000000 {
112      linux,phandle = <0x00000002>;
113      phandle = <0x00000002>;
114      riscv,ndev = <0x0000000a>;
115      riscv,max-priority = <0x00000007>;
116      reg-names = "control";
117      reg = <0x00000000 0x0c000000 0x00000000 0x04000000>;
118      interrupts-extended = <0x00000001 0xffffffff 0x00000001 0x00000009>;
119      interrupt-controller;
120      compatible = "riscv,plic0";
121      #interrupt-cells = <0x00000001>;
122    };
123  };
124};
125