1/* SPDX-License-Identifier: BSD-3-Clause */
2
3/*
4 * Copyright (c) 2012-2014, The Regents of the University of California
5 * (Regents).  All Rights Reserved.
6 *
7 *  Redistribution and use in source and binary forms, with or without
8 *  modification, are permitted provided that the following conditions are met:
9 *  1. Redistributions of source code must retain the above copyright
10 *     notice, this list of conditions and the following disclaimer.
11 *  2. Redistributions in binary form must reproduce the above copyright
12 *     notice, this list of conditions and the following disclaimer in the
13 *     documentation and/or other materials provided with the distribution.
14 *  3. Neither the name of the Regents nor the
15 *     names of its contributors may be used to endorse or promote products
16 *     derived from this software without specific prior written permission.
17 *
18 *  IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
19 *  SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
20 *  OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
21 *  BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 *  REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
24 *  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 *  PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
26 *  HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
27 *  MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
28 */
29
30/dts-v1/;
31
32/ {
33	#address-cells = <1>;
34	#size-cells = <1>;
35	compatible = "freechips,rocketchip-unknown-dev";
36	model = "freechips,rocketchip-unknown";
37  	chosen {
38	};
39	L13: cpus {
40		#address-cells = <1>;
41		#size-cells = <0>;
42		L5: cpu@0 {
43			clock-frequency = <0>;
44			compatible = "sifive,rocket0", "riscv";
45			d-cache-block-size = <64>;
46			d-cache-sets = <64>;
47			d-cache-size = <16384>;
48			d-tlb-sets = <1>;
49			d-tlb-size = <32>;
50			device_type = "cpu";
51			i-cache-block-size = <64>;
52			i-cache-sets = <64>;
53			i-cache-size = <16384>;
54			i-tlb-sets = <1>;
55			i-tlb-size = <32>;
56			mmu-type = "riscv,sv39";
57			next-level-cache = <&L6>;
58			reg = <0>;
59			riscv,isa = "rv64imafdc";
60			status = "okay";
61			timebase-frequency = <1000000>;
62			tlb-split;
63			L3: interrupt-controller {
64				#interrupt-cells = <1>;
65				compatible = "riscv,cpu-intc";
66				interrupt-controller;
67			};
68		};
69	};
70	L6: memory@80000000 {
71		device_type = "memory";
72		reg = <0x80000000 0x10000000>;
73	};
74	L12: soc {
75		#address-cells = <1>;
76		#size-cells = <1>;
77		compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
78		ranges;
79		L10: blkdev-controller@10015000 {
80			compatible = "ucbbar,blkdev";
81			interrupt-parent = <&L0>;
82			interrupts = <3>;
83			reg = <0x10015000 0x1000>;
84			reg-names = "control";
85		};
86		L1: clint@2000000 {
87			compatible = "riscv,clint0";
88			interrupts-extended = <&L3 3 &L3 7>;
89			reg = <0x2000000 0x10000>;
90			reg-names = "control";
91		};
92		L2: debug-controller@0 {
93			compatible = "sifive,debug-013", "riscv,debug-013";
94			interrupts-extended = <&L3 65535>;
95			reg = <0x0 0x1000>;
96			reg-names = "control";
97		};
98		L7: error-device@3000 {
99			compatible = "sifive,error0";
100			reg = <0x3000 0x1000>;
101			reg-names = "mem";
102		};
103		L9: external-interrupts {
104			interrupt-parent = <&L0>;
105			interrupts = <1 2>;
106		};
107		L0: interrupt-controller@c000000 {
108			#interrupt-cells = <1>;
109			compatible = "riscv,plic0";
110			interrupt-controller;
111			interrupts-extended = <&L3 11 &L3 9>;
112			reg = <0xc000000 0x4000000>;
113			reg-names = "control";
114			riscv,max-priority = <7>;
115			riscv,ndev = <3>;
116		};
117		L8: rom@10000 {
118			compatible = "sifive,rom0";
119			reg = <0x10000 0x10000>;
120			reg-names = "mem";
121		};
122	};
123	htif {
124		compatible = "ucb,htif0";
125	};
126};
127