1/* 2 * Copyright Linux Kernel Team 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 * 6 * This file is derived from an intermediate build stage of the 7 * Linux kernel. The licenses of all input files to this process 8 * are compatible with GPL-2.0-only. 9 */ 10 11/dts-v1/; 12 13/ { 14 compatible = "ti,omap3-beagle\0ti,omap3"; 15 interrupt-parent = < 0x01 >; 16 #address-cells = < 0x01 >; 17 #size-cells = < 0x01 >; 18 model = "TI OMAP3 BeagleBoard"; 19 20 chosen { 21 }; 22 23 aliases { 24 i2c0 = "/ocp@68000000/i2c@48070000"; 25 i2c1 = "/ocp@68000000/i2c@48072000"; 26 i2c2 = "/ocp@68000000/i2c@48060000"; 27 serial0 = "/ocp@68000000/serial@4806a000"; 28 serial1 = "/ocp@68000000/serial@4806c000"; 29 serial2 = "/ocp@68000000/serial@49020000"; 30 display0 = "/connector0"; 31 display1 = "/connector1"; 32 }; 33 34 cpus { 35 #address-cells = < 0x01 >; 36 #size-cells = < 0x00 >; 37 38 cpu@0 { 39 compatible = "arm,cortex-a8"; 40 device_type = "cpu"; 41 reg = < 0x00 >; 42 clocks = < 0x02 >; 43 clock-names = "cpu"; 44 clock-latency = < 0x493e0 >; 45 operating-points = < 0x1e848 0xee098 0x3d090 0x106738 0x7a120 0x124f80 0x86470 0x1360f0 0x927c0 0x149970 >; 46 cpu0-supply = < 0x03 >; 47 }; 48 }; 49 50 pmu@54000000 { 51 compatible = "arm,cortex-a8-pmu"; 52 reg = < 0x54000000 0x800000 >; 53 interrupts = < 0x03 >; 54 ti,hwmods = "debugss"; 55 }; 56 57 soc { 58 compatible = "ti,omap-infra"; 59 60 mpu { 61 compatible = "ti,omap3-mpu"; 62 ti,hwmods = "mpu"; 63 }; 64 65 iva { 66 compatible = "ti,iva2.2"; 67 ti,hwmods = "iva"; 68 69 dsp { 70 compatible = "ti,omap3-c64"; 71 }; 72 }; 73 }; 74 75 ocp@68000000 { 76 compatible = "ti,omap3-l3-smx\0simple-bus"; 77 reg = < 0x68000000 0x10000 >; 78 interrupts = < 0x09 0x0a >; 79 #address-cells = < 0x01 >; 80 #size-cells = < 0x01 >; 81 ranges; 82 ti,hwmods = "l3_main"; 83 84 l4@48000000 { 85 compatible = "ti,omap3-l4-core\0simple-bus"; 86 #address-cells = < 0x01 >; 87 #size-cells = < 0x01 >; 88 ranges = < 0x00 0x48000000 0x1000000 >; 89 90 scm@2000 { 91 compatible = "ti,omap3-scm\0simple-bus"; 92 reg = < 0x2000 0x2000 >; 93 #address-cells = < 0x01 >; 94 #size-cells = < 0x01 >; 95 ranges = < 0x00 0x2000 0x2000 >; 96 97 pinmux@30 { 98 compatible = "ti,omap3-padconf\0pinctrl-single"; 99 reg = < 0x30 0x238 >; 100 #address-cells = < 0x01 >; 101 #size-cells = < 0x00 >; 102 #pinctrl-cells = < 0x01 >; 103 #interrupt-cells = < 0x01 >; 104 interrupt-controller; 105 pinctrl-single,register-width = < 0x10 >; 106 pinctrl-single,function-mask = < 0xff1f >; 107 pinctrl-names = "default"; 108 pinctrl-0 = < 0x04 >; 109 phandle = < 0xe5 >; 110 111 pinmux_hsusb2_pins { 112 pinctrl-single,pins = < 0x1a4 0x10b 0x1a6 0x10b 0x1a8 0x10b 0x1aa 0x10b 0x1ac 0x10b 0x1ae 0x10b >; 113 phandle = < 0x04 >; 114 }; 115 116 pinmux_uart3_pins { 117 pinctrl-single,pins = < 0x16e 0x4100 0x170 0x00 >; 118 phandle = < 0xe6 >; 119 }; 120 121 pinmux_tfp410_pins { 122 pinctrl-single,pins = < 0x196 0x04 >; 123 phandle = < 0x109 >; 124 }; 125 126 pinmux_dss_dpi_pins { 127 pinctrl-single,pins = < 0xa4 0x00 0xa6 0x00 0xa8 0x00 0xaa 0x00 0xac 0x00 0xae 0x00 0xb0 0x00 0xb2 0x00 0xb4 0x00 0xb6 0x00 0xb8 0x00 0xba 0x00 0xbc 0x00 0xbe 0x00 0xc0 0x00 0xc2 0x00 0xc4 0x00 0xc6 0x00 0xc8 0x00 0xca 0x00 0xcc 0x00 0xce 0x00 0xd0 0x00 0xd2 0x00 0xd4 0x00 0xd6 0x00 0xd8 0x00 0xda 0x00 >; 128 phandle = < 0xf8 >; 129 }; 130 131 pinmux_twl4030_pins { 132 pinctrl-single,pins = < 0x1b0 0x4118 >; 133 phandle = < 0xe7 >; 134 }; 135 }; 136 137 scm_conf@270 { 138 compatible = "syscon\0simple-bus"; 139 reg = < 0x270 0x330 >; 140 #address-cells = < 0x01 >; 141 #size-cells = < 0x01 >; 142 ranges = < 0x00 0x270 0x330 >; 143 phandle = < 0x05 >; 144 145 pbias_regulator@2b0 { 146 compatible = "ti,pbias-omap3\0ti,pbias-omap"; 147 reg = < 0x2b0 0x04 >; 148 syscon = < 0x05 >; 149 150 pbias_mmc_omap2430 { 151 regulator-name = "pbias_mmc_omap2430"; 152 regulator-min-microvolt = < 0x1b7740 >; 153 regulator-max-microvolt = < 0x2dc6c0 >; 154 phandle = < 0xed >; 155 }; 156 }; 157 158 clocks { 159 #address-cells = < 0x01 >; 160 #size-cells = < 0x00 >; 161 162 mcbsp5_mux_fck@68 { 163 #clock-cells = < 0x00 >; 164 compatible = "ti,composite-mux-clock"; 165 clocks = < 0x06 0x07 >; 166 ti,bit-shift = < 0x04 >; 167 reg = < 0x68 >; 168 phandle = < 0x09 >; 169 }; 170 171 mcbsp5_fck { 172 #clock-cells = < 0x00 >; 173 compatible = "ti,composite-clock"; 174 clocks = < 0x08 0x09 >; 175 phandle = < 0xf4 >; 176 }; 177 178 mcbsp1_mux_fck@4 { 179 #clock-cells = < 0x00 >; 180 compatible = "ti,composite-mux-clock"; 181 clocks = < 0x06 0x07 >; 182 ti,bit-shift = < 0x02 >; 183 reg = < 0x04 >; 184 phandle = < 0x0b >; 185 }; 186 187 mcbsp1_fck { 188 #clock-cells = < 0x00 >; 189 compatible = "ti,composite-clock"; 190 clocks = < 0x0a 0x0b >; 191 phandle = < 0xf0 >; 192 }; 193 194 mcbsp2_mux_fck@4 { 195 #clock-cells = < 0x00 >; 196 compatible = "ti,composite-mux-clock"; 197 clocks = < 0x0c 0x07 >; 198 ti,bit-shift = < 0x06 >; 199 reg = < 0x04 >; 200 phandle = < 0x0e >; 201 }; 202 203 mcbsp2_fck { 204 #clock-cells = < 0x00 >; 205 compatible = "ti,composite-clock"; 206 clocks = < 0x0d 0x0e >; 207 phandle = < 0xf1 >; 208 }; 209 210 mcbsp3_mux_fck@68 { 211 #clock-cells = < 0x00 >; 212 compatible = "ti,composite-mux-clock"; 213 clocks = < 0x0c 0x07 >; 214 reg = < 0x68 >; 215 phandle = < 0x10 >; 216 }; 217 218 mcbsp3_fck { 219 #clock-cells = < 0x00 >; 220 compatible = "ti,composite-clock"; 221 clocks = < 0x0f 0x10 >; 222 phandle = < 0xf2 >; 223 }; 224 225 mcbsp4_mux_fck@68 { 226 #clock-cells = < 0x00 >; 227 compatible = "ti,composite-mux-clock"; 228 clocks = < 0x0c 0x07 >; 229 ti,bit-shift = < 0x02 >; 230 reg = < 0x68 >; 231 phandle = < 0x12 >; 232 }; 233 234 mcbsp4_fck { 235 #clock-cells = < 0x00 >; 236 compatible = "ti,composite-clock"; 237 clocks = < 0x11 0x12 >; 238 phandle = < 0xf3 >; 239 }; 240 }; 241 }; 242 243 clockdomains { 244 }; 245 246 pinmux@a00 { 247 compatible = "ti,omap3-padconf\0pinctrl-single"; 248 reg = < 0xa00 0x5c >; 249 #address-cells = < 0x01 >; 250 #size-cells = < 0x00 >; 251 #pinctrl-cells = < 0x01 >; 252 #interrupt-cells = < 0x01 >; 253 interrupt-controller; 254 pinctrl-single,register-width = < 0x10 >; 255 pinctrl-single,function-mask = < 0xff1f >; 256 257 pinmux_gpio1_pins { 258 pinctrl-single,pins = < 0x14 0x4104 >; 259 phandle = < 0xe4 >; 260 }; 261 262 pinmux_twl4030_vpins { 263 pinctrl-single,pins = < 0x00 0x100 0x02 0x100 0x06 0x00 0x18 0x00 >; 264 phandle = < 0xe8 >; 265 }; 266 }; 267 }; 268 }; 269 270 aes@480c5000 { 271 compatible = "ti,omap3-aes"; 272 ti,hwmods = "aes"; 273 reg = < 0x480c5000 0x50 >; 274 interrupts = < 0x00 >; 275 dmas = < 0x13 0x41 0x13 0x42 >; 276 dma-names = "tx\0rx"; 277 }; 278 279 prm@48306000 { 280 compatible = "ti,omap3-prm"; 281 reg = < 0x48306000 0x4000 >; 282 interrupts = < 0x0b >; 283 284 clocks { 285 #address-cells = < 0x01 >; 286 #size-cells = < 0x00 >; 287 288 virt_16_8m_ck { 289 #clock-cells = < 0x00 >; 290 compatible = "fixed-clock"; 291 clock-frequency = < 0x1005900 >; 292 phandle = < 0x19 >; 293 }; 294 295 osc_sys_ck@d40 { 296 #clock-cells = < 0x00 >; 297 compatible = "ti,mux-clock"; 298 clocks = < 0x14 0x15 0x16 0x17 0x18 0x19 >; 299 reg = < 0xd40 >; 300 phandle = < 0x1a >; 301 }; 302 303 sys_ck@1270 { 304 #clock-cells = < 0x00 >; 305 compatible = "ti,divider-clock"; 306 clocks = < 0x1a >; 307 ti,bit-shift = < 0x06 >; 308 ti,max-div = < 0x03 >; 309 reg = < 0x1270 >; 310 ti,index-starts-at-one; 311 phandle = < 0x1f >; 312 }; 313 314 sys_clkout1@d70 { 315 #clock-cells = < 0x00 >; 316 compatible = "ti,gate-clock"; 317 clocks = < 0x1a >; 318 reg = < 0xd70 >; 319 ti,bit-shift = < 0x07 >; 320 }; 321 322 dpll3_x2_ck { 323 #clock-cells = < 0x00 >; 324 compatible = "fixed-factor-clock"; 325 clocks = < 0x1b >; 326 clock-mult = < 0x02 >; 327 clock-div = < 0x01 >; 328 }; 329 330 dpll3_m2x2_ck { 331 #clock-cells = < 0x00 >; 332 compatible = "fixed-factor-clock"; 333 clocks = < 0x1c >; 334 clock-mult = < 0x02 >; 335 clock-div = < 0x01 >; 336 phandle = < 0x1e >; 337 }; 338 339 dpll4_x2_ck { 340 #clock-cells = < 0x00 >; 341 compatible = "fixed-factor-clock"; 342 clocks = < 0x1d >; 343 clock-mult = < 0x02 >; 344 clock-div = < 0x01 >; 345 }; 346 347 corex2_fck { 348 #clock-cells = < 0x00 >; 349 compatible = "fixed-factor-clock"; 350 clocks = < 0x1e >; 351 clock-mult = < 0x01 >; 352 clock-div = < 0x01 >; 353 phandle = < 0x20 >; 354 }; 355 356 wkup_l4_ick { 357 #clock-cells = < 0x00 >; 358 compatible = "fixed-factor-clock"; 359 clocks = < 0x1f >; 360 clock-mult = < 0x01 >; 361 clock-div = < 0x01 >; 362 phandle = < 0x4f >; 363 }; 364 365 corex2_d3_fck { 366 #clock-cells = < 0x00 >; 367 compatible = "fixed-factor-clock"; 368 clocks = < 0x20 >; 369 clock-mult = < 0x01 >; 370 clock-div = < 0x03 >; 371 phandle = < 0x86 >; 372 }; 373 374 corex2_d5_fck { 375 #clock-cells = < 0x00 >; 376 compatible = "fixed-factor-clock"; 377 clocks = < 0x20 >; 378 clock-mult = < 0x01 >; 379 clock-div = < 0x05 >; 380 phandle = < 0x87 >; 381 }; 382 }; 383 384 clockdomains { 385 }; 386 }; 387 388 cm@48004000 { 389 compatible = "ti,omap3-cm"; 390 reg = < 0x48004000 0x4000 >; 391 392 clocks { 393 #address-cells = < 0x01 >; 394 #size-cells = < 0x00 >; 395 396 dummy_apb_pclk { 397 #clock-cells = < 0x00 >; 398 compatible = "fixed-clock"; 399 clock-frequency = < 0x00 >; 400 }; 401 402 omap_32k_fck { 403 #clock-cells = < 0x00 >; 404 compatible = "fixed-clock"; 405 clock-frequency = < 0x8000 >; 406 phandle = < 0x41 >; 407 }; 408 409 virt_12m_ck { 410 #clock-cells = < 0x00 >; 411 compatible = "fixed-clock"; 412 clock-frequency = < 0xb71b00 >; 413 phandle = < 0x14 >; 414 }; 415 416 virt_13m_ck { 417 #clock-cells = < 0x00 >; 418 compatible = "fixed-clock"; 419 clock-frequency = < 0xc65d40 >; 420 phandle = < 0x15 >; 421 }; 422 423 virt_19200000_ck { 424 #clock-cells = < 0x00 >; 425 compatible = "fixed-clock"; 426 clock-frequency = < 0x124f800 >; 427 phandle = < 0x16 >; 428 }; 429 430 virt_26000000_ck { 431 #clock-cells = < 0x00 >; 432 compatible = "fixed-clock"; 433 clock-frequency = < 0x18cba80 >; 434 phandle = < 0x17 >; 435 }; 436 437 virt_38_4m_ck { 438 #clock-cells = < 0x00 >; 439 compatible = "fixed-clock"; 440 clock-frequency = < 0x249f000 >; 441 phandle = < 0x18 >; 442 }; 443 444 dpll4_ck@d00 { 445 #clock-cells = < 0x00 >; 446 compatible = "ti,omap3-dpll-per-clock"; 447 clocks = < 0x1f 0x1f >; 448 reg = < 0xd00 0xd20 0xd44 0xd30 >; 449 phandle = < 0x1d >; 450 }; 451 452 dpll4_m2_ck@d48 { 453 #clock-cells = < 0x00 >; 454 compatible = "ti,divider-clock"; 455 clocks = < 0x1d >; 456 ti,max-div = < 0x3f >; 457 reg = < 0xd48 >; 458 ti,index-starts-at-one; 459 phandle = < 0x21 >; 460 }; 461 462 dpll4_m2x2_mul_ck { 463 #clock-cells = < 0x00 >; 464 compatible = "fixed-factor-clock"; 465 clocks = < 0x21 >; 466 clock-mult = < 0x02 >; 467 clock-div = < 0x01 >; 468 phandle = < 0x22 >; 469 }; 470 471 dpll4_m2x2_ck@d00 { 472 #clock-cells = < 0x00 >; 473 compatible = "ti,gate-clock"; 474 clocks = < 0x22 >; 475 ti,bit-shift = < 0x1b >; 476 reg = < 0xd00 >; 477 ti,set-bit-to-disable; 478 phandle = < 0x23 >; 479 }; 480 481 omap_96m_alwon_fck { 482 #clock-cells = < 0x00 >; 483 compatible = "fixed-factor-clock"; 484 clocks = < 0x23 >; 485 clock-mult = < 0x01 >; 486 clock-div = < 0x01 >; 487 phandle = < 0x2a >; 488 }; 489 490 dpll3_ck@d00 { 491 #clock-cells = < 0x00 >; 492 compatible = "ti,omap3-dpll-core-clock"; 493 clocks = < 0x1f 0x1f >; 494 reg = < 0xd00 0xd20 0xd40 0xd30 >; 495 phandle = < 0x1b >; 496 }; 497 498 dpll3_m3_ck@1140 { 499 #clock-cells = < 0x00 >; 500 compatible = "ti,divider-clock"; 501 clocks = < 0x1b >; 502 ti,bit-shift = < 0x10 >; 503 ti,max-div = < 0x1f >; 504 reg = < 0x1140 >; 505 ti,index-starts-at-one; 506 phandle = < 0x24 >; 507 }; 508 509 dpll3_m3x2_mul_ck { 510 #clock-cells = < 0x00 >; 511 compatible = "fixed-factor-clock"; 512 clocks = < 0x24 >; 513 clock-mult = < 0x02 >; 514 clock-div = < 0x01 >; 515 phandle = < 0x25 >; 516 }; 517 518 dpll3_m3x2_ck@d00 { 519 #clock-cells = < 0x00 >; 520 compatible = "ti,gate-clock"; 521 clocks = < 0x25 >; 522 ti,bit-shift = < 0x0c >; 523 reg = < 0xd00 >; 524 ti,set-bit-to-disable; 525 phandle = < 0x26 >; 526 }; 527 528 emu_core_alwon_ck { 529 #clock-cells = < 0x00 >; 530 compatible = "fixed-factor-clock"; 531 clocks = < 0x26 >; 532 clock-mult = < 0x01 >; 533 clock-div = < 0x01 >; 534 phandle = < 0x63 >; 535 }; 536 537 sys_altclk { 538 #clock-cells = < 0x00 >; 539 compatible = "fixed-clock"; 540 clock-frequency = < 0x00 >; 541 phandle = < 0x2f >; 542 }; 543 544 mcbsp_clks { 545 #clock-cells = < 0x00 >; 546 compatible = "fixed-clock"; 547 clock-frequency = < 0x00 >; 548 phandle = < 0x07 >; 549 }; 550 551 dpll3_m2_ck@d40 { 552 #clock-cells = < 0x00 >; 553 compatible = "ti,divider-clock"; 554 clocks = < 0x1b >; 555 ti,bit-shift = < 0x1b >; 556 ti,max-div = < 0x1f >; 557 reg = < 0xd40 >; 558 ti,index-starts-at-one; 559 phandle = < 0x1c >; 560 }; 561 562 core_ck { 563 #clock-cells = < 0x00 >; 564 compatible = "fixed-factor-clock"; 565 clocks = < 0x1c >; 566 clock-mult = < 0x01 >; 567 clock-div = < 0x01 >; 568 phandle = < 0x27 >; 569 }; 570 571 dpll1_fck@940 { 572 #clock-cells = < 0x00 >; 573 compatible = "ti,divider-clock"; 574 clocks = < 0x27 >; 575 ti,bit-shift = < 0x13 >; 576 ti,max-div = < 0x07 >; 577 reg = < 0x940 >; 578 ti,index-starts-at-one; 579 phandle = < 0x28 >; 580 }; 581 582 dpll1_ck@904 { 583 #clock-cells = < 0x00 >; 584 compatible = "ti,omap3-dpll-clock"; 585 clocks = < 0x1f 0x28 >; 586 reg = < 0x904 0x924 0x940 0x934 >; 587 phandle = < 0x02 >; 588 }; 589 590 dpll1_x2_ck { 591 #clock-cells = < 0x00 >; 592 compatible = "fixed-factor-clock"; 593 clocks = < 0x02 >; 594 clock-mult = < 0x02 >; 595 clock-div = < 0x01 >; 596 phandle = < 0x29 >; 597 }; 598 599 dpll1_x2m2_ck@944 { 600 #clock-cells = < 0x00 >; 601 compatible = "ti,divider-clock"; 602 clocks = < 0x29 >; 603 ti,max-div = < 0x1f >; 604 reg = < 0x944 >; 605 ti,index-starts-at-one; 606 phandle = < 0x3d >; 607 }; 608 609 cm_96m_fck { 610 #clock-cells = < 0x00 >; 611 compatible = "fixed-factor-clock"; 612 clocks = < 0x2a >; 613 clock-mult = < 0x01 >; 614 clock-div = < 0x01 >; 615 phandle = < 0x2b >; 616 }; 617 618 omap_96m_fck@d40 { 619 #clock-cells = < 0x00 >; 620 compatible = "ti,mux-clock"; 621 clocks = < 0x2b 0x1f >; 622 ti,bit-shift = < 0x06 >; 623 reg = < 0xd40 >; 624 phandle = < 0x46 >; 625 }; 626 627 dpll4_m3_ck@e40 { 628 #clock-cells = < 0x00 >; 629 compatible = "ti,divider-clock"; 630 clocks = < 0x1d >; 631 ti,bit-shift = < 0x08 >; 632 ti,max-div = < 0x20 >; 633 reg = < 0xe40 >; 634 ti,index-starts-at-one; 635 phandle = < 0x2c >; 636 }; 637 638 dpll4_m3x2_mul_ck { 639 #clock-cells = < 0x00 >; 640 compatible = "fixed-factor-clock"; 641 clocks = < 0x2c >; 642 clock-mult = < 0x02 >; 643 clock-div = < 0x01 >; 644 phandle = < 0x2d >; 645 }; 646 647 dpll4_m3x2_ck@d00 { 648 #clock-cells = < 0x00 >; 649 compatible = "ti,gate-clock"; 650 clocks = < 0x2d >; 651 ti,bit-shift = < 0x1c >; 652 reg = < 0xd00 >; 653 ti,set-bit-to-disable; 654 phandle = < 0x2e >; 655 }; 656 657 omap_54m_fck@d40 { 658 #clock-cells = < 0x00 >; 659 compatible = "ti,mux-clock"; 660 clocks = < 0x2e 0x2f >; 661 ti,bit-shift = < 0x05 >; 662 reg = < 0xd40 >; 663 phandle = < 0x39 >; 664 }; 665 666 cm_96m_d2_fck { 667 #clock-cells = < 0x00 >; 668 compatible = "fixed-factor-clock"; 669 clocks = < 0x2b >; 670 clock-mult = < 0x01 >; 671 clock-div = < 0x02 >; 672 phandle = < 0x30 >; 673 }; 674 675 omap_48m_fck@d40 { 676 #clock-cells = < 0x00 >; 677 compatible = "ti,mux-clock"; 678 clocks = < 0x30 0x2f >; 679 ti,bit-shift = < 0x03 >; 680 reg = < 0xd40 >; 681 phandle = < 0x31 >; 682 }; 683 684 omap_12m_fck { 685 #clock-cells = < 0x00 >; 686 compatible = "fixed-factor-clock"; 687 clocks = < 0x31 >; 688 clock-mult = < 0x01 >; 689 clock-div = < 0x04 >; 690 phandle = < 0x48 >; 691 }; 692 693 dpll4_m4_ck@e40 { 694 #clock-cells = < 0x00 >; 695 compatible = "ti,divider-clock"; 696 clocks = < 0x1d >; 697 ti,max-div = < 0x20 >; 698 reg = < 0xe40 >; 699 ti,index-starts-at-one; 700 phandle = < 0x32 >; 701 }; 702 703 dpll4_m4x2_mul_ck { 704 #clock-cells = < 0x00 >; 705 compatible = "ti,fixed-factor-clock"; 706 clocks = < 0x32 >; 707 ti,clock-mult = < 0x02 >; 708 ti,clock-div = < 0x01 >; 709 ti,set-rate-parent; 710 phandle = < 0x33 >; 711 }; 712 713 dpll4_m4x2_ck@d00 { 714 #clock-cells = < 0x00 >; 715 compatible = "ti,gate-clock"; 716 clocks = < 0x33 >; 717 ti,bit-shift = < 0x1d >; 718 reg = < 0xd00 >; 719 ti,set-bit-to-disable; 720 ti,set-rate-parent; 721 phandle = < 0x8a >; 722 }; 723 724 dpll4_m5_ck@f40 { 725 #clock-cells = < 0x00 >; 726 compatible = "ti,divider-clock"; 727 clocks = < 0x1d >; 728 ti,max-div = < 0x3f >; 729 reg = < 0xf40 >; 730 ti,index-starts-at-one; 731 phandle = < 0x34 >; 732 }; 733 734 dpll4_m5x2_mul_ck { 735 #clock-cells = < 0x00 >; 736 compatible = "ti,fixed-factor-clock"; 737 clocks = < 0x34 >; 738 ti,clock-mult = < 0x02 >; 739 ti,clock-div = < 0x01 >; 740 ti,set-rate-parent; 741 phandle = < 0x35 >; 742 }; 743 744 dpll4_m5x2_ck@d00 { 745 #clock-cells = < 0x00 >; 746 compatible = "ti,gate-clock"; 747 clocks = < 0x35 >; 748 ti,bit-shift = < 0x1e >; 749 reg = < 0xd00 >; 750 ti,set-bit-to-disable; 751 ti,set-rate-parent; 752 phandle = < 0x6b >; 753 }; 754 755 dpll4_m6_ck@1140 { 756 #clock-cells = < 0x00 >; 757 compatible = "ti,divider-clock"; 758 clocks = < 0x1d >; 759 ti,bit-shift = < 0x18 >; 760 ti,max-div = < 0x3f >; 761 reg = < 0x1140 >; 762 ti,index-starts-at-one; 763 phandle = < 0x36 >; 764 }; 765 766 dpll4_m6x2_mul_ck { 767 #clock-cells = < 0x00 >; 768 compatible = "fixed-factor-clock"; 769 clocks = < 0x36 >; 770 clock-mult = < 0x02 >; 771 clock-div = < 0x01 >; 772 phandle = < 0x37 >; 773 }; 774 775 dpll4_m6x2_ck@d00 { 776 #clock-cells = < 0x00 >; 777 compatible = "ti,gate-clock"; 778 clocks = < 0x37 >; 779 ti,bit-shift = < 0x1f >; 780 reg = < 0xd00 >; 781 ti,set-bit-to-disable; 782 phandle = < 0x38 >; 783 }; 784 785 emu_per_alwon_ck { 786 #clock-cells = < 0x00 >; 787 compatible = "fixed-factor-clock"; 788 clocks = < 0x38 >; 789 clock-mult = < 0x01 >; 790 clock-div = < 0x01 >; 791 phandle = < 0x64 >; 792 }; 793 794 clkout2_src_gate_ck@d70 { 795 #clock-cells = < 0x00 >; 796 compatible = "ti,composite-no-wait-gate-clock"; 797 clocks = < 0x27 >; 798 ti,bit-shift = < 0x07 >; 799 reg = < 0xd70 >; 800 phandle = < 0x3a >; 801 }; 802 803 clkout2_src_mux_ck@d70 { 804 #clock-cells = < 0x00 >; 805 compatible = "ti,composite-mux-clock"; 806 clocks = < 0x27 0x1f 0x2b 0x39 >; 807 reg = < 0xd70 >; 808 phandle = < 0x3b >; 809 }; 810 811 clkout2_src_ck { 812 #clock-cells = < 0x00 >; 813 compatible = "ti,composite-clock"; 814 clocks = < 0x3a 0x3b >; 815 phandle = < 0x3c >; 816 }; 817 818 sys_clkout2@d70 { 819 #clock-cells = < 0x00 >; 820 compatible = "ti,divider-clock"; 821 clocks = < 0x3c >; 822 ti,bit-shift = < 0x03 >; 823 ti,max-div = < 0x40 >; 824 reg = < 0xd70 >; 825 ti,index-power-of-two; 826 }; 827 828 mpu_ck { 829 #clock-cells = < 0x00 >; 830 compatible = "fixed-factor-clock"; 831 clocks = < 0x3d >; 832 clock-mult = < 0x01 >; 833 clock-div = < 0x01 >; 834 phandle = < 0x3e >; 835 }; 836 837 arm_fck@924 { 838 #clock-cells = < 0x00 >; 839 compatible = "ti,divider-clock"; 840 clocks = < 0x3e >; 841 reg = < 0x924 >; 842 ti,max-div = < 0x02 >; 843 }; 844 845 emu_mpu_alwon_ck { 846 #clock-cells = < 0x00 >; 847 compatible = "fixed-factor-clock"; 848 clocks = < 0x3e >; 849 clock-mult = < 0x01 >; 850 clock-div = < 0x01 >; 851 phandle = < 0x65 >; 852 }; 853 854 l3_ick@a40 { 855 #clock-cells = < 0x00 >; 856 compatible = "ti,divider-clock"; 857 clocks = < 0x27 >; 858 ti,max-div = < 0x03 >; 859 reg = < 0xa40 >; 860 ti,index-starts-at-one; 861 phandle = < 0x3f >; 862 }; 863 864 l4_ick@a40 { 865 #clock-cells = < 0x00 >; 866 compatible = "ti,divider-clock"; 867 clocks = < 0x3f >; 868 ti,bit-shift = < 0x02 >; 869 ti,max-div = < 0x03 >; 870 reg = < 0xa40 >; 871 ti,index-starts-at-one; 872 phandle = < 0x40 >; 873 }; 874 875 rm_ick@c40 { 876 #clock-cells = < 0x00 >; 877 compatible = "ti,divider-clock"; 878 clocks = < 0x40 >; 879 ti,bit-shift = < 0x01 >; 880 ti,max-div = < 0x03 >; 881 reg = < 0xc40 >; 882 ti,index-starts-at-one; 883 }; 884 885 gpt10_gate_fck@a00 { 886 #clock-cells = < 0x00 >; 887 compatible = "ti,composite-gate-clock"; 888 clocks = < 0x1f >; 889 ti,bit-shift = < 0x0b >; 890 reg = < 0xa00 >; 891 phandle = < 0x42 >; 892 }; 893 894 gpt10_mux_fck@a40 { 895 #clock-cells = < 0x00 >; 896 compatible = "ti,composite-mux-clock"; 897 clocks = < 0x41 0x1f >; 898 ti,bit-shift = < 0x06 >; 899 reg = < 0xa40 >; 900 phandle = < 0x43 >; 901 }; 902 903 gpt10_fck { 904 #clock-cells = < 0x00 >; 905 compatible = "ti,composite-clock"; 906 clocks = < 0x42 0x43 >; 907 }; 908 909 gpt11_gate_fck@a00 { 910 #clock-cells = < 0x00 >; 911 compatible = "ti,composite-gate-clock"; 912 clocks = < 0x1f >; 913 ti,bit-shift = < 0x0c >; 914 reg = < 0xa00 >; 915 phandle = < 0x44 >; 916 }; 917 918 gpt11_mux_fck@a40 { 919 #clock-cells = < 0x00 >; 920 compatible = "ti,composite-mux-clock"; 921 clocks = < 0x41 0x1f >; 922 ti,bit-shift = < 0x07 >; 923 reg = < 0xa40 >; 924 phandle = < 0x45 >; 925 }; 926 927 gpt11_fck { 928 #clock-cells = < 0x00 >; 929 compatible = "ti,composite-clock"; 930 clocks = < 0x44 0x45 >; 931 }; 932 933 core_96m_fck { 934 #clock-cells = < 0x00 >; 935 compatible = "fixed-factor-clock"; 936 clocks = < 0x46 >; 937 clock-mult = < 0x01 >; 938 clock-div = < 0x01 >; 939 phandle = < 0x06 >; 940 }; 941 942 mmchs2_fck@a00 { 943 #clock-cells = < 0x00 >; 944 compatible = "ti,wait-gate-clock"; 945 clocks = < 0x06 >; 946 reg = < 0xa00 >; 947 ti,bit-shift = < 0x19 >; 948 phandle = < 0xb5 >; 949 }; 950 951 mmchs1_fck@a00 { 952 #clock-cells = < 0x00 >; 953 compatible = "ti,wait-gate-clock"; 954 clocks = < 0x06 >; 955 reg = < 0xa00 >; 956 ti,bit-shift = < 0x18 >; 957 phandle = < 0xb6 >; 958 }; 959 960 i2c3_fck@a00 { 961 #clock-cells = < 0x00 >; 962 compatible = "ti,wait-gate-clock"; 963 clocks = < 0x06 >; 964 reg = < 0xa00 >; 965 ti,bit-shift = < 0x11 >; 966 phandle = < 0xb7 >; 967 }; 968 969 i2c2_fck@a00 { 970 #clock-cells = < 0x00 >; 971 compatible = "ti,wait-gate-clock"; 972 clocks = < 0x06 >; 973 reg = < 0xa00 >; 974 ti,bit-shift = < 0x10 >; 975 phandle = < 0xb8 >; 976 }; 977 978 i2c1_fck@a00 { 979 #clock-cells = < 0x00 >; 980 compatible = "ti,wait-gate-clock"; 981 clocks = < 0x06 >; 982 reg = < 0xa00 >; 983 ti,bit-shift = < 0x0f >; 984 phandle = < 0xb9 >; 985 }; 986 987 mcbsp5_gate_fck@a00 { 988 #clock-cells = < 0x00 >; 989 compatible = "ti,composite-gate-clock"; 990 clocks = < 0x07 >; 991 ti,bit-shift = < 0x0a >; 992 reg = < 0xa00 >; 993 phandle = < 0x08 >; 994 }; 995 996 mcbsp1_gate_fck@a00 { 997 #clock-cells = < 0x00 >; 998 compatible = "ti,composite-gate-clock"; 999 clocks = < 0x07 >; 1000 ti,bit-shift = < 0x09 >; 1001 reg = < 0xa00 >; 1002 phandle = < 0x0a >; 1003 }; 1004 1005 core_48m_fck { 1006 #clock-cells = < 0x00 >; 1007 compatible = "fixed-factor-clock"; 1008 clocks = < 0x31 >; 1009 clock-mult = < 0x01 >; 1010 clock-div = < 0x01 >; 1011 phandle = < 0x47 >; 1012 }; 1013 1014 mcspi4_fck@a00 { 1015 #clock-cells = < 0x00 >; 1016 compatible = "ti,wait-gate-clock"; 1017 clocks = < 0x47 >; 1018 reg = < 0xa00 >; 1019 ti,bit-shift = < 0x15 >; 1020 phandle = < 0xba >; 1021 }; 1022 1023 mcspi3_fck@a00 { 1024 #clock-cells = < 0x00 >; 1025 compatible = "ti,wait-gate-clock"; 1026 clocks = < 0x47 >; 1027 reg = < 0xa00 >; 1028 ti,bit-shift = < 0x14 >; 1029 phandle = < 0xbb >; 1030 }; 1031 1032 mcspi2_fck@a00 { 1033 #clock-cells = < 0x00 >; 1034 compatible = "ti,wait-gate-clock"; 1035 clocks = < 0x47 >; 1036 reg = < 0xa00 >; 1037 ti,bit-shift = < 0x13 >; 1038 phandle = < 0xbc >; 1039 }; 1040 1041 mcspi1_fck@a00 { 1042 #clock-cells = < 0x00 >; 1043 compatible = "ti,wait-gate-clock"; 1044 clocks = < 0x47 >; 1045 reg = < 0xa00 >; 1046 ti,bit-shift = < 0x12 >; 1047 phandle = < 0xbd >; 1048 }; 1049 1050 uart2_fck@a00 { 1051 #clock-cells = < 0x00 >; 1052 compatible = "ti,wait-gate-clock"; 1053 clocks = < 0x47 >; 1054 reg = < 0xa00 >; 1055 ti,bit-shift = < 0x0e >; 1056 phandle = < 0xbe >; 1057 }; 1058 1059 uart1_fck@a00 { 1060 #clock-cells = < 0x00 >; 1061 compatible = "ti,wait-gate-clock"; 1062 clocks = < 0x47 >; 1063 reg = < 0xa00 >; 1064 ti,bit-shift = < 0x0d >; 1065 phandle = < 0xbf >; 1066 }; 1067 1068 core_12m_fck { 1069 #clock-cells = < 0x00 >; 1070 compatible = "fixed-factor-clock"; 1071 clocks = < 0x48 >; 1072 clock-mult = < 0x01 >; 1073 clock-div = < 0x01 >; 1074 phandle = < 0x49 >; 1075 }; 1076 1077 hdq_fck@a00 { 1078 #clock-cells = < 0x00 >; 1079 compatible = "ti,wait-gate-clock"; 1080 clocks = < 0x49 >; 1081 reg = < 0xa00 >; 1082 ti,bit-shift = < 0x16 >; 1083 phandle = < 0xc0 >; 1084 }; 1085 1086 core_l3_ick { 1087 #clock-cells = < 0x00 >; 1088 compatible = "fixed-factor-clock"; 1089 clocks = < 0x3f >; 1090 clock-mult = < 0x01 >; 1091 clock-div = < 0x01 >; 1092 phandle = < 0x4a >; 1093 }; 1094 1095 sdrc_ick@a10 { 1096 #clock-cells = < 0x00 >; 1097 compatible = "ti,wait-gate-clock"; 1098 clocks = < 0x4a >; 1099 reg = < 0xa10 >; 1100 ti,bit-shift = < 0x01 >; 1101 phandle = < 0x8b >; 1102 }; 1103 1104 gpmc_fck { 1105 #clock-cells = < 0x00 >; 1106 compatible = "fixed-factor-clock"; 1107 clocks = < 0x4a >; 1108 clock-mult = < 0x01 >; 1109 clock-div = < 0x01 >; 1110 }; 1111 1112 core_l4_ick { 1113 #clock-cells = < 0x00 >; 1114 compatible = "fixed-factor-clock"; 1115 clocks = < 0x40 >; 1116 clock-mult = < 0x01 >; 1117 clock-div = < 0x01 >; 1118 phandle = < 0x4b >; 1119 }; 1120 1121 mmchs2_ick@a10 { 1122 #clock-cells = < 0x00 >; 1123 compatible = "ti,omap3-interface-clock"; 1124 clocks = < 0x4b >; 1125 reg = < 0xa10 >; 1126 ti,bit-shift = < 0x19 >; 1127 phandle = < 0xc1 >; 1128 }; 1129 1130 mmchs1_ick@a10 { 1131 #clock-cells = < 0x00 >; 1132 compatible = "ti,omap3-interface-clock"; 1133 clocks = < 0x4b >; 1134 reg = < 0xa10 >; 1135 ti,bit-shift = < 0x18 >; 1136 phandle = < 0xc2 >; 1137 }; 1138 1139 hdq_ick@a10 { 1140 #clock-cells = < 0x00 >; 1141 compatible = "ti,omap3-interface-clock"; 1142 clocks = < 0x4b >; 1143 reg = < 0xa10 >; 1144 ti,bit-shift = < 0x16 >; 1145 phandle = < 0xc3 >; 1146 }; 1147 1148 mcspi4_ick@a10 { 1149 #clock-cells = < 0x00 >; 1150 compatible = "ti,omap3-interface-clock"; 1151 clocks = < 0x4b >; 1152 reg = < 0xa10 >; 1153 ti,bit-shift = < 0x15 >; 1154 phandle = < 0xc4 >; 1155 }; 1156 1157 mcspi3_ick@a10 { 1158 #clock-cells = < 0x00 >; 1159 compatible = "ti,omap3-interface-clock"; 1160 clocks = < 0x4b >; 1161 reg = < 0xa10 >; 1162 ti,bit-shift = < 0x14 >; 1163 phandle = < 0xc5 >; 1164 }; 1165 1166 mcspi2_ick@a10 { 1167 #clock-cells = < 0x00 >; 1168 compatible = "ti,omap3-interface-clock"; 1169 clocks = < 0x4b >; 1170 reg = < 0xa10 >; 1171 ti,bit-shift = < 0x13 >; 1172 phandle = < 0xc6 >; 1173 }; 1174 1175 mcspi1_ick@a10 { 1176 #clock-cells = < 0x00 >; 1177 compatible = "ti,omap3-interface-clock"; 1178 clocks = < 0x4b >; 1179 reg = < 0xa10 >; 1180 ti,bit-shift = < 0x12 >; 1181 phandle = < 0xc7 >; 1182 }; 1183 1184 i2c3_ick@a10 { 1185 #clock-cells = < 0x00 >; 1186 compatible = "ti,omap3-interface-clock"; 1187 clocks = < 0x4b >; 1188 reg = < 0xa10 >; 1189 ti,bit-shift = < 0x11 >; 1190 phandle = < 0xc8 >; 1191 }; 1192 1193 i2c2_ick@a10 { 1194 #clock-cells = < 0x00 >; 1195 compatible = "ti,omap3-interface-clock"; 1196 clocks = < 0x4b >; 1197 reg = < 0xa10 >; 1198 ti,bit-shift = < 0x10 >; 1199 phandle = < 0xc9 >; 1200 }; 1201 1202 i2c1_ick@a10 { 1203 #clock-cells = < 0x00 >; 1204 compatible = "ti,omap3-interface-clock"; 1205 clocks = < 0x4b >; 1206 reg = < 0xa10 >; 1207 ti,bit-shift = < 0x0f >; 1208 phandle = < 0xca >; 1209 }; 1210 1211 uart2_ick@a10 { 1212 #clock-cells = < 0x00 >; 1213 compatible = "ti,omap3-interface-clock"; 1214 clocks = < 0x4b >; 1215 reg = < 0xa10 >; 1216 ti,bit-shift = < 0x0e >; 1217 phandle = < 0xcb >; 1218 }; 1219 1220 uart1_ick@a10 { 1221 #clock-cells = < 0x00 >; 1222 compatible = "ti,omap3-interface-clock"; 1223 clocks = < 0x4b >; 1224 reg = < 0xa10 >; 1225 ti,bit-shift = < 0x0d >; 1226 phandle = < 0xcc >; 1227 }; 1228 1229 gpt11_ick@a10 { 1230 #clock-cells = < 0x00 >; 1231 compatible = "ti,omap3-interface-clock"; 1232 clocks = < 0x4b >; 1233 reg = < 0xa10 >; 1234 ti,bit-shift = < 0x0c >; 1235 phandle = < 0xcd >; 1236 }; 1237 1238 gpt10_ick@a10 { 1239 #clock-cells = < 0x00 >; 1240 compatible = "ti,omap3-interface-clock"; 1241 clocks = < 0x4b >; 1242 reg = < 0xa10 >; 1243 ti,bit-shift = < 0x0b >; 1244 phandle = < 0xce >; 1245 }; 1246 1247 mcbsp5_ick@a10 { 1248 #clock-cells = < 0x00 >; 1249 compatible = "ti,omap3-interface-clock"; 1250 clocks = < 0x4b >; 1251 reg = < 0xa10 >; 1252 ti,bit-shift = < 0x0a >; 1253 phandle = < 0xcf >; 1254 }; 1255 1256 mcbsp1_ick@a10 { 1257 #clock-cells = < 0x00 >; 1258 compatible = "ti,omap3-interface-clock"; 1259 clocks = < 0x4b >; 1260 reg = < 0xa10 >; 1261 ti,bit-shift = < 0x09 >; 1262 phandle = < 0xd0 >; 1263 }; 1264 1265 omapctrl_ick@a10 { 1266 #clock-cells = < 0x00 >; 1267 compatible = "ti,omap3-interface-clock"; 1268 clocks = < 0x4b >; 1269 reg = < 0xa10 >; 1270 ti,bit-shift = < 0x06 >; 1271 phandle = < 0xd1 >; 1272 }; 1273 1274 dss_tv_fck@e00 { 1275 #clock-cells = < 0x00 >; 1276 compatible = "ti,gate-clock"; 1277 clocks = < 0x39 >; 1278 reg = < 0xe00 >; 1279 ti,bit-shift = < 0x02 >; 1280 phandle = < 0xb0 >; 1281 }; 1282 1283 dss_96m_fck@e00 { 1284 #clock-cells = < 0x00 >; 1285 compatible = "ti,gate-clock"; 1286 clocks = < 0x46 >; 1287 reg = < 0xe00 >; 1288 ti,bit-shift = < 0x02 >; 1289 phandle = < 0xb1 >; 1290 }; 1291 1292 dss2_alwon_fck@e00 { 1293 #clock-cells = < 0x00 >; 1294 compatible = "ti,gate-clock"; 1295 clocks = < 0x1f >; 1296 reg = < 0xe00 >; 1297 ti,bit-shift = < 0x01 >; 1298 phandle = < 0xb2 >; 1299 }; 1300 1301 dummy_ck { 1302 #clock-cells = < 0x00 >; 1303 compatible = "fixed-clock"; 1304 clock-frequency = < 0x00 >; 1305 }; 1306 1307 gpt1_gate_fck@c00 { 1308 #clock-cells = < 0x00 >; 1309 compatible = "ti,composite-gate-clock"; 1310 clocks = < 0x1f >; 1311 ti,bit-shift = < 0x00 >; 1312 reg = < 0xc00 >; 1313 phandle = < 0x4c >; 1314 }; 1315 1316 gpt1_mux_fck@c40 { 1317 #clock-cells = < 0x00 >; 1318 compatible = "ti,composite-mux-clock"; 1319 clocks = < 0x41 0x1f >; 1320 reg = < 0xc40 >; 1321 phandle = < 0x4d >; 1322 }; 1323 1324 gpt1_fck { 1325 #clock-cells = < 0x00 >; 1326 compatible = "ti,composite-clock"; 1327 clocks = < 0x4c 0x4d >; 1328 }; 1329 1330 aes2_ick@a10 { 1331 #clock-cells = < 0x00 >; 1332 compatible = "ti,omap3-interface-clock"; 1333 clocks = < 0x4b >; 1334 ti,bit-shift = < 0x1c >; 1335 reg = < 0xa10 >; 1336 phandle = < 0xd2 >; 1337 }; 1338 1339 wkup_32k_fck { 1340 #clock-cells = < 0x00 >; 1341 compatible = "fixed-factor-clock"; 1342 clocks = < 0x41 >; 1343 clock-mult = < 0x01 >; 1344 clock-div = < 0x01 >; 1345 phandle = < 0x4e >; 1346 }; 1347 1348 gpio1_dbck@c00 { 1349 #clock-cells = < 0x00 >; 1350 compatible = "ti,gate-clock"; 1351 clocks = < 0x4e >; 1352 reg = < 0xc00 >; 1353 ti,bit-shift = < 0x03 >; 1354 phandle = < 0xa7 >; 1355 }; 1356 1357 sha12_ick@a10 { 1358 #clock-cells = < 0x00 >; 1359 compatible = "ti,omap3-interface-clock"; 1360 clocks = < 0x4b >; 1361 reg = < 0xa10 >; 1362 ti,bit-shift = < 0x1b >; 1363 phandle = < 0xd3 >; 1364 }; 1365 1366 wdt2_fck@c00 { 1367 #clock-cells = < 0x00 >; 1368 compatible = "ti,wait-gate-clock"; 1369 clocks = < 0x4e >; 1370 reg = < 0xc00 >; 1371 ti,bit-shift = < 0x05 >; 1372 phandle = < 0xa8 >; 1373 }; 1374 1375 wdt2_ick@c10 { 1376 #clock-cells = < 0x00 >; 1377 compatible = "ti,omap3-interface-clock"; 1378 clocks = < 0x4f >; 1379 reg = < 0xc10 >; 1380 ti,bit-shift = < 0x05 >; 1381 phandle = < 0xa9 >; 1382 }; 1383 1384 wdt1_ick@c10 { 1385 #clock-cells = < 0x00 >; 1386 compatible = "ti,omap3-interface-clock"; 1387 clocks = < 0x4f >; 1388 reg = < 0xc10 >; 1389 ti,bit-shift = < 0x04 >; 1390 phandle = < 0xaa >; 1391 }; 1392 1393 gpio1_ick@c10 { 1394 #clock-cells = < 0x00 >; 1395 compatible = "ti,omap3-interface-clock"; 1396 clocks = < 0x4f >; 1397 reg = < 0xc10 >; 1398 ti,bit-shift = < 0x03 >; 1399 phandle = < 0xab >; 1400 }; 1401 1402 omap_32ksync_ick@c10 { 1403 #clock-cells = < 0x00 >; 1404 compatible = "ti,omap3-interface-clock"; 1405 clocks = < 0x4f >; 1406 reg = < 0xc10 >; 1407 ti,bit-shift = < 0x02 >; 1408 phandle = < 0xac >; 1409 }; 1410 1411 gpt12_ick@c10 { 1412 #clock-cells = < 0x00 >; 1413 compatible = "ti,omap3-interface-clock"; 1414 clocks = < 0x4f >; 1415 reg = < 0xc10 >; 1416 ti,bit-shift = < 0x01 >; 1417 phandle = < 0xad >; 1418 }; 1419 1420 gpt1_ick@c10 { 1421 #clock-cells = < 0x00 >; 1422 compatible = "ti,omap3-interface-clock"; 1423 clocks = < 0x4f >; 1424 reg = < 0xc10 >; 1425 ti,bit-shift = < 0x00 >; 1426 phandle = < 0xae >; 1427 }; 1428 1429 per_96m_fck { 1430 #clock-cells = < 0x00 >; 1431 compatible = "fixed-factor-clock"; 1432 clocks = < 0x2a >; 1433 clock-mult = < 0x01 >; 1434 clock-div = < 0x01 >; 1435 phandle = < 0x0c >; 1436 }; 1437 1438 per_48m_fck { 1439 #clock-cells = < 0x00 >; 1440 compatible = "fixed-factor-clock"; 1441 clocks = < 0x31 >; 1442 clock-mult = < 0x01 >; 1443 clock-div = < 0x01 >; 1444 phandle = < 0x50 >; 1445 }; 1446 1447 uart3_fck@1000 { 1448 #clock-cells = < 0x00 >; 1449 compatible = "ti,wait-gate-clock"; 1450 clocks = < 0x50 >; 1451 reg = < 0x1000 >; 1452 ti,bit-shift = < 0x0b >; 1453 phandle = < 0x8d >; 1454 }; 1455 1456 gpt2_gate_fck@1000 { 1457 #clock-cells = < 0x00 >; 1458 compatible = "ti,composite-gate-clock"; 1459 clocks = < 0x1f >; 1460 ti,bit-shift = < 0x03 >; 1461 reg = < 0x1000 >; 1462 phandle = < 0x51 >; 1463 }; 1464 1465 gpt2_mux_fck@1040 { 1466 #clock-cells = < 0x00 >; 1467 compatible = "ti,composite-mux-clock"; 1468 clocks = < 0x41 0x1f >; 1469 reg = < 0x1040 >; 1470 phandle = < 0x52 >; 1471 }; 1472 1473 gpt2_fck { 1474 #clock-cells = < 0x00 >; 1475 compatible = "ti,composite-clock"; 1476 clocks = < 0x51 0x52 >; 1477 }; 1478 1479 gpt3_gate_fck@1000 { 1480 #clock-cells = < 0x00 >; 1481 compatible = "ti,composite-gate-clock"; 1482 clocks = < 0x1f >; 1483 ti,bit-shift = < 0x04 >; 1484 reg = < 0x1000 >; 1485 phandle = < 0x53 >; 1486 }; 1487 1488 gpt3_mux_fck@1040 { 1489 #clock-cells = < 0x00 >; 1490 compatible = "ti,composite-mux-clock"; 1491 clocks = < 0x41 0x1f >; 1492 ti,bit-shift = < 0x01 >; 1493 reg = < 0x1040 >; 1494 phandle = < 0x54 >; 1495 }; 1496 1497 gpt3_fck { 1498 #clock-cells = < 0x00 >; 1499 compatible = "ti,composite-clock"; 1500 clocks = < 0x53 0x54 >; 1501 }; 1502 1503 gpt4_gate_fck@1000 { 1504 #clock-cells = < 0x00 >; 1505 compatible = "ti,composite-gate-clock"; 1506 clocks = < 0x1f >; 1507 ti,bit-shift = < 0x05 >; 1508 reg = < 0x1000 >; 1509 phandle = < 0x55 >; 1510 }; 1511 1512 gpt4_mux_fck@1040 { 1513 #clock-cells = < 0x00 >; 1514 compatible = "ti,composite-mux-clock"; 1515 clocks = < 0x41 0x1f >; 1516 ti,bit-shift = < 0x02 >; 1517 reg = < 0x1040 >; 1518 phandle = < 0x56 >; 1519 }; 1520 1521 gpt4_fck { 1522 #clock-cells = < 0x00 >; 1523 compatible = "ti,composite-clock"; 1524 clocks = < 0x55 0x56 >; 1525 }; 1526 1527 gpt5_gate_fck@1000 { 1528 #clock-cells = < 0x00 >; 1529 compatible = "ti,composite-gate-clock"; 1530 clocks = < 0x1f >; 1531 ti,bit-shift = < 0x06 >; 1532 reg = < 0x1000 >; 1533 phandle = < 0x57 >; 1534 }; 1535 1536 gpt5_mux_fck@1040 { 1537 #clock-cells = < 0x00 >; 1538 compatible = "ti,composite-mux-clock"; 1539 clocks = < 0x41 0x1f >; 1540 ti,bit-shift = < 0x03 >; 1541 reg = < 0x1040 >; 1542 phandle = < 0x58 >; 1543 }; 1544 1545 gpt5_fck { 1546 #clock-cells = < 0x00 >; 1547 compatible = "ti,composite-clock"; 1548 clocks = < 0x57 0x58 >; 1549 }; 1550 1551 gpt6_gate_fck@1000 { 1552 #clock-cells = < 0x00 >; 1553 compatible = "ti,composite-gate-clock"; 1554 clocks = < 0x1f >; 1555 ti,bit-shift = < 0x07 >; 1556 reg = < 0x1000 >; 1557 phandle = < 0x59 >; 1558 }; 1559 1560 gpt6_mux_fck@1040 { 1561 #clock-cells = < 0x00 >; 1562 compatible = "ti,composite-mux-clock"; 1563 clocks = < 0x41 0x1f >; 1564 ti,bit-shift = < 0x04 >; 1565 reg = < 0x1040 >; 1566 phandle = < 0x5a >; 1567 }; 1568 1569 gpt6_fck { 1570 #clock-cells = < 0x00 >; 1571 compatible = "ti,composite-clock"; 1572 clocks = < 0x59 0x5a >; 1573 }; 1574 1575 gpt7_gate_fck@1000 { 1576 #clock-cells = < 0x00 >; 1577 compatible = "ti,composite-gate-clock"; 1578 clocks = < 0x1f >; 1579 ti,bit-shift = < 0x08 >; 1580 reg = < 0x1000 >; 1581 phandle = < 0x5b >; 1582 }; 1583 1584 gpt7_mux_fck@1040 { 1585 #clock-cells = < 0x00 >; 1586 compatible = "ti,composite-mux-clock"; 1587 clocks = < 0x41 0x1f >; 1588 ti,bit-shift = < 0x05 >; 1589 reg = < 0x1040 >; 1590 phandle = < 0x5c >; 1591 }; 1592 1593 gpt7_fck { 1594 #clock-cells = < 0x00 >; 1595 compatible = "ti,composite-clock"; 1596 clocks = < 0x5b 0x5c >; 1597 }; 1598 1599 gpt8_gate_fck@1000 { 1600 #clock-cells = < 0x00 >; 1601 compatible = "ti,composite-gate-clock"; 1602 clocks = < 0x1f >; 1603 ti,bit-shift = < 0x09 >; 1604 reg = < 0x1000 >; 1605 phandle = < 0x5d >; 1606 }; 1607 1608 gpt8_mux_fck@1040 { 1609 #clock-cells = < 0x00 >; 1610 compatible = "ti,composite-mux-clock"; 1611 clocks = < 0x41 0x1f >; 1612 ti,bit-shift = < 0x06 >; 1613 reg = < 0x1040 >; 1614 phandle = < 0x5e >; 1615 }; 1616 1617 gpt8_fck { 1618 #clock-cells = < 0x00 >; 1619 compatible = "ti,composite-clock"; 1620 clocks = < 0x5d 0x5e >; 1621 }; 1622 1623 gpt9_gate_fck@1000 { 1624 #clock-cells = < 0x00 >; 1625 compatible = "ti,composite-gate-clock"; 1626 clocks = < 0x1f >; 1627 ti,bit-shift = < 0x0a >; 1628 reg = < 0x1000 >; 1629 phandle = < 0x5f >; 1630 }; 1631 1632 gpt9_mux_fck@1040 { 1633 #clock-cells = < 0x00 >; 1634 compatible = "ti,composite-mux-clock"; 1635 clocks = < 0x41 0x1f >; 1636 ti,bit-shift = < 0x07 >; 1637 reg = < 0x1040 >; 1638 phandle = < 0x60 >; 1639 }; 1640 1641 gpt9_fck { 1642 #clock-cells = < 0x00 >; 1643 compatible = "ti,composite-clock"; 1644 clocks = < 0x5f 0x60 >; 1645 }; 1646 1647 per_32k_alwon_fck { 1648 #clock-cells = < 0x00 >; 1649 compatible = "fixed-factor-clock"; 1650 clocks = < 0x41 >; 1651 clock-mult = < 0x01 >; 1652 clock-div = < 0x01 >; 1653 phandle = < 0x61 >; 1654 }; 1655 1656 gpio6_dbck@1000 { 1657 #clock-cells = < 0x00 >; 1658 compatible = "ti,gate-clock"; 1659 clocks = < 0x61 >; 1660 reg = < 0x1000 >; 1661 ti,bit-shift = < 0x11 >; 1662 phandle = < 0x8e >; 1663 }; 1664 1665 gpio5_dbck@1000 { 1666 #clock-cells = < 0x00 >; 1667 compatible = "ti,gate-clock"; 1668 clocks = < 0x61 >; 1669 reg = < 0x1000 >; 1670 ti,bit-shift = < 0x10 >; 1671 phandle = < 0x8f >; 1672 }; 1673 1674 gpio4_dbck@1000 { 1675 #clock-cells = < 0x00 >; 1676 compatible = "ti,gate-clock"; 1677 clocks = < 0x61 >; 1678 reg = < 0x1000 >; 1679 ti,bit-shift = < 0x0f >; 1680 phandle = < 0x90 >; 1681 }; 1682 1683 gpio3_dbck@1000 { 1684 #clock-cells = < 0x00 >; 1685 compatible = "ti,gate-clock"; 1686 clocks = < 0x61 >; 1687 reg = < 0x1000 >; 1688 ti,bit-shift = < 0x0e >; 1689 phandle = < 0x91 >; 1690 }; 1691 1692 gpio2_dbck@1000 { 1693 #clock-cells = < 0x00 >; 1694 compatible = "ti,gate-clock"; 1695 clocks = < 0x61 >; 1696 reg = < 0x1000 >; 1697 ti,bit-shift = < 0x0d >; 1698 phandle = < 0x92 >; 1699 }; 1700 1701 wdt3_fck@1000 { 1702 #clock-cells = < 0x00 >; 1703 compatible = "ti,wait-gate-clock"; 1704 clocks = < 0x61 >; 1705 reg = < 0x1000 >; 1706 ti,bit-shift = < 0x0c >; 1707 phandle = < 0x93 >; 1708 }; 1709 1710 per_l4_ick { 1711 #clock-cells = < 0x00 >; 1712 compatible = "fixed-factor-clock"; 1713 clocks = < 0x40 >; 1714 clock-mult = < 0x01 >; 1715 clock-div = < 0x01 >; 1716 phandle = < 0x62 >; 1717 }; 1718 1719 gpio6_ick@1010 { 1720 #clock-cells = < 0x00 >; 1721 compatible = "ti,omap3-interface-clock"; 1722 clocks = < 0x62 >; 1723 reg = < 0x1010 >; 1724 ti,bit-shift = < 0x11 >; 1725 phandle = < 0x94 >; 1726 }; 1727 1728 gpio5_ick@1010 { 1729 #clock-cells = < 0x00 >; 1730 compatible = "ti,omap3-interface-clock"; 1731 clocks = < 0x62 >; 1732 reg = < 0x1010 >; 1733 ti,bit-shift = < 0x10 >; 1734 phandle = < 0x95 >; 1735 }; 1736 1737 gpio4_ick@1010 { 1738 #clock-cells = < 0x00 >; 1739 compatible = "ti,omap3-interface-clock"; 1740 clocks = < 0x62 >; 1741 reg = < 0x1010 >; 1742 ti,bit-shift = < 0x0f >; 1743 phandle = < 0x96 >; 1744 }; 1745 1746 gpio3_ick@1010 { 1747 #clock-cells = < 0x00 >; 1748 compatible = "ti,omap3-interface-clock"; 1749 clocks = < 0x62 >; 1750 reg = < 0x1010 >; 1751 ti,bit-shift = < 0x0e >; 1752 phandle = < 0x97 >; 1753 }; 1754 1755 gpio2_ick@1010 { 1756 #clock-cells = < 0x00 >; 1757 compatible = "ti,omap3-interface-clock"; 1758 clocks = < 0x62 >; 1759 reg = < 0x1010 >; 1760 ti,bit-shift = < 0x0d >; 1761 phandle = < 0x98 >; 1762 }; 1763 1764 wdt3_ick@1010 { 1765 #clock-cells = < 0x00 >; 1766 compatible = "ti,omap3-interface-clock"; 1767 clocks = < 0x62 >; 1768 reg = < 0x1010 >; 1769 ti,bit-shift = < 0x0c >; 1770 phandle = < 0x99 >; 1771 }; 1772 1773 uart3_ick@1010 { 1774 #clock-cells = < 0x00 >; 1775 compatible = "ti,omap3-interface-clock"; 1776 clocks = < 0x62 >; 1777 reg = < 0x1010 >; 1778 ti,bit-shift = < 0x0b >; 1779 phandle = < 0x9a >; 1780 }; 1781 1782 uart4_ick@1010 { 1783 #clock-cells = < 0x00 >; 1784 compatible = "ti,omap3-interface-clock"; 1785 clocks = < 0x62 >; 1786 reg = < 0x1010 >; 1787 ti,bit-shift = < 0x12 >; 1788 phandle = < 0x9b >; 1789 }; 1790 1791 gpt9_ick@1010 { 1792 #clock-cells = < 0x00 >; 1793 compatible = "ti,omap3-interface-clock"; 1794 clocks = < 0x62 >; 1795 reg = < 0x1010 >; 1796 ti,bit-shift = < 0x0a >; 1797 phandle = < 0x9c >; 1798 }; 1799 1800 gpt8_ick@1010 { 1801 #clock-cells = < 0x00 >; 1802 compatible = "ti,omap3-interface-clock"; 1803 clocks = < 0x62 >; 1804 reg = < 0x1010 >; 1805 ti,bit-shift = < 0x09 >; 1806 phandle = < 0x9d >; 1807 }; 1808 1809 gpt7_ick@1010 { 1810 #clock-cells = < 0x00 >; 1811 compatible = "ti,omap3-interface-clock"; 1812 clocks = < 0x62 >; 1813 reg = < 0x1010 >; 1814 ti,bit-shift = < 0x08 >; 1815 phandle = < 0x9e >; 1816 }; 1817 1818 gpt6_ick@1010 { 1819 #clock-cells = < 0x00 >; 1820 compatible = "ti,omap3-interface-clock"; 1821 clocks = < 0x62 >; 1822 reg = < 0x1010 >; 1823 ti,bit-shift = < 0x07 >; 1824 phandle = < 0x9f >; 1825 }; 1826 1827 gpt5_ick@1010 { 1828 #clock-cells = < 0x00 >; 1829 compatible = "ti,omap3-interface-clock"; 1830 clocks = < 0x62 >; 1831 reg = < 0x1010 >; 1832 ti,bit-shift = < 0x06 >; 1833 phandle = < 0xa0 >; 1834 }; 1835 1836 gpt4_ick@1010 { 1837 #clock-cells = < 0x00 >; 1838 compatible = "ti,omap3-interface-clock"; 1839 clocks = < 0x62 >; 1840 reg = < 0x1010 >; 1841 ti,bit-shift = < 0x05 >; 1842 phandle = < 0xa1 >; 1843 }; 1844 1845 gpt3_ick@1010 { 1846 #clock-cells = < 0x00 >; 1847 compatible = "ti,omap3-interface-clock"; 1848 clocks = < 0x62 >; 1849 reg = < 0x1010 >; 1850 ti,bit-shift = < 0x04 >; 1851 phandle = < 0xa2 >; 1852 }; 1853 1854 gpt2_ick@1010 { 1855 #clock-cells = < 0x00 >; 1856 compatible = "ti,omap3-interface-clock"; 1857 clocks = < 0x62 >; 1858 reg = < 0x1010 >; 1859 ti,bit-shift = < 0x03 >; 1860 phandle = < 0xa3 >; 1861 }; 1862 1863 mcbsp2_ick@1010 { 1864 #clock-cells = < 0x00 >; 1865 compatible = "ti,omap3-interface-clock"; 1866 clocks = < 0x62 >; 1867 reg = < 0x1010 >; 1868 ti,bit-shift = < 0x00 >; 1869 phandle = < 0xa4 >; 1870 }; 1871 1872 mcbsp3_ick@1010 { 1873 #clock-cells = < 0x00 >; 1874 compatible = "ti,omap3-interface-clock"; 1875 clocks = < 0x62 >; 1876 reg = < 0x1010 >; 1877 ti,bit-shift = < 0x01 >; 1878 phandle = < 0xa5 >; 1879 }; 1880 1881 mcbsp4_ick@1010 { 1882 #clock-cells = < 0x00 >; 1883 compatible = "ti,omap3-interface-clock"; 1884 clocks = < 0x62 >; 1885 reg = < 0x1010 >; 1886 ti,bit-shift = < 0x02 >; 1887 phandle = < 0xa6 >; 1888 }; 1889 1890 mcbsp2_gate_fck@1000 { 1891 #clock-cells = < 0x00 >; 1892 compatible = "ti,composite-gate-clock"; 1893 clocks = < 0x07 >; 1894 ti,bit-shift = < 0x00 >; 1895 reg = < 0x1000 >; 1896 phandle = < 0x0d >; 1897 }; 1898 1899 mcbsp3_gate_fck@1000 { 1900 #clock-cells = < 0x00 >; 1901 compatible = "ti,composite-gate-clock"; 1902 clocks = < 0x07 >; 1903 ti,bit-shift = < 0x01 >; 1904 reg = < 0x1000 >; 1905 phandle = < 0x0f >; 1906 }; 1907 1908 mcbsp4_gate_fck@1000 { 1909 #clock-cells = < 0x00 >; 1910 compatible = "ti,composite-gate-clock"; 1911 clocks = < 0x07 >; 1912 ti,bit-shift = < 0x02 >; 1913 reg = < 0x1000 >; 1914 phandle = < 0x11 >; 1915 }; 1916 1917 emu_src_mux_ck@1140 { 1918 #clock-cells = < 0x00 >; 1919 compatible = "ti,mux-clock"; 1920 clocks = < 0x1f 0x63 0x64 0x65 >; 1921 reg = < 0x1140 >; 1922 phandle = < 0x66 >; 1923 }; 1924 1925 emu_src_ck { 1926 #clock-cells = < 0x00 >; 1927 compatible = "ti,clkdm-gate-clock"; 1928 clocks = < 0x66 >; 1929 phandle = < 0x67 >; 1930 }; 1931 1932 pclk_fck@1140 { 1933 #clock-cells = < 0x00 >; 1934 compatible = "ti,divider-clock"; 1935 clocks = < 0x67 >; 1936 ti,bit-shift = < 0x08 >; 1937 ti,max-div = < 0x07 >; 1938 reg = < 0x1140 >; 1939 ti,index-starts-at-one; 1940 }; 1941 1942 pclkx2_fck@1140 { 1943 #clock-cells = < 0x00 >; 1944 compatible = "ti,divider-clock"; 1945 clocks = < 0x67 >; 1946 ti,bit-shift = < 0x06 >; 1947 ti,max-div = < 0x03 >; 1948 reg = < 0x1140 >; 1949 ti,index-starts-at-one; 1950 }; 1951 1952 atclk_fck@1140 { 1953 #clock-cells = < 0x00 >; 1954 compatible = "ti,divider-clock"; 1955 clocks = < 0x67 >; 1956 ti,bit-shift = < 0x04 >; 1957 ti,max-div = < 0x03 >; 1958 reg = < 0x1140 >; 1959 ti,index-starts-at-one; 1960 }; 1961 1962 traceclk_src_fck@1140 { 1963 #clock-cells = < 0x00 >; 1964 compatible = "ti,mux-clock"; 1965 clocks = < 0x1f 0x63 0x64 0x65 >; 1966 ti,bit-shift = < 0x02 >; 1967 reg = < 0x1140 >; 1968 phandle = < 0x68 >; 1969 }; 1970 1971 traceclk_fck@1140 { 1972 #clock-cells = < 0x00 >; 1973 compatible = "ti,divider-clock"; 1974 clocks = < 0x68 >; 1975 ti,bit-shift = < 0x0b >; 1976 ti,max-div = < 0x07 >; 1977 reg = < 0x1140 >; 1978 ti,index-starts-at-one; 1979 }; 1980 1981 secure_32k_fck { 1982 #clock-cells = < 0x00 >; 1983 compatible = "fixed-clock"; 1984 clock-frequency = < 0x8000 >; 1985 phandle = < 0x69 >; 1986 }; 1987 1988 gpt12_fck { 1989 #clock-cells = < 0x00 >; 1990 compatible = "fixed-factor-clock"; 1991 clocks = < 0x69 >; 1992 clock-mult = < 0x01 >; 1993 clock-div = < 0x01 >; 1994 }; 1995 1996 wdt1_fck { 1997 #clock-cells = < 0x00 >; 1998 compatible = "fixed-factor-clock"; 1999 clocks = < 0x69 >; 2000 clock-mult = < 0x01 >; 2001 clock-div = < 0x01 >; 2002 }; 2003 2004 security_l4_ick2 { 2005 #clock-cells = < 0x00 >; 2006 compatible = "fixed-factor-clock"; 2007 clocks = < 0x40 >; 2008 clock-mult = < 0x01 >; 2009 clock-div = < 0x01 >; 2010 phandle = < 0x6a >; 2011 }; 2012 2013 aes1_ick@a14 { 2014 #clock-cells = < 0x00 >; 2015 compatible = "ti,omap3-interface-clock"; 2016 clocks = < 0x6a >; 2017 ti,bit-shift = < 0x03 >; 2018 reg = < 0xa14 >; 2019 }; 2020 2021 rng_ick@a14 { 2022 #clock-cells = < 0x00 >; 2023 compatible = "ti,omap3-interface-clock"; 2024 clocks = < 0x6a >; 2025 reg = < 0xa14 >; 2026 ti,bit-shift = < 0x02 >; 2027 }; 2028 2029 sha11_ick@a14 { 2030 #clock-cells = < 0x00 >; 2031 compatible = "ti,omap3-interface-clock"; 2032 clocks = < 0x6a >; 2033 reg = < 0xa14 >; 2034 ti,bit-shift = < 0x01 >; 2035 }; 2036 2037 des1_ick@a14 { 2038 #clock-cells = < 0x00 >; 2039 compatible = "ti,omap3-interface-clock"; 2040 clocks = < 0x6a >; 2041 reg = < 0xa14 >; 2042 ti,bit-shift = < 0x00 >; 2043 }; 2044 2045 cam_mclk@f00 { 2046 #clock-cells = < 0x00 >; 2047 compatible = "ti,gate-clock"; 2048 clocks = < 0x6b >; 2049 ti,bit-shift = < 0x00 >; 2050 reg = < 0xf00 >; 2051 ti,set-rate-parent; 2052 }; 2053 2054 cam_ick@f10 { 2055 #clock-cells = < 0x00 >; 2056 compatible = "ti,omap3-no-wait-interface-clock"; 2057 clocks = < 0x40 >; 2058 reg = < 0xf10 >; 2059 ti,bit-shift = < 0x00 >; 2060 phandle = < 0xda >; 2061 }; 2062 2063 csi2_96m_fck@f00 { 2064 #clock-cells = < 0x00 >; 2065 compatible = "ti,gate-clock"; 2066 clocks = < 0x06 >; 2067 reg = < 0xf00 >; 2068 ti,bit-shift = < 0x01 >; 2069 phandle = < 0xdb >; 2070 }; 2071 2072 security_l3_ick { 2073 #clock-cells = < 0x00 >; 2074 compatible = "fixed-factor-clock"; 2075 clocks = < 0x3f >; 2076 clock-mult = < 0x01 >; 2077 clock-div = < 0x01 >; 2078 phandle = < 0x6c >; 2079 }; 2080 2081 pka_ick@a14 { 2082 #clock-cells = < 0x00 >; 2083 compatible = "ti,omap3-interface-clock"; 2084 clocks = < 0x6c >; 2085 reg = < 0xa14 >; 2086 ti,bit-shift = < 0x04 >; 2087 }; 2088 2089 icr_ick@a10 { 2090 #clock-cells = < 0x00 >; 2091 compatible = "ti,omap3-interface-clock"; 2092 clocks = < 0x4b >; 2093 reg = < 0xa10 >; 2094 ti,bit-shift = < 0x1d >; 2095 }; 2096 2097 des2_ick@a10 { 2098 #clock-cells = < 0x00 >; 2099 compatible = "ti,omap3-interface-clock"; 2100 clocks = < 0x4b >; 2101 reg = < 0xa10 >; 2102 ti,bit-shift = < 0x1a >; 2103 }; 2104 2105 mspro_ick@a10 { 2106 #clock-cells = < 0x00 >; 2107 compatible = "ti,omap3-interface-clock"; 2108 clocks = < 0x4b >; 2109 reg = < 0xa10 >; 2110 ti,bit-shift = < 0x17 >; 2111 }; 2112 2113 mailboxes_ick@a10 { 2114 #clock-cells = < 0x00 >; 2115 compatible = "ti,omap3-interface-clock"; 2116 clocks = < 0x4b >; 2117 reg = < 0xa10 >; 2118 ti,bit-shift = < 0x07 >; 2119 }; 2120 2121 ssi_l4_ick { 2122 #clock-cells = < 0x00 >; 2123 compatible = "fixed-factor-clock"; 2124 clocks = < 0x40 >; 2125 clock-mult = < 0x01 >; 2126 clock-div = < 0x01 >; 2127 phandle = < 0x73 >; 2128 }; 2129 2130 sr1_fck@c00 { 2131 #clock-cells = < 0x00 >; 2132 compatible = "ti,wait-gate-clock"; 2133 clocks = < 0x1f >; 2134 reg = < 0xc00 >; 2135 ti,bit-shift = < 0x06 >; 2136 phandle = < 0x101 >; 2137 }; 2138 2139 sr2_fck@c00 { 2140 #clock-cells = < 0x00 >; 2141 compatible = "ti,wait-gate-clock"; 2142 clocks = < 0x1f >; 2143 reg = < 0xc00 >; 2144 ti,bit-shift = < 0x07 >; 2145 phandle = < 0x100 >; 2146 }; 2147 2148 sr_l4_ick { 2149 #clock-cells = < 0x00 >; 2150 compatible = "fixed-factor-clock"; 2151 clocks = < 0x40 >; 2152 clock-mult = < 0x01 >; 2153 clock-div = < 0x01 >; 2154 }; 2155 2156 dpll2_fck@40 { 2157 #clock-cells = < 0x00 >; 2158 compatible = "ti,divider-clock"; 2159 clocks = < 0x27 >; 2160 ti,bit-shift = < 0x13 >; 2161 ti,max-div = < 0x07 >; 2162 reg = < 0x40 >; 2163 ti,index-starts-at-one; 2164 phandle = < 0x6d >; 2165 }; 2166 2167 dpll2_ck@4 { 2168 #clock-cells = < 0x00 >; 2169 compatible = "ti,omap3-dpll-clock"; 2170 clocks = < 0x1f 0x6d >; 2171 reg = < 0x04 0x24 0x40 0x34 >; 2172 ti,low-power-stop; 2173 ti,lock; 2174 ti,low-power-bypass; 2175 phandle = < 0x6e >; 2176 }; 2177 2178 dpll2_m2_ck@44 { 2179 #clock-cells = < 0x00 >; 2180 compatible = "ti,divider-clock"; 2181 clocks = < 0x6e >; 2182 ti,max-div = < 0x1f >; 2183 reg = < 0x44 >; 2184 ti,index-starts-at-one; 2185 phandle = < 0x6f >; 2186 }; 2187 2188 iva2_ck@0 { 2189 #clock-cells = < 0x00 >; 2190 compatible = "ti,wait-gate-clock"; 2191 clocks = < 0x6f >; 2192 reg = < 0x00 >; 2193 ti,bit-shift = < 0x00 >; 2194 phandle = < 0xdc >; 2195 }; 2196 2197 modem_fck@a00 { 2198 #clock-cells = < 0x00 >; 2199 compatible = "ti,omap3-interface-clock"; 2200 clocks = < 0x1f >; 2201 reg = < 0xa00 >; 2202 ti,bit-shift = < 0x1f >; 2203 phandle = < 0xdd >; 2204 }; 2205 2206 sad2d_ick@a10 { 2207 #clock-cells = < 0x00 >; 2208 compatible = "ti,omap3-interface-clock"; 2209 clocks = < 0x3f >; 2210 reg = < 0xa10 >; 2211 ti,bit-shift = < 0x03 >; 2212 phandle = < 0xde >; 2213 }; 2214 2215 mad2d_ick@a18 { 2216 #clock-cells = < 0x00 >; 2217 compatible = "ti,omap3-interface-clock"; 2218 clocks = < 0x3f >; 2219 reg = < 0xa18 >; 2220 ti,bit-shift = < 0x03 >; 2221 phandle = < 0xdf >; 2222 }; 2223 2224 mspro_fck@a00 { 2225 #clock-cells = < 0x00 >; 2226 compatible = "ti,wait-gate-clock"; 2227 clocks = < 0x06 >; 2228 reg = < 0xa00 >; 2229 ti,bit-shift = < 0x17 >; 2230 }; 2231 2232 ssi_ssr_gate_fck_3430es2@a00 { 2233 #clock-cells = < 0x00 >; 2234 compatible = "ti,composite-no-wait-gate-clock"; 2235 clocks = < 0x20 >; 2236 ti,bit-shift = < 0x00 >; 2237 reg = < 0xa00 >; 2238 phandle = < 0x70 >; 2239 }; 2240 2241 ssi_ssr_div_fck_3430es2@a40 { 2242 #clock-cells = < 0x00 >; 2243 compatible = "ti,composite-divider-clock"; 2244 clocks = < 0x20 >; 2245 ti,bit-shift = < 0x08 >; 2246 reg = < 0xa40 >; 2247 ti,dividers = < 0x00 0x01 0x02 0x03 0x04 0x00 0x06 0x00 0x08 >; 2248 phandle = < 0x71 >; 2249 }; 2250 2251 ssi_ssr_fck_3430es2 { 2252 #clock-cells = < 0x00 >; 2253 compatible = "ti,composite-clock"; 2254 clocks = < 0x70 0x71 >; 2255 phandle = < 0x72 >; 2256 }; 2257 2258 ssi_sst_fck_3430es2 { 2259 #clock-cells = < 0x00 >; 2260 compatible = "fixed-factor-clock"; 2261 clocks = < 0x72 >; 2262 clock-mult = < 0x01 >; 2263 clock-div = < 0x02 >; 2264 phandle = < 0xfc >; 2265 }; 2266 2267 hsotgusb_ick_3430es2@a10 { 2268 #clock-cells = < 0x00 >; 2269 compatible = "ti,omap3-hsotgusb-interface-clock"; 2270 clocks = < 0x4a >; 2271 reg = < 0xa10 >; 2272 ti,bit-shift = < 0x04 >; 2273 phandle = < 0x8c >; 2274 }; 2275 2276 ssi_ick_3430es2@a10 { 2277 #clock-cells = < 0x00 >; 2278 compatible = "ti,omap3-ssi-interface-clock"; 2279 clocks = < 0x73 >; 2280 reg = < 0xa10 >; 2281 ti,bit-shift = < 0x00 >; 2282 phandle = < 0xfd >; 2283 }; 2284 2285 usim_gate_fck@c00 { 2286 #clock-cells = < 0x00 >; 2287 compatible = "ti,composite-gate-clock"; 2288 clocks = < 0x46 >; 2289 ti,bit-shift = < 0x09 >; 2290 reg = < 0xc00 >; 2291 phandle = < 0x7e >; 2292 }; 2293 2294 sys_d2_ck { 2295 #clock-cells = < 0x00 >; 2296 compatible = "fixed-factor-clock"; 2297 clocks = < 0x1f >; 2298 clock-mult = < 0x01 >; 2299 clock-div = < 0x02 >; 2300 phandle = < 0x75 >; 2301 }; 2302 2303 omap_96m_d2_fck { 2304 #clock-cells = < 0x00 >; 2305 compatible = "fixed-factor-clock"; 2306 clocks = < 0x46 >; 2307 clock-mult = < 0x01 >; 2308 clock-div = < 0x02 >; 2309 phandle = < 0x76 >; 2310 }; 2311 2312 omap_96m_d4_fck { 2313 #clock-cells = < 0x00 >; 2314 compatible = "fixed-factor-clock"; 2315 clocks = < 0x46 >; 2316 clock-mult = < 0x01 >; 2317 clock-div = < 0x04 >; 2318 phandle = < 0x77 >; 2319 }; 2320 2321 omap_96m_d8_fck { 2322 #clock-cells = < 0x00 >; 2323 compatible = "fixed-factor-clock"; 2324 clocks = < 0x46 >; 2325 clock-mult = < 0x01 >; 2326 clock-div = < 0x08 >; 2327 phandle = < 0x78 >; 2328 }; 2329 2330 omap_96m_d10_fck { 2331 #clock-cells = < 0x00 >; 2332 compatible = "fixed-factor-clock"; 2333 clocks = < 0x46 >; 2334 clock-mult = < 0x01 >; 2335 clock-div = < 0x0a >; 2336 phandle = < 0x79 >; 2337 }; 2338 2339 dpll5_m2_d4_ck { 2340 #clock-cells = < 0x00 >; 2341 compatible = "fixed-factor-clock"; 2342 clocks = < 0x74 >; 2343 clock-mult = < 0x01 >; 2344 clock-div = < 0x04 >; 2345 phandle = < 0x7a >; 2346 }; 2347 2348 dpll5_m2_d8_ck { 2349 #clock-cells = < 0x00 >; 2350 compatible = "fixed-factor-clock"; 2351 clocks = < 0x74 >; 2352 clock-mult = < 0x01 >; 2353 clock-div = < 0x08 >; 2354 phandle = < 0x7b >; 2355 }; 2356 2357 dpll5_m2_d16_ck { 2358 #clock-cells = < 0x00 >; 2359 compatible = "fixed-factor-clock"; 2360 clocks = < 0x74 >; 2361 clock-mult = < 0x01 >; 2362 clock-div = < 0x10 >; 2363 phandle = < 0x7c >; 2364 }; 2365 2366 dpll5_m2_d20_ck { 2367 #clock-cells = < 0x00 >; 2368 compatible = "fixed-factor-clock"; 2369 clocks = < 0x74 >; 2370 clock-mult = < 0x01 >; 2371 clock-div = < 0x14 >; 2372 phandle = < 0x7d >; 2373 }; 2374 2375 usim_mux_fck@c40 { 2376 #clock-cells = < 0x00 >; 2377 compatible = "ti,composite-mux-clock"; 2378 clocks = < 0x1f 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d >; 2379 ti,bit-shift = < 0x03 >; 2380 reg = < 0xc40 >; 2381 ti,index-starts-at-one; 2382 phandle = < 0x7f >; 2383 }; 2384 2385 usim_fck { 2386 #clock-cells = < 0x00 >; 2387 compatible = "ti,composite-clock"; 2388 clocks = < 0x7e 0x7f >; 2389 }; 2390 2391 usim_ick@c10 { 2392 #clock-cells = < 0x00 >; 2393 compatible = "ti,omap3-interface-clock"; 2394 clocks = < 0x4f >; 2395 reg = < 0xc10 >; 2396 ti,bit-shift = < 0x09 >; 2397 phandle = < 0xaf >; 2398 }; 2399 2400 dpll5_ck@d04 { 2401 #clock-cells = < 0x00 >; 2402 compatible = "ti,omap3-dpll-clock"; 2403 clocks = < 0x1f 0x1f >; 2404 reg = < 0xd04 0xd24 0xd4c 0xd34 >; 2405 ti,low-power-stop; 2406 ti,lock; 2407 phandle = < 0x80 >; 2408 }; 2409 2410 dpll5_m2_ck@d50 { 2411 #clock-cells = < 0x00 >; 2412 compatible = "ti,divider-clock"; 2413 clocks = < 0x80 >; 2414 ti,max-div = < 0x1f >; 2415 reg = < 0xd50 >; 2416 ti,index-starts-at-one; 2417 phandle = < 0x74 >; 2418 }; 2419 2420 sgx_gate_fck@b00 { 2421 #clock-cells = < 0x00 >; 2422 compatible = "ti,composite-gate-clock"; 2423 clocks = < 0x27 >; 2424 ti,bit-shift = < 0x01 >; 2425 reg = < 0xb00 >; 2426 phandle = < 0x88 >; 2427 }; 2428 2429 core_d3_ck { 2430 #clock-cells = < 0x00 >; 2431 compatible = "fixed-factor-clock"; 2432 clocks = < 0x27 >; 2433 clock-mult = < 0x01 >; 2434 clock-div = < 0x03 >; 2435 phandle = < 0x81 >; 2436 }; 2437 2438 core_d4_ck { 2439 #clock-cells = < 0x00 >; 2440 compatible = "fixed-factor-clock"; 2441 clocks = < 0x27 >; 2442 clock-mult = < 0x01 >; 2443 clock-div = < 0x04 >; 2444 phandle = < 0x82 >; 2445 }; 2446 2447 core_d6_ck { 2448 #clock-cells = < 0x00 >; 2449 compatible = "fixed-factor-clock"; 2450 clocks = < 0x27 >; 2451 clock-mult = < 0x01 >; 2452 clock-div = < 0x06 >; 2453 phandle = < 0x83 >; 2454 }; 2455 2456 omap_192m_alwon_fck { 2457 #clock-cells = < 0x00 >; 2458 compatible = "fixed-factor-clock"; 2459 clocks = < 0x23 >; 2460 clock-mult = < 0x01 >; 2461 clock-div = < 0x01 >; 2462 phandle = < 0x84 >; 2463 }; 2464 2465 core_d2_ck { 2466 #clock-cells = < 0x00 >; 2467 compatible = "fixed-factor-clock"; 2468 clocks = < 0x27 >; 2469 clock-mult = < 0x01 >; 2470 clock-div = < 0x02 >; 2471 phandle = < 0x85 >; 2472 }; 2473 2474 sgx_mux_fck@b40 { 2475 #clock-cells = < 0x00 >; 2476 compatible = "ti,composite-mux-clock"; 2477 clocks = < 0x81 0x82 0x83 0x2b 0x84 0x85 0x86 0x87 >; 2478 reg = < 0xb40 >; 2479 phandle = < 0x89 >; 2480 }; 2481 2482 sgx_fck { 2483 #clock-cells = < 0x00 >; 2484 compatible = "ti,composite-clock"; 2485 clocks = < 0x88 0x89 >; 2486 }; 2487 2488 sgx_ick@b10 { 2489 #clock-cells = < 0x00 >; 2490 compatible = "ti,wait-gate-clock"; 2491 clocks = < 0x3f >; 2492 reg = < 0xb10 >; 2493 ti,bit-shift = < 0x00 >; 2494 phandle = < 0xe0 >; 2495 }; 2496 2497 cpefuse_fck@a08 { 2498 #clock-cells = < 0x00 >; 2499 compatible = "ti,gate-clock"; 2500 clocks = < 0x1f >; 2501 reg = < 0xa08 >; 2502 ti,bit-shift = < 0x00 >; 2503 phandle = < 0xd4 >; 2504 }; 2505 2506 ts_fck@a08 { 2507 #clock-cells = < 0x00 >; 2508 compatible = "ti,gate-clock"; 2509 clocks = < 0x41 >; 2510 reg = < 0xa08 >; 2511 ti,bit-shift = < 0x01 >; 2512 phandle = < 0xd5 >; 2513 }; 2514 2515 usbtll_fck@a08 { 2516 #clock-cells = < 0x00 >; 2517 compatible = "ti,wait-gate-clock"; 2518 clocks = < 0x74 >; 2519 reg = < 0xa08 >; 2520 ti,bit-shift = < 0x02 >; 2521 phandle = < 0xd6 >; 2522 }; 2523 2524 usbtll_ick@a18 { 2525 #clock-cells = < 0x00 >; 2526 compatible = "ti,omap3-interface-clock"; 2527 clocks = < 0x4b >; 2528 reg = < 0xa18 >; 2529 ti,bit-shift = < 0x02 >; 2530 phandle = < 0xd7 >; 2531 }; 2532 2533 mmchs3_ick@a10 { 2534 #clock-cells = < 0x00 >; 2535 compatible = "ti,omap3-interface-clock"; 2536 clocks = < 0x4b >; 2537 reg = < 0xa10 >; 2538 ti,bit-shift = < 0x1e >; 2539 phandle = < 0xd8 >; 2540 }; 2541 2542 mmchs3_fck@a00 { 2543 #clock-cells = < 0x00 >; 2544 compatible = "ti,wait-gate-clock"; 2545 clocks = < 0x06 >; 2546 reg = < 0xa00 >; 2547 ti,bit-shift = < 0x1e >; 2548 phandle = < 0xd9 >; 2549 }; 2550 2551 dss1_alwon_fck_3430es2@e00 { 2552 #clock-cells = < 0x00 >; 2553 compatible = "ti,dss-gate-clock"; 2554 clocks = < 0x8a >; 2555 ti,bit-shift = < 0x00 >; 2556 reg = < 0xe00 >; 2557 ti,set-rate-parent; 2558 phandle = < 0xb3 >; 2559 }; 2560 2561 dss_ick_3430es2@e10 { 2562 #clock-cells = < 0x00 >; 2563 compatible = "ti,omap3-dss-interface-clock"; 2564 clocks = < 0x40 >; 2565 reg = < 0xe10 >; 2566 ti,bit-shift = < 0x00 >; 2567 phandle = < 0xb4 >; 2568 }; 2569 2570 usbhost_120m_fck@1400 { 2571 #clock-cells = < 0x00 >; 2572 compatible = "ti,gate-clock"; 2573 clocks = < 0x74 >; 2574 reg = < 0x1400 >; 2575 ti,bit-shift = < 0x01 >; 2576 phandle = < 0xe1 >; 2577 }; 2578 2579 usbhost_48m_fck@1400 { 2580 #clock-cells = < 0x00 >; 2581 compatible = "ti,dss-gate-clock"; 2582 clocks = < 0x31 >; 2583 reg = < 0x1400 >; 2584 ti,bit-shift = < 0x00 >; 2585 phandle = < 0xe2 >; 2586 }; 2587 2588 usbhost_ick@1410 { 2589 #clock-cells = < 0x00 >; 2590 compatible = "ti,omap3-dss-interface-clock"; 2591 clocks = < 0x40 >; 2592 reg = < 0x1410 >; 2593 ti,bit-shift = < 0x00 >; 2594 phandle = < 0xe3 >; 2595 }; 2596 }; 2597 2598 clockdomains { 2599 2600 core_l3_clkdm { 2601 compatible = "ti,clockdomain"; 2602 clocks = < 0x8b 0x8c >; 2603 }; 2604 2605 dpll3_clkdm { 2606 compatible = "ti,clockdomain"; 2607 clocks = < 0x1b >; 2608 }; 2609 2610 dpll1_clkdm { 2611 compatible = "ti,clockdomain"; 2612 clocks = < 0x02 >; 2613 }; 2614 2615 per_clkdm { 2616 compatible = "ti,clockdomain"; 2617 clocks = < 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 >; 2618 }; 2619 2620 emu_clkdm { 2621 compatible = "ti,clockdomain"; 2622 clocks = < 0x67 >; 2623 }; 2624 2625 dpll4_clkdm { 2626 compatible = "ti,clockdomain"; 2627 clocks = < 0x1d >; 2628 }; 2629 2630 wkup_clkdm { 2631 compatible = "ti,clockdomain"; 2632 clocks = < 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf >; 2633 }; 2634 2635 dss_clkdm { 2636 compatible = "ti,clockdomain"; 2637 clocks = < 0xb0 0xb1 0xb2 0xb3 0xb4 >; 2638 }; 2639 2640 core_l4_clkdm { 2641 compatible = "ti,clockdomain"; 2642 clocks = < 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 >; 2643 }; 2644 2645 cam_clkdm { 2646 compatible = "ti,clockdomain"; 2647 clocks = < 0xda 0xdb >; 2648 }; 2649 2650 iva2_clkdm { 2651 compatible = "ti,clockdomain"; 2652 clocks = < 0xdc >; 2653 }; 2654 2655 dpll2_clkdm { 2656 compatible = "ti,clockdomain"; 2657 clocks = < 0x6e >; 2658 }; 2659 2660 d2d_clkdm { 2661 compatible = "ti,clockdomain"; 2662 clocks = < 0xdd 0xde 0xdf >; 2663 }; 2664 2665 dpll5_clkdm { 2666 compatible = "ti,clockdomain"; 2667 clocks = < 0x80 >; 2668 }; 2669 2670 sgx_clkdm { 2671 compatible = "ti,clockdomain"; 2672 clocks = < 0xe0 >; 2673 }; 2674 2675 usbhost_clkdm { 2676 compatible = "ti,clockdomain"; 2677 clocks = < 0xe1 0xe2 0xe3 >; 2678 }; 2679 }; 2680 }; 2681 2682 counter@48320000 { 2683 compatible = "ti,omap-counter32k"; 2684 reg = < 0x48320000 0x20 >; 2685 ti,hwmods = "counter_32k"; 2686 }; 2687 2688 interrupt-controller@48200000 { 2689 compatible = "ti,omap3-intc"; 2690 interrupt-controller; 2691 #interrupt-cells = < 0x01 >; 2692 reg = < 0x48200000 0x1000 >; 2693 phandle = < 0x01 >; 2694 }; 2695 2696 dma-controller@48056000 { 2697 compatible = "ti,omap3630-sdma\0ti,omap3430-sdma"; 2698 reg = < 0x48056000 0x1000 >; 2699 interrupts = < 0x0c 0x0d 0x0e 0x0f >; 2700 #dma-cells = < 0x01 >; 2701 dma-channels = < 0x20 >; 2702 dma-requests = < 0x60 >; 2703 ti,hwmods = "dma"; 2704 phandle = < 0x13 >; 2705 }; 2706 2707 gpio@48310000 { 2708 compatible = "ti,omap3-gpio"; 2709 reg = < 0x48310000 0x200 >; 2710 interrupts = < 0x1d >; 2711 ti,hwmods = "gpio1"; 2712 ti,gpio-always-on; 2713 gpio-controller; 2714 #gpio-cells = < 0x02 >; 2715 interrupt-controller; 2716 #interrupt-cells = < 0x02 >; 2717 pinctrl-names = "default"; 2718 pinctrl-0 = < 0xe4 >; 2719 phandle = < 0x107 >; 2720 }; 2721 2722 gpio@49050000 { 2723 compatible = "ti,omap3-gpio"; 2724 reg = < 0x49050000 0x200 >; 2725 interrupts = < 0x1e >; 2726 ti,hwmods = "gpio2"; 2727 gpio-controller; 2728 #gpio-cells = < 0x02 >; 2729 interrupt-controller; 2730 #interrupt-cells = < 0x02 >; 2731 }; 2732 2733 gpio@49052000 { 2734 compatible = "ti,omap3-gpio"; 2735 reg = < 0x49052000 0x200 >; 2736 interrupts = < 0x1f >; 2737 ti,hwmods = "gpio3"; 2738 gpio-controller; 2739 #gpio-cells = < 0x02 >; 2740 interrupt-controller; 2741 #interrupt-cells = < 0x02 >; 2742 }; 2743 2744 gpio@49054000 { 2745 compatible = "ti,omap3-gpio"; 2746 reg = < 0x49054000 0x200 >; 2747 interrupts = < 0x20 >; 2748 ti,hwmods = "gpio4"; 2749 gpio-controller; 2750 #gpio-cells = < 0x02 >; 2751 interrupt-controller; 2752 #interrupt-cells = < 0x02 >; 2753 }; 2754 2755 gpio@49056000 { 2756 compatible = "ti,omap3-gpio"; 2757 reg = < 0x49056000 0x200 >; 2758 interrupts = < 0x21 >; 2759 ti,hwmods = "gpio5"; 2760 gpio-controller; 2761 #gpio-cells = < 0x02 >; 2762 interrupt-controller; 2763 #interrupt-cells = < 0x02 >; 2764 phandle = < 0x104 >; 2765 }; 2766 2767 gpio@49058000 { 2768 compatible = "ti,omap3-gpio"; 2769 reg = < 0x49058000 0x200 >; 2770 interrupts = < 0x22 >; 2771 ti,hwmods = "gpio6"; 2772 gpio-controller; 2773 #gpio-cells = < 0x02 >; 2774 interrupt-controller; 2775 #interrupt-cells = < 0x02 >; 2776 phandle = < 0x108 >; 2777 }; 2778 2779 serial@4806a000 { 2780 compatible = "ti,omap3-uart"; 2781 reg = < 0x4806a000 0x2000 >; 2782 interrupts-extended = < 0x01 0x48 >; 2783 dmas = < 0x13 0x31 0x13 0x32 >; 2784 dma-names = "tx\0rx"; 2785 ti,hwmods = "uart1"; 2786 clock-frequency = < 0x2dc6c00 >; 2787 }; 2788 2789 serial@4806c000 { 2790 compatible = "ti,omap3-uart"; 2791 reg = < 0x4806c000 0x400 >; 2792 interrupts-extended = < 0x01 0x49 >; 2793 dmas = < 0x13 0x33 0x13 0x34 >; 2794 dma-names = "tx\0rx"; 2795 ti,hwmods = "uart2"; 2796 clock-frequency = < 0x2dc6c00 >; 2797 }; 2798 2799 serial@49020000 { 2800 compatible = "ti,omap3-uart"; 2801 reg = < 0x49020000 0x400 >; 2802 interrupts-extended = < 0x01 0x4a 0xe5 0x16e >; 2803 dmas = < 0x13 0x35 0x13 0x36 >; 2804 dma-names = "tx\0rx"; 2805 ti,hwmods = "uart3"; 2806 clock-frequency = < 0x2dc6c00 >; 2807 pinctrl-names = "default"; 2808 pinctrl-0 = < 0xe6 >; 2809 }; 2810 2811 i2c@48070000 { 2812 compatible = "ti,omap3-i2c"; 2813 reg = < 0x48070000 0x80 >; 2814 interrupts = < 0x38 >; 2815 dmas = < 0x13 0x1b 0x13 0x1c >; 2816 dma-names = "tx\0rx"; 2817 #address-cells = < 0x01 >; 2818 #size-cells = < 0x00 >; 2819 ti,hwmods = "i2c1"; 2820 clock-frequency = < 0x27ac40 >; 2821 2822 twl@48 { 2823 reg = < 0x48 >; 2824 interrupts = < 0x07 >; 2825 interrupt-parent = < 0x01 >; 2826 compatible = "ti,twl4030"; 2827 interrupt-controller; 2828 #interrupt-cells = < 0x01 >; 2829 pinctrl-names = "default"; 2830 pinctrl-0 = < 0xe7 0xe8 >; 2831 2832 audio { 2833 compatible = "ti,twl4030-audio"; 2834 2835 codec { 2836 }; 2837 }; 2838 2839 rtc { 2840 compatible = "ti,twl4030-rtc"; 2841 interrupts = < 0x0b >; 2842 }; 2843 2844 bci { 2845 compatible = "ti,twl4030-bci"; 2846 interrupts = < 0x09 0x02 >; 2847 bci3v1-supply = < 0xe9 >; 2848 io-channels = < 0xea 0x0b >; 2849 io-channel-names = "vac"; 2850 }; 2851 2852 watchdog { 2853 compatible = "ti,twl4030-wdt"; 2854 }; 2855 2856 regulator-vaux1 { 2857 compatible = "ti,twl4030-vaux1"; 2858 }; 2859 2860 regulator-vaux2 { 2861 compatible = "ti,twl4030-vaux2"; 2862 regulator-name = "vdd_ehci"; 2863 regulator-min-microvolt = < 0x1b7740 >; 2864 regulator-max-microvolt = < 0x1b7740 >; 2865 regulator-always-on; 2866 }; 2867 2868 regulator-vaux3 { 2869 compatible = "ti,twl4030-vaux3"; 2870 }; 2871 2872 regulator-vaux4 { 2873 compatible = "ti,twl4030-vaux4"; 2874 }; 2875 2876 regulator-vdd1 { 2877 compatible = "ti,twl4030-vdd1"; 2878 regulator-min-microvolt = < 0x927c0 >; 2879 regulator-max-microvolt = < 0x162010 >; 2880 phandle = < 0x03 >; 2881 }; 2882 2883 regulator-vdac { 2884 compatible = "ti,twl4030-vdac"; 2885 regulator-min-microvolt = < 0x1b7740 >; 2886 regulator-max-microvolt = < 0x1b7740 >; 2887 phandle = < 0xf9 >; 2888 }; 2889 2890 regulator-vio { 2891 compatible = "ti,twl4030-vio"; 2892 }; 2893 2894 regulator-vintana1 { 2895 compatible = "ti,twl4030-vintana1"; 2896 }; 2897 2898 regulator-vintana2 { 2899 compatible = "ti,twl4030-vintana2"; 2900 }; 2901 2902 regulator-vintdig { 2903 compatible = "ti,twl4030-vintdig"; 2904 }; 2905 2906 regulator-vmmc1 { 2907 compatible = "ti,twl4030-vmmc1"; 2908 regulator-min-microvolt = < 0x1c3a90 >; 2909 regulator-max-microvolt = < 0x3010b0 >; 2910 phandle = < 0xee >; 2911 }; 2912 2913 regulator-vmmc2 { 2914 compatible = "ti,twl4030-vmmc2"; 2915 regulator-min-microvolt = < 0x1c3a90 >; 2916 regulator-max-microvolt = < 0x3010b0 >; 2917 }; 2918 2919 regulator-vusb1v5 { 2920 compatible = "ti,twl4030-vusb1v5"; 2921 phandle = < 0xeb >; 2922 }; 2923 2924 regulator-vusb1v8 { 2925 compatible = "ti,twl4030-vusb1v8"; 2926 phandle = < 0xec >; 2927 }; 2928 2929 regulator-vusb3v1 { 2930 compatible = "ti,twl4030-vusb3v1"; 2931 phandle = < 0xe9 >; 2932 }; 2933 2934 regulator-vpll1 { 2935 compatible = "ti,twl4030-vpll1"; 2936 }; 2937 2938 regulator-vpll2 { 2939 compatible = "ti,twl4030-vpll2"; 2940 regulator-min-microvolt = < 0x1b7740 >; 2941 regulator-max-microvolt = < 0x1b7740 >; 2942 regulator-always-on; 2943 }; 2944 2945 regulator-vsim { 2946 compatible = "ti,twl4030-vsim"; 2947 regulator-min-microvolt = < 0x1b7740 >; 2948 regulator-max-microvolt = < 0x2dc6c0 >; 2949 phandle = < 0xef >; 2950 }; 2951 2952 gpio { 2953 compatible = "ti,twl4030-gpio"; 2954 gpio-controller; 2955 #gpio-cells = < 0x02 >; 2956 interrupt-controller; 2957 #interrupt-cells = < 0x01 >; 2958 ti,use-leds; 2959 ti,pullups = < 0x02 >; 2960 ti,pulldowns = < 0x3a1c4 >; 2961 phandle = < 0x103 >; 2962 }; 2963 2964 twl4030-usb { 2965 compatible = "ti,twl4030-usb"; 2966 interrupts = < 0x0a 0x04 >; 2967 usb1v5-supply = < 0xeb >; 2968 usb1v8-supply = < 0xec >; 2969 usb3v1-supply = < 0xe9 >; 2970 usb_mode = < 0x01 >; 2971 #phy-cells = < 0x00 >; 2972 phandle = < 0xf7 >; 2973 }; 2974 2975 pwm { 2976 compatible = "ti,twl4030-pwm"; 2977 #pwm-cells = < 0x02 >; 2978 }; 2979 2980 pwmled { 2981 compatible = "ti,twl4030-pwmled"; 2982 #pwm-cells = < 0x02 >; 2983 }; 2984 2985 pwrbutton { 2986 compatible = "ti,twl4030-pwrbutton"; 2987 interrupts = < 0x08 >; 2988 }; 2989 2990 keypad { 2991 compatible = "ti,twl4030-keypad"; 2992 interrupts = < 0x01 >; 2993 keypad,num-rows = < 0x08 >; 2994 keypad,num-columns = < 0x08 >; 2995 }; 2996 2997 madc { 2998 compatible = "ti,twl4030-madc"; 2999 interrupts = < 0x03 >; 3000 #io-channel-cells = < 0x01 >; 3001 phandle = < 0xea >; 3002 }; 3003 }; 3004 }; 3005 3006 i2c@48072000 { 3007 compatible = "ti,omap3-i2c"; 3008 reg = < 0x48072000 0x80 >; 3009 interrupts = < 0x39 >; 3010 dmas = < 0x13 0x1d 0x13 0x1e >; 3011 dma-names = "tx\0rx"; 3012 #address-cells = < 0x01 >; 3013 #size-cells = < 0x00 >; 3014 ti,hwmods = "i2c2"; 3015 }; 3016 3017 i2c@48060000 { 3018 compatible = "ti,omap3-i2c"; 3019 reg = < 0x48060000 0x80 >; 3020 interrupts = < 0x3d >; 3021 dmas = < 0x13 0x19 0x13 0x1a >; 3022 dma-names = "tx\0rx"; 3023 #address-cells = < 0x01 >; 3024 #size-cells = < 0x00 >; 3025 ti,hwmods = "i2c3"; 3026 clock-frequency = < 0x186a0 >; 3027 phandle = < 0x10c >; 3028 }; 3029 3030 mailbox@48094000 { 3031 compatible = "ti,omap3-mailbox"; 3032 ti,hwmods = "mailbox"; 3033 reg = < 0x48094000 0x200 >; 3034 interrupts = < 0x1a >; 3035 #mbox-cells = < 0x01 >; 3036 ti,mbox-num-users = < 0x02 >; 3037 ti,mbox-num-fifos = < 0x02 >; 3038 3039 dsp { 3040 ti,mbox-tx = < 0x00 0x00 0x00 >; 3041 ti,mbox-rx = < 0x01 0x00 0x00 >; 3042 }; 3043 }; 3044 3045 spi@48098000 { 3046 compatible = "ti,omap2-mcspi"; 3047 reg = < 0x48098000 0x100 >; 3048 interrupts = < 0x41 >; 3049 #address-cells = < 0x01 >; 3050 #size-cells = < 0x00 >; 3051 ti,hwmods = "mcspi1"; 3052 ti,spi-num-cs = < 0x04 >; 3053 dmas = < 0x13 0x23 0x13 0x24 0x13 0x25 0x13 0x26 0x13 0x27 0x13 0x28 0x13 0x29 0x13 0x2a >; 3054 dma-names = "tx0\0rx0\0tx1\0rx1\0tx2\0rx2\0tx3\0rx3"; 3055 }; 3056 3057 spi@4809a000 { 3058 compatible = "ti,omap2-mcspi"; 3059 reg = < 0x4809a000 0x100 >; 3060 interrupts = < 0x42 >; 3061 #address-cells = < 0x01 >; 3062 #size-cells = < 0x00 >; 3063 ti,hwmods = "mcspi2"; 3064 ti,spi-num-cs = < 0x02 >; 3065 dmas = < 0x13 0x2b 0x13 0x2c 0x13 0x2d 0x13 0x2e >; 3066 dma-names = "tx0\0rx0\0tx1\0rx1"; 3067 }; 3068 3069 spi@480b8000 { 3070 compatible = "ti,omap2-mcspi"; 3071 reg = < 0x480b8000 0x100 >; 3072 interrupts = < 0x5b >; 3073 #address-cells = < 0x01 >; 3074 #size-cells = < 0x00 >; 3075 ti,hwmods = "mcspi3"; 3076 ti,spi-num-cs = < 0x02 >; 3077 dmas = < 0x13 0x0f 0x13 0x10 0x13 0x17 0x13 0x18 >; 3078 dma-names = "tx0\0rx0\0tx1\0rx1"; 3079 }; 3080 3081 spi@480ba000 { 3082 compatible = "ti,omap2-mcspi"; 3083 reg = < 0x480ba000 0x100 >; 3084 interrupts = < 0x30 >; 3085 #address-cells = < 0x01 >; 3086 #size-cells = < 0x00 >; 3087 ti,hwmods = "mcspi4"; 3088 ti,spi-num-cs = < 0x01 >; 3089 dmas = < 0x13 0x46 0x13 0x47 >; 3090 dma-names = "tx0\0rx0"; 3091 }; 3092 3093 1w@480b2000 { 3094 compatible = "ti,omap3-1w"; 3095 reg = < 0x480b2000 0x1000 >; 3096 interrupts = < 0x3a >; 3097 ti,hwmods = "hdq1w"; 3098 }; 3099 3100 mmc@4809c000 { 3101 compatible = "ti,omap3-hsmmc"; 3102 reg = < 0x4809c000 0x200 >; 3103 interrupts = < 0x53 >; 3104 ti,hwmods = "mmc1"; 3105 ti,dual-volt; 3106 dmas = < 0x13 0x3d 0x13 0x3e >; 3107 dma-names = "tx\0rx"; 3108 pbias-supply = < 0xed >; 3109 vmmc-supply = < 0xee >; 3110 vqmmc-supply = < 0xef >; 3111 bus-width = < 0x08 >; 3112 }; 3113 3114 mmc@480b4000 { 3115 compatible = "ti,omap3-hsmmc"; 3116 reg = < 0x480b4000 0x200 >; 3117 interrupts = < 0x56 >; 3118 ti,hwmods = "mmc2"; 3119 dmas = < 0x13 0x2f 0x13 0x30 >; 3120 dma-names = "tx\0rx"; 3121 status = "disabled"; 3122 }; 3123 3124 mmc@480ad000 { 3125 compatible = "ti,omap3-hsmmc"; 3126 reg = < 0x480ad000 0x200 >; 3127 interrupts = < 0x5e >; 3128 ti,hwmods = "mmc3"; 3129 dmas = < 0x13 0x4d 0x13 0x4e >; 3130 dma-names = "tx\0rx"; 3131 status = "disabled"; 3132 }; 3133 3134 mmu@480bd400 { 3135 #iommu-cells = < 0x00 >; 3136 compatible = "ti,omap2-iommu"; 3137 reg = < 0x480bd400 0x80 >; 3138 interrupts = < 0x18 >; 3139 ti,hwmods = "mmu_isp"; 3140 ti,#tlb-entries = < 0x08 >; 3141 phandle = < 0xff >; 3142 }; 3143 3144 mmu@5d000000 { 3145 #iommu-cells = < 0x00 >; 3146 compatible = "ti,omap2-iommu"; 3147 reg = < 0x5d000000 0x80 >; 3148 interrupts = < 0x1c >; 3149 ti,hwmods = "mmu_iva"; 3150 status = "disabled"; 3151 }; 3152 3153 wdt@48314000 { 3154 compatible = "ti,omap3-wdt"; 3155 reg = < 0x48314000 0x80 >; 3156 ti,hwmods = "wd_timer2"; 3157 }; 3158 3159 mcbsp@48074000 { 3160 compatible = "ti,omap3-mcbsp"; 3161 reg = < 0x48074000 0xff >; 3162 reg-names = "mpu"; 3163 interrupts = < 0x10 0x3b 0x3c >; 3164 interrupt-names = "common\0tx\0rx"; 3165 ti,buffer-size = < 0x80 >; 3166 ti,hwmods = "mcbsp1"; 3167 dmas = < 0x13 0x1f 0x13 0x20 >; 3168 dma-names = "tx\0rx"; 3169 clocks = < 0xf0 >; 3170 clock-names = "fck"; 3171 status = "disabled"; 3172 }; 3173 3174 mcbsp@49022000 { 3175 compatible = "ti,omap3-mcbsp"; 3176 reg = < 0x49022000 0xff 0x49028000 0xff >; 3177 reg-names = "mpu\0sidetone"; 3178 interrupts = < 0x11 0x3e 0x3f 0x04 >; 3179 interrupt-names = "common\0tx\0rx\0sidetone"; 3180 ti,buffer-size = < 0x500 >; 3181 ti,hwmods = "mcbsp2\0mcbsp2_sidetone"; 3182 dmas = < 0x13 0x21 0x13 0x22 >; 3183 dma-names = "tx\0rx"; 3184 clocks = < 0xf1 0xa4 >; 3185 clock-names = "fck\0ick"; 3186 status = "okay"; 3187 phandle = < 0x106 >; 3188 }; 3189 3190 mcbsp@49024000 { 3191 compatible = "ti,omap3-mcbsp"; 3192 reg = < 0x49024000 0xff 0x4902a000 0xff >; 3193 reg-names = "mpu\0sidetone"; 3194 interrupts = < 0x16 0x59 0x5a 0x05 >; 3195 interrupt-names = "common\0tx\0rx\0sidetone"; 3196 ti,buffer-size = < 0x80 >; 3197 ti,hwmods = "mcbsp3\0mcbsp3_sidetone"; 3198 dmas = < 0x13 0x11 0x13 0x12 >; 3199 dma-names = "tx\0rx"; 3200 clocks = < 0xf2 0xa5 >; 3201 clock-names = "fck\0ick"; 3202 status = "disabled"; 3203 }; 3204 3205 mcbsp@49026000 { 3206 compatible = "ti,omap3-mcbsp"; 3207 reg = < 0x49026000 0xff >; 3208 reg-names = "mpu"; 3209 interrupts = < 0x17 0x36 0x37 >; 3210 interrupt-names = "common\0tx\0rx"; 3211 ti,buffer-size = < 0x80 >; 3212 ti,hwmods = "mcbsp4"; 3213 dmas = < 0x13 0x13 0x13 0x14 >; 3214 dma-names = "tx\0rx"; 3215 clocks = < 0xf3 >; 3216 clock-names = "fck"; 3217 #sound-dai-cells = < 0x00 >; 3218 status = "disabled"; 3219 }; 3220 3221 mcbsp@48096000 { 3222 compatible = "ti,omap3-mcbsp"; 3223 reg = < 0x48096000 0xff >; 3224 reg-names = "mpu"; 3225 interrupts = < 0x1b 0x51 0x52 >; 3226 interrupt-names = "common\0tx\0rx"; 3227 ti,buffer-size = < 0x80 >; 3228 ti,hwmods = "mcbsp5"; 3229 dmas = < 0x13 0x15 0x13 0x16 >; 3230 dma-names = "tx\0rx"; 3231 clocks = < 0xf4 >; 3232 clock-names = "fck"; 3233 status = "disabled"; 3234 }; 3235 3236 sham@480c3000 { 3237 compatible = "ti,omap3-sham"; 3238 ti,hwmods = "sham"; 3239 reg = < 0x480c3000 0x64 >; 3240 interrupts = < 0x31 >; 3241 dmas = < 0x13 0x45 >; 3242 dma-names = "rx"; 3243 }; 3244 3245 timer@48318000 { 3246 compatible = "ti,omap3430-timer"; 3247 reg = < 0x48318000 0x400 >; 3248 interrupts = < 0x25 >; 3249 ti,hwmods = "timer1"; 3250 ti,timer-alwon; 3251 }; 3252 3253 timer@49032000 { 3254 compatible = "ti,omap3430-timer"; 3255 reg = < 0x49032000 0x400 >; 3256 interrupts = < 0x26 >; 3257 ti,hwmods = "timer2"; 3258 }; 3259 3260 timer@49034000 { 3261 compatible = "ti,omap3430-timer"; 3262 reg = < 0x49034000 0x400 >; 3263 interrupts = < 0x27 >; 3264 ti,hwmods = "timer3"; 3265 }; 3266 3267 timer@49036000 { 3268 compatible = "ti,omap3430-timer"; 3269 reg = < 0x49036000 0x400 >; 3270 interrupts = < 0x28 >; 3271 ti,hwmods = "timer4"; 3272 }; 3273 3274 timer@49038000 { 3275 compatible = "ti,omap3430-timer"; 3276 reg = < 0x49038000 0x400 >; 3277 interrupts = < 0x29 >; 3278 ti,hwmods = "timer5"; 3279 ti,timer-dsp; 3280 }; 3281 3282 timer@4903a000 { 3283 compatible = "ti,omap3430-timer"; 3284 reg = < 0x4903a000 0x400 >; 3285 interrupts = < 0x2a >; 3286 ti,hwmods = "timer6"; 3287 ti,timer-dsp; 3288 }; 3289 3290 timer@4903c000 { 3291 compatible = "ti,omap3430-timer"; 3292 reg = < 0x4903c000 0x400 >; 3293 interrupts = < 0x2b >; 3294 ti,hwmods = "timer7"; 3295 ti,timer-dsp; 3296 }; 3297 3298 timer@4903e000 { 3299 compatible = "ti,omap3430-timer"; 3300 reg = < 0x4903e000 0x400 >; 3301 interrupts = < 0x2c >; 3302 ti,hwmods = "timer8"; 3303 ti,timer-pwm; 3304 ti,timer-dsp; 3305 }; 3306 3307 timer@49040000 { 3308 compatible = "ti,omap3430-timer"; 3309 reg = < 0x49040000 0x400 >; 3310 interrupts = < 0x2d >; 3311 ti,hwmods = "timer9"; 3312 ti,timer-pwm; 3313 }; 3314 3315 timer@48086000 { 3316 compatible = "ti,omap3430-timer"; 3317 reg = < 0x48086000 0x400 >; 3318 interrupts = < 0x2e >; 3319 ti,hwmods = "timer10"; 3320 ti,timer-pwm; 3321 }; 3322 3323 timer@48088000 { 3324 compatible = "ti,omap3430-timer"; 3325 reg = < 0x48088000 0x400 >; 3326 interrupts = < 0x2f >; 3327 ti,hwmods = "timer11"; 3328 ti,timer-pwm; 3329 }; 3330 3331 timer@48304000 { 3332 compatible = "ti,omap3430-timer"; 3333 reg = < 0x48304000 0x400 >; 3334 interrupts = < 0x5f >; 3335 ti,hwmods = "timer12"; 3336 ti,timer-alwon; 3337 ti,timer-secure; 3338 }; 3339 3340 usbhstll@48062000 { 3341 compatible = "ti,usbhs-tll"; 3342 reg = < 0x48062000 0x1000 >; 3343 interrupts = < 0x4e >; 3344 ti,hwmods = "usb_tll_hs"; 3345 }; 3346 3347 usbhshost@48064000 { 3348 compatible = "ti,usbhs-host"; 3349 reg = < 0x48064000 0x400 >; 3350 ti,hwmods = "usb_host_hs"; 3351 #address-cells = < 0x01 >; 3352 #size-cells = < 0x01 >; 3353 ranges; 3354 port2-mode = "ehci-phy"; 3355 3356 ohci@48064400 { 3357 compatible = "ti,ohci-omap3"; 3358 reg = < 0x48064400 0x400 >; 3359 interrupts = < 0x4c >; 3360 remote-wakeup-connected; 3361 }; 3362 3363 ehci@48064800 { 3364 compatible = "ti,ehci-omap"; 3365 reg = < 0x48064800 0x400 >; 3366 interrupts = < 0x4d >; 3367 phys = < 0x00 0xf5 >; 3368 }; 3369 }; 3370 3371 gpmc@6e000000 { 3372 compatible = "ti,omap3430-gpmc"; 3373 ti,hwmods = "gpmc"; 3374 reg = < 0x6e000000 0x2d0 >; 3375 interrupts = < 0x14 >; 3376 dmas = < 0x13 0x04 >; 3377 dma-names = "rxtx"; 3378 gpmc,num-cs = < 0x08 >; 3379 gpmc,num-waitpins = < 0x04 >; 3380 #address-cells = < 0x02 >; 3381 #size-cells = < 0x01 >; 3382 interrupt-controller; 3383 #interrupt-cells = < 0x02 >; 3384 gpio-controller; 3385 #gpio-cells = < 0x02 >; 3386 status = "ok"; 3387 ranges = < 0x00 0x00 0x30000000 0x1000000 >; 3388 phandle = < 0xf6 >; 3389 3390 nand@0,0 { 3391 compatible = "ti,omap2-nand"; 3392 reg = < 0x00 0x00 0x04 >; 3393 interrupt-parent = < 0xf6 >; 3394 interrupts = < 0x00 0x00 0x01 0x00 >; 3395 ti,nand-ecc-opt = "ham1"; 3396 rb-gpios = < 0xf6 0x00 0x00 >; 3397 nand-bus-width = < 0x10 >; 3398 #address-cells = < 0x01 >; 3399 #size-cells = < 0x01 >; 3400 gpmc,device-width = < 0x02 >; 3401 gpmc,cs-on-ns = < 0x00 >; 3402 gpmc,cs-rd-off-ns = < 0x24 >; 3403 gpmc,cs-wr-off-ns = < 0x24 >; 3404 gpmc,adv-on-ns = < 0x06 >; 3405 gpmc,adv-rd-off-ns = < 0x18 >; 3406 gpmc,adv-wr-off-ns = < 0x24 >; 3407 gpmc,oe-on-ns = < 0x06 >; 3408 gpmc,oe-off-ns = < 0x30 >; 3409 gpmc,we-on-ns = < 0x06 >; 3410 gpmc,we-off-ns = < 0x1e >; 3411 gpmc,rd-cycle-ns = < 0x48 >; 3412 gpmc,wr-cycle-ns = < 0x48 >; 3413 gpmc,access-ns = < 0x36 >; 3414 gpmc,wr-access-ns = < 0x1e >; 3415 3416 partition@0 { 3417 label = "X-Loader"; 3418 reg = < 0x00 0x80000 >; 3419 }; 3420 3421 partition@80000 { 3422 label = "U-Boot"; 3423 reg = < 0x80000 0x1e0000 >; 3424 }; 3425 3426 partition@1c0000 { 3427 label = "U-Boot Env"; 3428 reg = < 0x260000 0x20000 >; 3429 }; 3430 3431 partition@280000 { 3432 label = "Kernel"; 3433 reg = < 0x280000 0x400000 >; 3434 }; 3435 3436 partition@780000 { 3437 label = "Filesystem"; 3438 reg = < 0x680000 0xf980000 >; 3439 }; 3440 }; 3441 }; 3442 3443 usb_otg_hs@480ab000 { 3444 compatible = "ti,omap3-musb"; 3445 reg = < 0x480ab000 0x1000 >; 3446 interrupts = < 0x5c 0x5d >; 3447 interrupt-names = "mc\0dma"; 3448 ti,hwmods = "usb_otg_hs"; 3449 multipoint = < 0x01 >; 3450 num-eps = < 0x10 >; 3451 ram-bits = < 0x0c >; 3452 interface-type = < 0x00 >; 3453 usb-phy = < 0xf7 >; 3454 phys = < 0xf7 >; 3455 phy-names = "usb2-phy"; 3456 mode = < 0x03 >; 3457 power = < 0x32 >; 3458 }; 3459 3460 dss@48050000 { 3461 compatible = "ti,omap3-dss"; 3462 reg = < 0x48050000 0x200 >; 3463 status = "ok"; 3464 ti,hwmods = "dss_core"; 3465 clocks = < 0xb3 >; 3466 clock-names = "fck"; 3467 #address-cells = < 0x01 >; 3468 #size-cells = < 0x01 >; 3469 ranges; 3470 pinctrl-names = "default"; 3471 pinctrl-0 = < 0xf8 >; 3472 3473 dispc@48050400 { 3474 compatible = "ti,omap3-dispc"; 3475 reg = < 0x48050400 0x400 >; 3476 interrupts = < 0x19 >; 3477 ti,hwmods = "dss_dispc"; 3478 clocks = < 0xb3 >; 3479 clock-names = "fck"; 3480 }; 3481 3482 encoder@4804fc00 { 3483 compatible = "ti,omap3-dsi"; 3484 reg = < 0x4804fc00 0x200 0x4804fe00 0x40 0x4804ff00 0x20 >; 3485 reg-names = "proto\0phy\0pll"; 3486 interrupts = < 0x19 >; 3487 status = "disabled"; 3488 ti,hwmods = "dss_dsi1"; 3489 clocks = < 0xb3 0xb2 >; 3490 clock-names = "fck\0sys_clk"; 3491 }; 3492 3493 encoder@48050800 { 3494 compatible = "ti,omap3-rfbi"; 3495 reg = < 0x48050800 0x100 >; 3496 status = "disabled"; 3497 ti,hwmods = "dss_rfbi"; 3498 clocks = < 0xb3 0xb4 >; 3499 clock-names = "fck\0ick"; 3500 }; 3501 3502 encoder@48050c00 { 3503 compatible = "ti,omap3-venc"; 3504 reg = < 0x48050c00 0x100 >; 3505 status = "ok"; 3506 ti,hwmods = "dss_venc"; 3507 clocks = < 0xb0 >; 3508 clock-names = "fck"; 3509 vdda-supply = < 0xf9 >; 3510 3511 port { 3512 3513 endpoint { 3514 remote-endpoint = < 0xfa >; 3515 ti,channels = < 0x02 >; 3516 phandle = < 0x10e >; 3517 }; 3518 }; 3519 }; 3520 3521 port { 3522 3523 endpoint { 3524 remote-endpoint = < 0xfb >; 3525 data-lines = < 0x18 >; 3526 phandle = < 0x10a >; 3527 }; 3528 }; 3529 }; 3530 3531 ssi-controller@48058000 { 3532 compatible = "ti,omap3-ssi"; 3533 ti,hwmods = "ssi"; 3534 status = "ok"; 3535 reg = < 0x48058000 0x1000 0x48059000 0x1000 >; 3536 reg-names = "sys\0gdd"; 3537 interrupts = < 0x47 >; 3538 interrupt-names = "gdd_mpu"; 3539 #address-cells = < 0x01 >; 3540 #size-cells = < 0x01 >; 3541 ranges; 3542 clocks = < 0x72 0xfc 0xfd >; 3543 clock-names = "ssi_ssr_fck\0ssi_sst_fck\0ssi_ick"; 3544 3545 ssi-port@4805a000 { 3546 compatible = "ti,omap3-ssi-port"; 3547 reg = < 0x4805a000 0x800 0x4805a800 0x800 >; 3548 reg-names = "tx\0rx"; 3549 interrupts = < 0x43 0x44 >; 3550 }; 3551 3552 ssi-port@4805b000 { 3553 compatible = "ti,omap3-ssi-port"; 3554 reg = < 0x4805b000 0x800 0x4805b800 0x800 >; 3555 reg-names = "tx\0rx"; 3556 interrupts = < 0x45 0x46 >; 3557 }; 3558 }; 3559 3560 pinmux@480025d8 { 3561 compatible = "ti,omap3-padconf\0pinctrl-single"; 3562 reg = < 0x480025d8 0x24 >; 3563 #address-cells = < 0x01 >; 3564 #size-cells = < 0x00 >; 3565 #pinctrl-cells = < 0x01 >; 3566 #interrupt-cells = < 0x01 >; 3567 interrupt-controller; 3568 pinctrl-single,register-width = < 0x10 >; 3569 pinctrl-single,function-mask = < 0xff1f >; 3570 pinctrl-names = "default"; 3571 pinctrl-0 = < 0xfe >; 3572 3573 pinmux_hsusb2_2_pins { 3574 pinctrl-single,pins = < 0x18 0x03 0x1a 0x03 0x1c 0x10b 0x1e 0x10b 0x20 0x10b 0x22 0x10b >; 3575 phandle = < 0xfe >; 3576 }; 3577 }; 3578 3579 isp@480bc000 { 3580 compatible = "ti,omap3-isp"; 3581 reg = < 0x480bc000 0x12fc 0x480bd800 0x17c >; 3582 interrupts = < 0x18 >; 3583 iommus = < 0xff >; 3584 syscon = < 0x05 0x6c >; 3585 ti,phy-type = < 0x00 >; 3586 #clock-cells = < 0x01 >; 3587 3588 ports { 3589 #address-cells = < 0x01 >; 3590 #size-cells = < 0x00 >; 3591 }; 3592 }; 3593 3594 bandgap@48002524 { 3595 reg = < 0x48002524 0x04 >; 3596 compatible = "ti,omap34xx-bandgap"; 3597 #thermal-sensor-cells = < 0x00 >; 3598 phandle = < 0x102 >; 3599 }; 3600 3601 target-module@480cb000 { 3602 compatible = "ti,sysc-omap3430-sr\0ti,sysc"; 3603 ti,hwmods = "smartreflex_core"; 3604 reg = < 0x480cb024 0x04 >; 3605 reg-names = "sysc"; 3606 ti,sysc-mask = < 0x300 >; 3607 clocks = < 0x100 >; 3608 clock-names = "fck"; 3609 #address-cells = < 0x01 >; 3610 #size-cells = < 0x01 >; 3611 ranges = < 0x00 0x480cb000 0x1000 >; 3612 3613 smartreflex@0 { 3614 compatible = "ti,omap3-smartreflex-core"; 3615 reg = < 0x00 0x400 >; 3616 interrupts = < 0x13 >; 3617 }; 3618 }; 3619 3620 target-module@480c9000 { 3621 compatible = "ti,sysc-omap3430-sr\0ti,sysc"; 3622 ti,hwmods = "smartreflex_mpu_iva"; 3623 reg = < 0x480c9024 0x04 >; 3624 reg-names = "sysc"; 3625 ti,sysc-mask = < 0x300 >; 3626 clocks = < 0x101 >; 3627 clock-names = "fck"; 3628 #address-cells = < 0x01 >; 3629 #size-cells = < 0x01 >; 3630 ranges = < 0x00 0x480c9000 0x1000 >; 3631 3632 smartreflex@480c9000 { 3633 compatible = "ti,omap3-smartreflex-mpu-iva"; 3634 reg = < 0x00 0x400 >; 3635 interrupts = < 0x12 >; 3636 }; 3637 }; 3638 }; 3639 3640 thermal-zones { 3641 3642 cpu_thermal { 3643 polling-delay-passive = < 0xfa >; 3644 polling-delay = < 0x3e8 >; 3645 coefficients = < 0x00 0x4e20 >; 3646 thermal-sensors = < 0x102 0x00 >; 3647 }; 3648 }; 3649 3650 memory@80000000 { 3651 device_type = "memory"; 3652 reg = < 0x80000000 0x10000000 >; 3653 }; 3654 3655 leds { 3656 compatible = "gpio-leds"; 3657 3658 pmu_stat { 3659 label = "beagleboard::pmu_stat"; 3660 gpios = < 0x103 0x13 0x00 >; 3661 }; 3662 3663 heartbeat { 3664 label = "beagleboard::usr0"; 3665 gpios = < 0x104 0x16 0x00 >; 3666 linux,default-trigger = "heartbeat"; 3667 }; 3668 3669 mmc { 3670 label = "beagleboard::usr1"; 3671 gpios = < 0x104 0x15 0x00 >; 3672 linux,default-trigger = "mmc0"; 3673 }; 3674 }; 3675 3676 hsusb2_power_reg { 3677 compatible = "regulator-fixed"; 3678 regulator-name = "hsusb2_vbus"; 3679 regulator-min-microvolt = < 0x325aa0 >; 3680 regulator-max-microvolt = < 0x325aa0 >; 3681 gpio = < 0x103 0x12 0x00 >; 3682 startup-delay-us = < 0x11170 >; 3683 phandle = < 0x105 >; 3684 }; 3685 3686 hsusb2_phy { 3687 compatible = "usb-nop-xceiv"; 3688 reset-gpios = < 0x104 0x13 0x01 >; 3689 vcc-supply = < 0x105 >; 3690 #phy-cells = < 0x00 >; 3691 phandle = < 0xf5 >; 3692 }; 3693 3694 sound { 3695 compatible = "ti,omap-twl4030"; 3696 ti,model = "omap3beagle"; 3697 ti,mcbsp = < 0x106 >; 3698 }; 3699 3700 gpio_keys { 3701 compatible = "gpio-keys"; 3702 3703 user { 3704 label = "user"; 3705 gpios = < 0x107 0x07 0x00 >; 3706 linux,code = < 0x114 >; 3707 wakeup-source; 3708 }; 3709 }; 3710 3711 encoder0 { 3712 compatible = "ti,tfp410"; 3713 powerdown-gpios = < 0x108 0x0a 0x01 >; 3714 pinctrl-names = "default"; 3715 pinctrl-0 = < 0x109 >; 3716 3717 ports { 3718 #address-cells = < 0x01 >; 3719 #size-cells = < 0x00 >; 3720 3721 port@0 { 3722 reg = < 0x00 >; 3723 3724 endpoint { 3725 remote-endpoint = < 0x10a >; 3726 phandle = < 0xfb >; 3727 }; 3728 }; 3729 3730 port@1 { 3731 reg = < 0x01 >; 3732 3733 endpoint { 3734 remote-endpoint = < 0x10b >; 3735 phandle = < 0x10d >; 3736 }; 3737 }; 3738 }; 3739 }; 3740 3741 connector0 { 3742 compatible = "dvi-connector"; 3743 label = "dvi"; 3744 digital; 3745 ddc-i2c-bus = < 0x10c >; 3746 3747 port { 3748 3749 endpoint { 3750 remote-endpoint = < 0x10d >; 3751 phandle = < 0x10b >; 3752 }; 3753 }; 3754 }; 3755 3756 connector1 { 3757 compatible = "svideo-connector"; 3758 label = "tv"; 3759 3760 port { 3761 3762 endpoint { 3763 remote-endpoint = < 0x10e >; 3764 phandle = < 0xfa >; 3765 }; 3766 }; 3767 }; 3768 3769 etb@540000000 { 3770 compatible = "arm,coresight-etb10\0arm,primecell"; 3771 reg = < 0x5401b000 0x1000 >; 3772 clocks = < 0x67 >; 3773 clock-names = "apb_pclk"; 3774 3775 in-ports { 3776 3777 port { 3778 3779 endpoint { 3780 remote-endpoint = < 0x10f >; 3781 phandle = < 0x110 >; 3782 }; 3783 }; 3784 }; 3785 }; 3786 3787 etm@54010000 { 3788 compatible = "arm,coresight-etm3x\0arm,primecell"; 3789 reg = < 0x54010000 0x1000 >; 3790 clocks = < 0x67 >; 3791 clock-names = "apb_pclk"; 3792 3793 out-ports { 3794 3795 port { 3796 3797 endpoint { 3798 remote-endpoint = < 0x110 >; 3799 phandle = < 0x10f >; 3800 }; 3801 }; 3802 }; 3803 }; 3804}; 3805