1/*
2 * Copyright Linux Kernel Team
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * This file is derived from an intermediate build stage of the
7 * Linux kernel. The licenses of all input files to this process
8 * are compatible with GPL-2.0-only.
9 */
10
11/dts-v1/;
12
13/ {
14	#address-cells = < 0x01 >;
15	#size-cells = < 0x01 >;
16	model = "Buglabs i.MX31 Bug 1.x";
17	compatible = "buglabs,imx31-bug\0fsl,imx31";
18
19	chosen {
20	};
21
22	memory {
23		device_type = "memory";
24	};
25
26	aliases {
27		gpio0 = "/soc/aips@53f00000/gpio@53fcc000";
28		gpio1 = "/soc/aips@53f00000/gpio@53fd0000";
29		gpio2 = "/soc/aips@53f00000/gpio@53fa4000";
30		i2c0 = "/soc/aips@43f00000/i2c@43f80000";
31		i2c1 = "/soc/aips@43f00000/i2c@43f98000";
32		i2c2 = "/soc/aips@43f00000/i2c@43f84000";
33		serial0 = "/soc/aips@43f00000/serial@43f90000";
34		serial1 = "/soc/aips@43f00000/serial@43f94000";
35		serial2 = "/soc/spba@50000000/serial@5000c000";
36		serial3 = "/soc/aips@43f00000/serial@43fb0000";
37		serial4 = "/soc/aips@43f00000/serial@43fb4000";
38		spi0 = "/soc/aips@43f00000/spi@43fa4000";
39		spi1 = "/soc/spba@50000000/spi@50010000";
40		spi2 = "/soc/aips@53f00000/spi@53f84000";
41	};
42
43	cpus {
44		#address-cells = < 0x01 >;
45		#size-cells = < 0x00 >;
46
47		cpu@0 {
48			compatible = "arm,arm1136jf-s";
49			device_type = "cpu";
50			reg = < 0x00 >;
51		};
52	};
53
54	interrupt-controller@68000000 {
55		compatible = "fsl,imx31-avic\0fsl,avic";
56		interrupt-controller;
57		#interrupt-cells = < 0x01 >;
58		reg = < 0x68000000 0x100000 >;
59		phandle = < 0x01 >;
60	};
61
62	soc {
63		#address-cells = < 0x01 >;
64		#size-cells = < 0x01 >;
65		compatible = "simple-bus";
66		interrupt-parent = < 0x01 >;
67		ranges;
68
69		iram@1fffc000 {
70			compatible = "mmio-sram";
71			reg = < 0x1fffc000 0x4000 >;
72			#address-cells = < 0x01 >;
73			#size-cells = < 0x01 >;
74			ranges = < 0x00 0x1fffc000 0x4000 >;
75		};
76
77		aips@43f00000 {
78			compatible = "fsl,aips-bus\0simple-bus";
79			#address-cells = < 0x01 >;
80			#size-cells = < 0x01 >;
81			reg = < 0x43f00000 0x100000 >;
82			ranges;
83
84			i2c@43f80000 {
85				compatible = "fsl,imx31-i2c\0fsl,imx21-i2c";
86				reg = < 0x43f80000 0x4000 >;
87				interrupts = < 0x0a >;
88				clocks = < 0x02 0x21 >;
89				#address-cells = < 0x01 >;
90				#size-cells = < 0x00 >;
91				status = "disabled";
92			};
93
94			i2c@43f84000 {
95				compatible = "fsl,imx31-i2c\0fsl,imx21-i2c";
96				reg = < 0x43f84000 0x4000 >;
97				interrupts = < 0x03 >;
98				clocks = < 0x02 0x23 >;
99				#address-cells = < 0x01 >;
100				#size-cells = < 0x00 >;
101				status = "disabled";
102			};
103
104			ata@43f8c000 {
105				compatible = "fsl,imx31-pata\0fsl,imx27-pata";
106				reg = < 0x43f8c000 0x4000 >;
107				interrupts = < 0x0f >;
108				clocks = < 0x02 0x1a >;
109				status = "disabled";
110			};
111
112			serial@43f90000 {
113				compatible = "fsl,imx31-uart\0fsl,imx21-uart";
114				reg = < 0x43f90000 0x4000 >;
115				interrupts = < 0x2d >;
116				clocks = < 0x02 0x0a 0x02 0x1e >;
117				clock-names = "ipg\0per";
118				status = "disabled";
119			};
120
121			serial@43f94000 {
122				compatible = "fsl,imx31-uart\0fsl,imx21-uart";
123				reg = < 0x43f94000 0x4000 >;
124				interrupts = < 0x20 >;
125				clocks = < 0x02 0x0a 0x02 0x1f >;
126				clock-names = "ipg\0per";
127				status = "disabled";
128			};
129
130			i2c@43f98000 {
131				compatible = "fsl,imx31-i2c\0fsl,imx21-i2c";
132				reg = < 0x43f98000 0x4000 >;
133				interrupts = < 0x04 >;
134				clocks = < 0x02 0x22 >;
135				#address-cells = < 0x01 >;
136				#size-cells = < 0x00 >;
137				status = "disabled";
138			};
139
140			spi@43fa4000 {
141				compatible = "fsl,imx31-cspi";
142				reg = < 0x43fa4000 0x4000 >;
143				interrupts = < 0x0e >;
144				clocks = < 0x02 0x0a 0x02 0x35 >;
145				clock-names = "ipg\0per";
146				dmas = < 0x03 0x08 0x08 0x00 0x03 0x09 0x08 0x00 >;
147				dma-names = "rx\0tx";
148				#address-cells = < 0x01 >;
149				#size-cells = < 0x00 >;
150				status = "disabled";
151			};
152
153			kpp@43fa8000 {
154				compatible = "fsl,imx31-kpp\0fsl,imx21-kpp";
155				reg = < 0x43fa8000 0x4000 >;
156				interrupts = < 0x18 >;
157				clocks = < 0x02 0x2e >;
158				status = "disabled";
159			};
160
161			serial@43fb0000 {
162				compatible = "fsl,imx31-uart\0fsl,imx21-uart";
163				reg = < 0x43fb0000 0x4000 >;
164				clocks = < 0x02 0x0a 0x02 0x31 >;
165				clock-names = "ipg\0per";
166				interrupts = < 0x2e >;
167				status = "disabled";
168			};
169
170			serial@43fb4000 {
171				compatible = "fsl,imx31-uart\0fsl,imx21-uart";
172				reg = < 0x43fb4000 0x4000 >;
173				interrupts = < 0x2f >;
174				clocks = < 0x02 0x0a 0x02 0x32 >;
175				clock-names = "ipg\0per";
176				status = "okay";
177				uart-has-rtscts;
178			};
179		};
180
181		spba@50000000 {
182			compatible = "fsl,spba-bus\0simple-bus";
183			#address-cells = < 0x01 >;
184			#size-cells = < 0x01 >;
185			reg = < 0x50000000 0x100000 >;
186			ranges;
187
188			sdhci@50004000 {
189				compatible = "fsl,imx31-mmc";
190				reg = < 0x50004000 0x4000 >;
191				interrupts = < 0x09 >;
192				clocks = < 0x02 0x0a 0x02 0x14 >;
193				clock-names = "ipg\0per";
194				dmas = < 0x03 0x14 0x03 0x00 >;
195				dma-names = "rx-tx";
196				status = "disabled";
197			};
198
199			sdhci@50008000 {
200				compatible = "fsl,imx31-mmc";
201				reg = < 0x50008000 0x4000 >;
202				interrupts = < 0x08 >;
203				clocks = < 0x02 0x0a 0x02 0x15 >;
204				clock-names = "ipg\0per";
205				dmas = < 0x03 0x15 0x03 0x00 >;
206				dma-names = "rx-tx";
207				status = "disabled";
208			};
209
210			serial@5000c000 {
211				compatible = "fsl,imx31-uart\0fsl,imx21-uart";
212				reg = < 0x5000c000 0x4000 >;
213				interrupts = < 0x12 >;
214				clocks = < 0x02 0x0a 0x02 0x30 >;
215				clock-names = "ipg\0per";
216				status = "disabled";
217			};
218
219			spi@50010000 {
220				compatible = "fsl,imx31-cspi";
221				reg = < 0x50010000 0x4000 >;
222				interrupts = < 0x0d >;
223				clocks = < 0x02 0x0a 0x02 0x36 >;
224				clock-names = "ipg\0per";
225				dmas = < 0x03 0x06 0x08 0x00 0x03 0x07 0x08 0x00 >;
226				dma-names = "rx\0tx";
227				#address-cells = < 0x01 >;
228				#size-cells = < 0x00 >;
229				status = "disabled";
230			};
231
232			iim@5001c000 {
233				compatible = "fsl,imx31-iim\0fsl,imx27-iim";
234				reg = < 0x5001c000 0x1000 >;
235				interrupts = < 0x13 >;
236				clocks = < 0x02 0x19 >;
237			};
238		};
239
240		aips@53f00000 {
241			compatible = "fsl,aips-bus\0simple-bus";
242			#address-cells = < 0x01 >;
243			#size-cells = < 0x01 >;
244			reg = < 0x53f00000 0x100000 >;
245			ranges;
246
247			ccm@53f80000 {
248				compatible = "fsl,imx31-ccm";
249				reg = < 0x53f80000 0x4000 >;
250				interrupts = < 0x1f 0x35 >;
251				#clock-cells = < 0x01 >;
252				phandle = < 0x02 >;
253			};
254
255			spi@53f84000 {
256				compatible = "fsl,imx31-cspi";
257				reg = < 0x53f84000 0x4000 >;
258				interrupts = < 0x11 >;
259				clocks = < 0x02 0x0a 0x02 0x1c >;
260				clock-names = "ipg\0per";
261				dmas = < 0x03 0x0a 0x08 0x00 0x03 0x0b 0x08 0x00 >;
262				dma-names = "rx\0tx";
263				#address-cells = < 0x01 >;
264				#size-cells = < 0x00 >;
265				status = "disabled";
266			};
267
268			timer@53f90000 {
269				compatible = "fsl,imx31-gpt";
270				reg = < 0x53f90000 0x4000 >;
271				interrupts = < 0x1d >;
272				clocks = < 0x02 0x0a 0x02 0x16 >;
273				clock-names = "ipg\0per";
274			};
275
276			gpio@53fa4000 {
277				compatible = "fsl,imx31-gpio";
278				reg = < 0x53fa4000 0x4000 >;
279				interrupts = < 0x38 >;
280				gpio-controller;
281				#gpio-cells = < 0x02 >;
282				interrupt-controller;
283				#interrupt-cells = < 0x02 >;
284			};
285
286			rng@53fb0000 {
287				compatible = "fsl,imx31-rnga";
288				reg = < 0x53fb0000 0x4000 >;
289				interrupts = < 0x16 >;
290				clocks = < 0x02 0x1d >;
291			};
292
293			gpio@53fcc000 {
294				compatible = "fsl,imx31-gpio";
295				reg = < 0x53fcc000 0x4000 >;
296				interrupts = < 0x34 >;
297				gpio-controller;
298				#gpio-cells = < 0x02 >;
299				interrupt-controller;
300				#interrupt-cells = < 0x02 >;
301			};
302
303			gpio@53fd0000 {
304				compatible = "fsl,imx31-gpio";
305				reg = < 0x53fd0000 0x4000 >;
306				interrupts = < 0x33 >;
307				gpio-controller;
308				#gpio-cells = < 0x02 >;
309				interrupt-controller;
310				#interrupt-cells = < 0x02 >;
311			};
312
313			sdma@53fd4000 {
314				compatible = "fsl,imx31-sdma";
315				reg = < 0x53fd4000 0x4000 >;
316				interrupts = < 0x22 >;
317				clocks = < 0x02 0x0a 0x02 0x1b >;
318				clock-names = "ipg\0ahb";
319				#dma-cells = < 0x03 >;
320				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
321				phandle = < 0x03 >;
322			};
323
324			rtc@53fd8000 {
325				compatible = "fsl,imx31-rtc\0fsl,imx21-rtc";
326				reg = < 0x53fd8000 0x4000 >;
327				interrupts = < 0x19 >;
328				clocks = < 0x02 0x02 0x02 0x28 >;
329				clock-names = "ref\0ipg";
330			};
331
332			wdog@53fdc000 {
333				compatible = "fsl,imx31-wdt\0fsl,imx21-wdt";
334				reg = < 0x53fdc000 0x4000 >;
335				clocks = < 0x02 0x29 >;
336			};
337
338			pwm@53fe0000 {
339				compatible = "fsl,imx31-pwm\0fsl,imx27-pwm";
340				reg = < 0x53fe0000 0x4000 >;
341				interrupts = < 0x1a >;
342				clocks = < 0x02 0x0a 0x02 0x2a >;
343				clock-names = "ipg\0per";
344				#pwm-cells = < 0x02 >;
345				status = "disabled";
346			};
347		};
348
349		emi@b8000000 {
350			compatible = "simple-bus";
351			reg = < 0xb8000000 0x5000 >;
352			ranges;
353			#address-cells = < 0x01 >;
354			#size-cells = < 0x01 >;
355
356			nand@b8000000 {
357				compatible = "fsl,imx31-nand\0fsl,imx27-nand";
358				reg = < 0xb8000000 0x1000 >;
359				interrupts = < 0x21 >;
360				clocks = < 0x02 0x09 >;
361				dmas = < 0x03 0x1e 0x11 0x00 >;
362				dma-names = "rx-tx";
363				#address-cells = < 0x01 >;
364				#size-cells = < 0x01 >;
365				status = "disabled";
366			};
367
368			weim@b8002000 {
369				compatible = "fsl,imx31-weim\0fsl,imx27-weim";
370				reg = < 0xb8002000 0x1000 >;
371				clocks = < 0x02 0x38 >;
372				#address-cells = < 0x02 >;
373				#size-cells = < 0x01 >;
374				ranges = < 0x00 0x00 0xa0000000 0x8000000 0x01 0x00 0xa8000000 0x8000000 0x02 0x00 0xb0000000 0x2000000 0x03 0x00 0xb2000000 0x2000000 0x04 0x00 0xb4000000 0x2000000 0x05 0x00 0xb6000000 0x2000000 >;
375				status = "disabled";
376			};
377		};
378	};
379
380	memory@80000000 {
381		reg = < 0x80000000 0x8000000 >;
382	};
383};
384