1/* Copyright (c) 2018 SiFive, Inc */
2/* SPDX-License-Identifier: Apache-2.0 */
3/* SPDX-License-Identifier: GPL-2.0-or-later */
4
5/dts-v1/;
6
7/ {
8  #address-cells = <0x00000002>;
9  #size-cells = <0x00000002>;
10  compatible = "sifive,fu540g", "sifive,fu500";
11  model = "sifive,hifive-unleashed-a00";
12  aliases {
13    serial0 = <0x2f736f63 0x2f736572 0x69616c40 0x31303031 0x30303030>;
14    serial1 = <0x2f736f63 0x2f736572 0x69616c40 0x31303031 0x31303030>;
15  };
16  chosen {
17    stdout-path = "/soc/serial@10010000";
18  };
19  firmware {
20    sifive,fsbl = "2018-03-20";
21  };
22  cpus {
23    #address-cells = <0x00000001>;
24    #size-cells = <0x00000000>;
25    timebase-frequency = <0x000f4240>;
26    cpu@0 {
27      clock-frequency = <0x00000000>;
28      compatible = "sifive,rocket0", "riscv";
29      device_type = "cpu";
30      i-cache-block-size = <0x00000040>;
31      i-cache-sets = <0x00000080>;
32      i-cache-size = <0x00004000>;
33      next-level-cache = <0x00000001 0x00000002>;
34      reg = <0x00000000>;
35      riscv,isa = "rv64imac";
36      sifive,dtim = <0x00000003>;
37      sifive,itim = <0x00000004>;
38      status = "masked";
39      interrupt-controller {
40        #interrupt-cells = <0x00000001>;
41        compatible = "riscv,cpu-intc";
42        interrupt-controller;
43        linux,phandle = <0x0000000f>;
44        phandle = <0x0000000f>;
45      };
46    };
47    cpu@1 {
48      clock-frequency = <0x00000000>;
49      compatible = "sifive,rocket0", "riscv";
50      d-cache-block-size = <0x00000040>;
51      d-cache-sets = <0x00000040>;
52      d-cache-size = <0x00008000>;
53      d-tlb-sets = <0x00000001>;
54      d-tlb-size = <0x00000020>;
55      device_type = "cpu";
56      i-cache-block-size = <0x00000040>;
57      i-cache-sets = <0x00000040>;
58      i-cache-size = <0x00008000>;
59      i-tlb-sets = <0x00000001>;
60      i-tlb-size = <0x00000020>;
61      mmu-type = "riscv,sv39";
62      next-level-cache = <0x00000001 0x00000002>;
63      reg = <0x00000001>;
64      riscv,isa = "rv64imafdc";
65      sifive,itim = <0x00000005>;
66      status = "okay";
67      tlb-split;
68      interrupt-controller {
69        #interrupt-cells = <0x00000001>;
70        compatible = "riscv,cpu-intc";
71        interrupt-controller;
72        linux,phandle = <0x00000010>;
73        phandle = <0x00000010>;
74      };
75    };
76    cpu@2 {
77      clock-frequency = <0x00000000>;
78      compatible = "sifive,rocket0", "riscv";
79      d-cache-block-size = <0x00000040>;
80      d-cache-sets = <0x00000040>;
81      d-cache-size = <0x00008000>;
82      d-tlb-sets = <0x00000001>;
83      d-tlb-size = <0x00000020>;
84      device_type = "cpu";
85      i-cache-block-size = <0x00000040>;
86      i-cache-sets = <0x00000040>;
87      i-cache-size = <0x00008000>;
88      i-tlb-sets = <0x00000001>;
89      i-tlb-size = <0x00000020>;
90      mmu-type = "riscv,sv39";
91      next-level-cache = <0x00000001 0x00000002>;
92      reg = <0x00000002>;
93      riscv,isa = "rv64imafdc";
94      sifive,itim = <0x00000006>;
95      status = "okay";
96      tlb-split;
97      interrupt-controller {
98        #interrupt-cells = <0x00000001>;
99        compatible = "riscv,cpu-intc";
100        interrupt-controller;
101        linux,phandle = <0x00000011>;
102        phandle = <0x00000011>;
103      };
104    };
105    cpu@3 {
106      clock-frequency = <0x00000000>;
107      compatible = "sifive,rocket0", "riscv";
108      d-cache-block-size = <0x00000040>;
109      d-cache-sets = <0x00000040>;
110      d-cache-size = <0x00008000>;
111      d-tlb-sets = <0x00000001>;
112      d-tlb-size = <0x00000020>;
113      device_type = "cpu";
114      i-cache-block-size = <0x00000040>;
115      i-cache-sets = <0x00000040>;
116      i-cache-size = <0x00008000>;
117      i-tlb-sets = <0x00000001>;
118      i-tlb-size = <0x00000020>;
119      mmu-type = "riscv,sv39";
120      next-level-cache = <0x00000001 0x00000002>;
121      reg = <0x00000003>;
122      riscv,isa = "rv64imafdc";
123      sifive,itim = <0x00000007>;
124      status = "okay";
125      tlb-split;
126      interrupt-controller {
127        #interrupt-cells = <0x00000001>;
128        compatible = "riscv,cpu-intc";
129        interrupt-controller;
130        linux,phandle = <0x00000012>;
131        phandle = <0x00000012>;
132      };
133    };
134    cpu@4 {
135      clock-frequency = <0x00000000>;
136      compatible = "sifive,rocket0", "riscv";
137      d-cache-block-size = <0x00000040>;
138      d-cache-sets = <0x00000040>;
139      d-cache-size = <0x00008000>;
140      d-tlb-sets = <0x00000001>;
141      d-tlb-size = <0x00000020>;
142      device_type = "cpu";
143      i-cache-block-size = <0x00000040>;
144      i-cache-sets = <0x00000040>;
145      i-cache-size = <0x00008000>;
146      i-tlb-sets = <0x00000001>;
147      i-tlb-size = <0x00000020>;
148      mmu-type = "riscv,sv39";
149      next-level-cache = <0x00000001 0x00000002>;
150      reg = <0x00000004>;
151      riscv,isa = "rv64imafdc";
152      sifive,itim = <0x00000008>;
153      status = "okay";
154      tlb-split;
155      interrupt-controller {
156        #interrupt-cells = <0x00000001>;
157        compatible = "riscv,cpu-intc";
158        interrupt-controller;
159        linux,phandle = <0x00000013>;
160        phandle = <0x00000013>;
161      };
162    };
163  };
164  memory@80000000 {
165    device_type = "memory";
166    reg = <0x00000000 0x80000000 0x00000002 0x00000000>;
167    linux,phandle = <0x0000000e>;
168    phandle = <0x0000000e>;
169  };
170  soc {
171    #address-cells = <0x00000002>;
172    #size-cells = <0x00000002>;
173    compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
174    ranges;
175    refclk {
176      #clock-cells = <0x00000000>;
177      compatible = "fixed-clock";
178      clock-frequency = <0x01fca055>;
179      clock-output-names = "xtal";
180      linux,phandle = <0x00000009>;
181      phandle = <0x00000009>;
182    };
183    prci@10000000 {
184      compatible = "sifive,aloeprci0";
185      reg = <0x00000000 0x10000000 0x00000000 0x00001000>;
186      reg-names = "control";
187      clocks = <0x00000009>;
188      #clock-cells = <0x00000001>;
189      linux,phandle = <0x0000000a>;
190      phandle = <0x0000000a>;
191    };
192    tlclk {
193      compatible = "fixed-factor-clock";
194      clocks = <0x0000000a 0x00000000>;
195      #clock-cells = <0x00000000>;
196      clock-div = <0x00000002>;
197      clock-mult = <0x00000001>;
198      linux,phandle = <0x00000016>;
199      phandle = <0x00000016>;
200    };
201    cadence-gemgxl-mgmt@100a0000 {
202      compatible = "sifive,cadencegemgxlmgmt0";
203      reg = <0x00000000 0x100a0000 0x00000000 0x00001000>;
204      reg-names = "control";
205      #clock-cells = <0x00000000>;
206      linux,phandle = <0x00000014>;
207      phandle = <0x00000014>;
208    };
209    bus-blocker@100b8000 {
210      compatible = "sifive,bus-blocker0";
211      reg = <0x00000000 0x100b8000 0x00000000 0x00001000>;
212      reg-names = "control";
213    };
214    cache-controller@2010000 {
215      cache-block-size = <0x00000040>;
216      cache-level = <0x00000002>;
217      cache-sets = <0x00000800>;
218      cache-size = <0x00200000>;
219      cache-unified;
220      compatible = "sifive,ccache0", "cache";
221      interrupt-parent = <0x0000000b>;
222      interrupts = <0x00000001 0x00000002 0x00000003>;
223      next-level-cache = <0x0000000c 0x0000000d 0x0000000e>;
224      reg = <0x00000000 0x02010000 0x00000000 0x00001000 0x00000000 0x08000000 0x00000000 0x02000000>;
225      reg-names = "control", "sideband";
226      linux,phandle = <0x00000002>;
227      phandle = <0x00000002>;
228    };
229    cadence-ddr-mgmt@100c0000 {
230      compatible = "sifive,cadenceddrmgmt0";
231      reg = <0x00000000 0x100c0000 0x00000000 0x00001000>;
232      reg-names = "control";
233    };
234    chiplink@40000000 {
235      #address-cells = <0x00000002>;
236      #size-cells = <0x00000002>;
237      compatible = "sifive,chiplink", "simple-bus";
238      ranges = <0x00000000 0x60000000 0x00000000 0x60000000 0x00000000 0x20000000 0x00000030 0x00000000 0x00000030 0x00000000 0x00000010 0x00000000 0x00000000 0x40000000 0x00000000 0x40000000 0x00000000 0x20000000 0x00000020 0x00000000 0x00000020 0x00000000 0x00000010 0x00000000>;
239      linux,phandle = <0x0000000d>;
240      phandle = <0x0000000d>;
241    };
242    dma@3000000 {
243      #dma-cells = <0x00000001>;
244      compatible = "riscv,dma0";
245      dma-channels = <0x00000004>;
246      dma-requests = <0x00000000>;
247      interrupt-parent = <0x0000000b>;
248      interrupts = <0x00000017 0x00000018 0x00000019 0x0000001a 0x0000001b 0x0000001c 0x0000001d 0x0000001e>;
249      reg = <0x00000000 0x03000000 0x00000000 0x00100000>;
250      reg-names = "control";
251      riscv,dma-pools = <0x00000001>;
252    };
253    dtim@1000000 {
254      compatible = "sifive,dtim0";
255      reg = <0x00000000 0x01000000 0x00000000 0x00002000>;
256      reg-names = "mem";
257      linux,phandle = <0x00000003>;
258      phandle = <0x00000003>;
259    };
260    ememoryotp@10070000 {
261      compatible = "sifive,ememoryotp0";
262      reg = <0x00000000 0x10070000 0x00000000 0x00001000>;
263      reg-names = "control";
264    };
265    error-device@18000000 {
266      compatible = "sifive,error0";
267      reg = <0x00000000 0x18000000 0x00000000 0x08000000>;
268      reg-names = "mem";
269      linux,phandle = <0x00000001>;
270      phandle = <0x00000001>;
271    };
272    ethernet@10090000 {
273      compatible = "cdns,macb";
274      interrupt-parent = <0x0000000b>;
275      interrupts = <0x00000035>;
276      reg = <0x00000000 0x10090000 0x00000000 0x00002000>;
277      reg-names = "control";
278      local-mac-address = <0x70b3d592>;
279      phy-mode = "gmii";
280      clock-names = <0x70636c6b 0x0068636c 0x6b007478 0x5f636c6b>;
281      clocks = <0x0000000a 0x00000001 0x0000000a 0x00000001 0x00000014>;
282      #address-cells = <0x00000001>;
283      #size-cells = <0x00000000>;
284      ethernet-phy@0 {
285        reg = <0x00000000>;
286        reset-gpios = <0x00000015 0x0000000c 0x00000001>;
287      };
288    };
289    gpio@10060000 {
290      compatible = "sifive,gpio0";
291      interrupt-parent = <0x0000000b>;
292      interrupts = <0x00000007 0x00000008 0x00000009 0x0000000a 0x0000000b 0x0000000c 0x0000000d 0x0000000e 0x0000000f 0x00000010 0x00000011 0x00000012 0x00000013 0x00000014 0x00000015 0x00000016>;
293      reg = <0x00000000 0x10060000 0x00000000 0x00001000>;
294      reg-names = "control";
295      gpio-controller;
296      #gpio-cells = <0x00000002>;
297      interrupt-controller;
298      #interrupt-cells = <0x00000002>;
299      linux,phandle = <0x00000015>;
300      phandle = <0x00000015>;
301    };
302    gpio-restart {
303      compatible = "gpio-restart";
304      gpios = <0x00000015 0x0000000a 0x00000001>;
305    };
306    i2c@10030000 {
307      compatible = "sifive,i2c0", "opencores,i2c-ocores";
308      reg = <0x00000000 0x10030000 0x00000000 0x00001000>;
309      reg-names = "control";
310      clocks = <0x00000016>;
311      reg-shift = <0x00000002>;
312      reg-io-width = <0x00000001>;
313      #address-cells = <0x00000001>;
314      #size-cells = <0x00000000>;
315    };
316    interrupt-controller@c000000 {
317      #interrupt-cells = <0x00000001>;
318      compatible = "riscv,plic0";
319      interrupt-controller;
320      interrupts-extended = <0x0000000f 0xffffffff 0x00000010 0xffffffff 0x00000010 0x00000009 0x00000011 0xffffffff 0x00000011 0x00000009 0x00000012 0xffffffff 0x00000012 0x00000009 0x00000013 0xffffffff 0x00000013 0x00000009>;
321      reg = <0x00000000 0x0c000000 0x00000000 0x04000000>;
322      reg-names = "control";
323      riscv,max-priority = <0x00000007>;
324      riscv,ndev = <0x00000035>;
325      linux,phandle = <0x0000000b>;
326      phandle = <0x0000000b>;
327    };
328    itim@1800000 {
329      compatible = "sifive,itim0";
330      reg = <0x00000000 0x01800000 0x00000000 0x00004000>;
331      reg-names = "mem";
332      linux,phandle = <0x00000004>;
333      phandle = <0x00000004>;
334    };
335    itim@1808000 {
336      compatible = "sifive,itim0";
337      reg = <0x00000000 0x01808000 0x00000000 0x00008000>;
338      reg-names = "mem";
339      linux,phandle = <0x00000005>;
340      phandle = <0x00000005>;
341    };
342    itim@1810000 {
343      compatible = "sifive,itim0";
344      reg = <0x00000000 0x01810000 0x00000000 0x00008000>;
345      reg-names = "mem";
346      linux,phandle = <0x00000006>;
347      phandle = <0x00000006>;
348    };
349    itim@1818000 {
350      compatible = "sifive,itim0";
351      reg = <0x00000000 0x01818000 0x00000000 0x00008000>;
352      reg-names = "mem";
353      linux,phandle = <0x00000007>;
354      phandle = <0x00000007>;
355    };
356    itim@1820000 {
357      compatible = "sifive,itim0";
358      reg = <0x00000000 0x01820000 0x00000000 0x00008000>;
359      reg-names = "mem";
360      linux,phandle = <0x00000008>;
361      phandle = <0x00000008>;
362    };
363    memory-controller@100b0000 {
364      compatible = "sifive,aloeddr0";
365      interrupt-parent = <0x0000000b>;
366      interrupts = <0x0000001f>;
367      reg = <0x00000000 0x100b0000 0x00000000 0x00004000>;
368      reg-names = "control";
369    };
370    pci@2000000000 {
371      #address-cells = <0x00000003>;
372      #interrupt-cells = <0x00000001>;
373      #size-cells = <0x00000002>;
374      compatible = "ms-pf,axi-pcie-host";
375      device_type = "pci";
376      interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000017 0x00000001 0x00000000 0x00000000 0x00000000 0x00000002 0x00000017 0x00000002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000017 0x00000003 0x00000000 0x00000000 0x00000000 0x00000004 0x00000017 0x00000004>;
377      interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
378      interrupt-parent = <0x0000000b>;
379      interrupts = <0x00000020>;
380      ranges = <0x02000000 0x00000000 0x40000000 0x00000000 0x40000000 0x00000000 0x20000000>;
381      reg = <0x00000020 0x00000000 0x00000000 0x04000000>;
382      reg-names = "control";
383      interrupt-controller {
384        #address-cells = <0x00000000>;
385        #interrupt-cells = <0x00000001>;
386        interrupt-controller;
387        linux,phandle = <0x00000017>;
388        phandle = <0x00000017>;
389      };
390    };
391    pinctrl@10080000 {
392      compatible = "sifive,pinctrl0";
393      reg = <0x00000000 0x10080000 0x00000000 0x00001000>;
394      reg-names = "control";
395    };
396    pwm@10020000 {
397      compatible = "sifive,pwm0";
398      interrupt-parent = <0x0000000b>;
399      interrupts = <0x0000002a 0x0000002b 0x0000002c 0x0000002d>;
400      reg = <0x00000000 0x10020000 0x00000000 0x00001000>;
401      reg-names = "control";
402      clocks = <0x00000016>;
403      sifive,approx-period = <0x000f4240>;
404      #pwm-cells = <0x00000002>;
405      linux,phandle = <0x00000018>;
406      phandle = <0x00000018>;
407    };
408    pwm@10021000 {
409      compatible = "sifive,pwm0";
410      interrupt-parent = <0x0000000b>;
411      interrupts = <0x0000002e 0x0000002f 0x00000030 0x00000031>;
412      reg = <0x00000000 0x10021000 0x00000000 0x00001000>;
413      reg-names = "control";
414      clocks = <0x00000016>;
415      sifive,approx-period = <0x000f4240>;
416      #pwm-cells = <0x00000002>;
417    };
418    pwmleds {
419      compatible = "pwm-leds";
420      heartbeat {
421        pwms = <0x00000018 0x00000000 0x00000000>;
422        max-brightness = <0x000000ff>;
423        linux,default-trigger = "heartbeat";
424      };
425      mtd {
426        pwms = <0x00000018 0x00000001 0x00000000>;
427        max-brightness = <0x000000ff>;
428        linux,default-trigger = "mtd";
429      };
430      netdev {
431        pwms = <0x00000018 0x00000002 0x00000000>;
432        max-brightness = <0x000000ff>;
433        linux,default-trigger = "netdev";
434      };
435      panic {
436        pwms = <0x00000018 0x00000003 0x00000000>;
437        max-brightness = <0x000000ff>;
438        linux,default-trigger = "panic";
439      };
440    };
441    rom@1000 {
442      compatible = "sifive,modeselect0";
443      reg = <0x00000000 0x00001000 0x00000000 0x00001000>;
444      reg-names = "mem";
445    };
446    rom@10000 {
447      compatible = "sifive,maskrom0";
448      reg = <0x00000000 0x00010000 0x00000000 0x00008000>;
449      reg-names = "mem";
450    };
451    rom@a000000 {
452      compatible = "ucbbar,cacheable-zero0";
453      reg = <0x00000000 0x0a000000 0x00000000 0x02000000>;
454      reg-names = "mem";
455      linux,phandle = <0x0000000c>;
456      phandle = <0x0000000c>;
457    };
458    serial@10010000 {
459      compatible = "sifive,uart0";
460      interrupt-parent = <0x0000000b>;
461      interrupts = <0x00000004>;
462      reg = <0x00000000 0x10010000 0x00000000 0x00001000>;
463      reg-names = "control";
464      clocks = <0x00000016>;
465    };
466    serial@10011000 {
467      compatible = "sifive,uart0";
468      interrupt-parent = <0x0000000b>;
469      interrupts = <0x00000005>;
470      reg = <0x00000000 0x10011000 0x00000000 0x00001000>;
471      reg-names = "control";
472      clocks = <0x00000016>;
473    };
474    spi@10040000 {
475      compatible = "sifive,spi0";
476      interrupt-parent = <0x0000000b>;
477      interrupts = <0x00000033>;
478      reg = <0x00000000 0x10040000 0x00000000 0x00001000 0x00000000 0x20000000 0x00000000 0x10000000>;
479      reg-names = "control", "mem";
480      clocks = <0x00000016>;
481      #address-cells = <0x00000001>;
482      #size-cells = <0x00000000>;
483      flash@0 {
484        compatible = "issi,is25wp256d", "jedec,spi-nor";
485        reg = <0x00000000>;
486        spi-max-frequency = <0x02faf080>;
487        m25p,fast-read;
488        spi-tx-bus-width = <0x00000004>;
489        spi-rx-bus-width = <0x00000004>;
490      };
491    };
492    spi@10041000 {
493      compatible = "sifive,spi0";
494      interrupt-parent = <0x0000000b>;
495      interrupts = <0x00000034>;
496      reg = <0x00000000 0x10041000 0x00000000 0x00001000 0x00000000 0x30000000 0x00000000 0x10000000>;
497      reg-names = "control", "mem";
498      clocks = <0x00000016>;
499      #address-cells = <0x00000001>;
500      #size-cells = <0x00000000>;
501    };
502    spi@10050000 {
503      compatible = "sifive,spi0";
504      interrupt-parent = <0x0000000b>;
505      interrupts = <0x00000006>;
506      reg = <0x00000000 0x10050000 0x00000000 0x00001000>;
507      reg-names = "control";
508      clocks = <0x00000016>;
509      #address-cells = <0x00000001>;
510      #size-cells = <0x00000000>;
511      mmc@0 {
512        compatible = "mmc-spi-slot";
513        reg = <0x00000000>;
514        spi-max-frequency = <0x01312d00>;
515        voltage-ranges = <0x00000ce4 0x00000ce4>;
516        disable-wp;
517        gpios = <0x00000015 0x0000000b 0x00000001>;
518      };
519    };
520    teststatus@4000 {
521      compatible = "sifive,test0";
522      reg = <0x00000000 0x00004000 0x00000000 0x00001000>;
523      reg-names = "control";
524    };
525  };
526};
527