1/* 2 * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7#ifndef __RISCV_PLAT_H 8#define __RISCV_PLAT_H 9 10#include <config.h> 11#define TIMER_CLOCK_HZ @CONFIGURE_TIMER_FREQUENCY@ 12#include <machine/interrupt.h> 13 14/* 15 * seL4 assigns all IRQs global interrupt numbers that are used in interrupt 16 * invocations. On RISC-V we have 3 different types of interrupts: core timer, 17 * core software generated, and global external IRQs delivered through the PLIC. 18 * Only global external interrupts are available from user level and so it is 19 * nice to be able to match PLIC IRQ numbers to seL4 IRQ numbers. The PLIC uses 20 * IRQ 0 to refer to no IRQ pending and so we can also use 0 for irqInvalid in 21 * the global IRQ number space and not have any aliasing issues. We then place 22 * the kernel timer interrupts after the last PLIC interrupt and intend on 23 * placing software generated interrupts after this in the future. As the kernel 24 * timer and SGI interrupts are never seen outside of the kernel, it doesn't 25 * matter what number they get assigned to as we can refer to them by their enum 26 * field name. 27 */ 28enum IRQConstants { 29 PLIC_IRQ_OFFSET = 0, 30 PLIC_MAX_IRQ = PLIC_IRQ_OFFSET + (@CONFIGURE_PLIC_MAX_NUM_INT@), 31#ifdef ENABLE_SMP_SUPPORT 32 INTERRUPT_IPI_0, 33 INTERRUPT_IPI_1, 34#endif 35 INTERRUPT_CORE_TIMER, 36 maxIRQ = INTERRUPT_CORE_TIMER, 37} platform_interrupt_t; 38 39enum irqNumbers { 40 irqInvalid = 0 41}; 42 43#define KERNEL_TIMER_IRQ INTERRUPT_CORE_TIMER 44#define IRQ_CNODE_SLOT_BITS (@CONFIGURE_IRQ_SLOT_BITS@) 45 46#include <@CONFIGURE_INTERRUPT_CONTROLLER@> 47 48#endif /* !__RISCV_PLAT_H */ 49