1#
2# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
3#
4# SPDX-License-Identifier: GPL-2.0-only
5#
6
7cmake_minimum_required(VERSION 3.7.2)
8
9config_string(
10    KernelPTLevels PT_LEVELS "Number of page \
11    table levels for RISC-V depends on the mode. For example there are: \
12    2, 3 and 4 levels on Sv32, Sv39, Sv48 RISC-V paging modes respectively."
13    DEFAULT 3 UNDEF_DISABLED
14    UNQUOTE
15    DEPENDS "KernelArchRiscV"
16)
17
18config_option(
19    KernelRiscvExtF RISCV_EXT_F "RISCV extension for single-preciison floating-point"
20    DEFAULT OFF
21    DEPENDS "KernelArchRiscV"
22)
23
24config_option(
25    KernelRiscvExtD RISCV_EXT_D "RISCV extension for double-precision floating-point"
26    DEFAULT OFF
27    DEPENDS "KernelArchRiscV"
28)
29
30if(KernelSel4ArchRiscV32)
31    set(KernelPTLevels 2 CACHE STRING "" FORCE)
32endif()
33if(KernelPTLevels EQUAL 2)
34    if(KernelSel4ArchRiscV32)
35        # seL4 on RISCV32 uses 32-bit ints for addresses,
36        # so limit the maximum paddr to 32-bits.
37        math(EXPR KernelPaddrUserTop "(1 << 32) - 1")
38    else()
39        math(EXPR KernelPaddrUserTop "(1 << 34) - 1")
40    endif()
41elseif(KernelPTLevels EQUAL 3)
42    # RISC-V technically supports 56-bit paddrs,
43    # but structures.bf limits us to using 39 of those bits.
44    math(EXPR KernelPaddrUserTop "(1 << 39) - 1")
45elseif(KernelPTLevels EQUAL 4)
46    math(EXPR KernelPaddrUserTop "(1 << 56) - 1")
47endif()
48
49if(KernelRiscvExtD)
50    set(KernelRiscvExtF ON)
51    set(KernelHaveFPU ON)
52endif()
53
54if(KernelRiscvExtF)
55    set(KernelHaveFPU ON)
56endif()
57
58# This is not supported on RISC-V
59set(KernelHardwareDebugAPIUnsupported ON CACHE INTERNAL "")
60
61add_sources(
62    DEP "KernelArchRiscV"
63    PREFIX src/arch/riscv
64    CFILES
65        c_traps.c
66        idle.c
67        api/faults.c
68        api/benchmark.c
69        kernel/boot.c
70        kernel/thread.c
71        kernel/vspace.c
72        machine/hardware.c
73        machine/registerset.c
74        machine/io.c
75        machine/fpu.c
76        model/statedata.c
77        object/interrupt.c
78        object/objecttype.c
79        object/tcb.c
80        smp/ipi.c
81    ASMFILES halt.S head.S traps.S
82)
83
84add_sources(DEP "KernelDebugBuild;KernelSel4ArchRiscV32" CFILES src/arch/riscv/machine/capdl.c)
85
86add_bf_source_old("KernelArchRiscV" "structures.bf" "include/arch/riscv" "arch/object")
87