1/*
2 * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 */
6
7#include <autoconf.h>
8#include <elfloader/gen_config.h>
9
10#include <assembler.h>
11#include <armv/assembler.h>
12
13.text
14
15.extern _boot_pd
16
17/*
18 * Enable the ARM MMU
19 *
20 * It is expected that the code of this function will be mapped 1:1
21 * virtual/physical in the pagetable we activate.
22 */
23BEGIN_FUNC(arm_enable_mmu)
24    /* ensure i-cache is disabled */
25    mrc     SCTLR(r0)
26    bic     r1, r0, #(1 << 12)
27    mcr     SCTLR(r1)
28
29    /* clean entire d-cache. */
30    mov     r1, #0
31    nop
32    mcr     DCIALL(r1)
33    nop
34    nop
35
36    /* drain write-buffer */
37    mcr     DCALL(r1)
38
39    /* clean i-cache */
40    mcr     IIALL(r1)
41
42    /* Setup client to only have access to domain 0, and setup the DACR. */
43    mov     r1, #1
44    mcr     DACR(r1)
45
46    /* Set up TTBR0, enable caching of pagetables. */
47    ldr     r2, =_boot_pd
48    orr     r1, r2, #0x19
49    mcr     TTBR0(r1)
50
51    /* setup misc MMU */
52    mov     r1, #0
53    mcr     CONTEXTIDR(r1)  /* set ASID to 0    */
54    mcr     TLBIALL(r1)     /* invalidate TLB entries */
55    mcr     TTBCR(r1)       /* set TTBCR to 0   */
56    mcr     PIALL(r1)       /* flush prefetch buffer */
57    mcr     BPIALL(r1)      /* flush branch target cache */
58
59    /* Enable MMU, D-cache, and I-cache. */
60    orr     r0, r0, #(1 << 13)      /* selects the base address of the exception vectors */
61    orr     r0, r0, #(1 << 12)      /* Enable I-cache */
62    orr     r0, r0, #(1 << 2)       /* Enable D-cache */
63    orr     r0, r0, #(1 << 0)       /* Enable MMU */
64    mcr     SCTLR(r0)
65
66    /* Enable/disable Async aborts to drain pending bootloader aborts */
67    mov     r0, #0
68    cpsie   a
69    mcr     DSB(r0)
70    mcr     ISB(r0)
71    cpsid   a
72
73    bx      lr
74END_FUNC(arm_enable_mmu)
75
76BEGIN_FUNC(arm_enable_hyp_mmu)
77    bl abort
78END_FUNC(arm_enable_hyp_mmu)
79