1/*
2 * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 */
6
7#include <autoconf.h>
8#include <elfloader/gen_config.h>
9.extern main
10.global _start
11.extern __global_pointer$
12.extern elfloader_stack_alloc
13
14#define BIT(n) (1 << (n))
15.section ".text.start"
16
17_start:
18
19.option push
20.option norelax
211:auipc gp, %pcrel_hi(__global_pointer$)
22  addi  gp, gp, %pcrel_lo(1b)
23.option pop
24
25/* BBL starts all HARTs and sends them to this entry point. */
26  li s0, CONFIG_FIRST_HART_ID
27  bne  a0, s0, secondary_harts
28
29  la sp, (elfloader_stack_alloc + BIT(12))
30
31  la s0, main
32  jr s0
33
34#if CONFIG_MAX_NUM_NODES > 1
35.extern next_logical_core_id
36.data
37bootstack_secondary_cores:
38.align 12
39.space 4096 * (CONFIG_MAX_NUM_NODES - 1)
40#endif
41
42.text
43
44secondary_harts:
45#if CONFIG_MAX_NUM_NODES > 1
46  la a1, next_logical_core_id
47  li t2, 1
48  amoadd.w a1, t2, (a1)
49  /* now a1 has the logical core id */
50  li t2, CONFIG_MAX_NUM_NODES
51  bge a1, t2, spin_hart
52  mv t0, a1
53  slli t0, t0, 12
54  la sp, bootstack_secondary_cores
55  add sp, sp, t0
56  la s0, secondary_entry
57  jr s0
58#endif
59spin_hart:
60  wfi
61  j spin_hart
62