1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#include <autoconf.h> 14#include <platsupport/gen_config.h> 15#include <platsupport/i2c.h> 16#include <platsupport/mux.h> 17#include <platsupport/plat/mux.h> 18#include <utils/util.h> 19#include "../../services.h" 20 21/********************* 22 *** SoC specifics *** 23 *********************/ 24 25#if defined(CONFIG_PLAT_EXYNOS4) 26/* IRQS */ 27#define EXYNOS_I2C0_IRQ 90 28#define EXYNOS_I2C1_IRQ 91 29#define EXYNOS_I2C2_IRQ 92 30#define EXYNOS_I2C3_IRQ 93 31#define EXYNOS_I2C4_IRQ 94 32#define EXYNOS_I2C5_IRQ 95 33#define EXYNOS_I2C6_IRQ 96 34#define EXYNOS_I2C7_IRQ 97 35#define EXYNOS_I2C8_IRQ 0 36#define EXYNOS_I2C9_IRQ 0 37#define EXYNOS_I2C10_IRQ 0 38#define EXYNOS_I2C11_IRQ 0 39/* Physical addresses */ 40#define EXYNOS_I2C0_PADDR 0x13860000 41#define EXYNOS_I2C1_PADDR 0x13870000 42#define EXYNOS_I2C2_PADDR 0x13880000 43#define EXYNOS_I2C3_PADDR 0x13890000 44#define EXYNOS_I2C4_PADDR 0x138A0000 45#define EXYNOS_I2C5_PADDR 0x138B0000 46#define EXYNOS_I2C6_PADDR 0x138C0000 47#define EXYNOS_I2C7_PADDR 0x138D0000 48#define EXYNOS_I2C8_PADDR 0x138E0000 49#define EXYNOS_I2C9_PADDR 0xDEADBEEF 50#define EXYNOS_I2C10_PADDR 0xDEADBEEF 51#define EXYNOS_I2C11_PADDR 0xDEADBEEF 52 53#elif defined(CONFIG_PLAT_EXYNOS5) 54/* IRQS */ 55#define EXYNOS_I2C0_IRQ 88 56#define EXYNOS_I2C1_IRQ 89 57#define EXYNOS_I2C2_IRQ 90 58#define EXYNOS_I2C3_IRQ 91 59#define EXYNOS_I2C4_IRQ 92 60#define EXYNOS_I2C5_IRQ 93 61#define EXYNOS_I2C6_IRQ 94 62#define EXYNOS_I2C7_IRQ 95 63#define EXYNOS_I2C8_IRQ 96 64#define EXYNOS_I2C9_IRQ 0 65#define EXYNOS_I2C10_IRQ 0 66#define EXYNOS_I2C11_IRQ 0 67/* Physical addresses */ 68#define EXYNOS_I2C0_PADDR 0x12C60000 69#define EXYNOS_I2C1_PADDR 0x12C70000 70#define EXYNOS_I2C2_PADDR 0x12C80000 71#define EXYNOS_I2C3_PADDR 0x12C90000 72#define EXYNOS_I2C4_PADDR 0x12CA0000 73#define EXYNOS_I2C5_PADDR 0x12CB0000 74#define EXYNOS_I2C6_PADDR 0x12CC0000 75#define EXYNOS_I2C7_PADDR 0x12CD0000 76#define EXYNOS_I2C8_PADDR 0x12CE0000 77#define EXYNOS_I2C9_PADDR 0x13130000 78#define EXYNOS_I2C10_PADDR 0x13140000 79#define EXYNOS_I2C11_PADDR 0x121D0000 80 81#else /* EXYNOS? */ 82#error Unknown Exynos based platform 83#endif /* EXYNOSX */ 84 85/* Sizes */ 86#define EXYNOS_I2CX_SIZE 0x1000 87#define EXYNOS_I2C0_SIZE EXYNOS_I2CX_SIZE 88#define EXYNOS_I2C1_SIZE EXYNOS_I2CX_SIZE 89#define EXYNOS_I2C2_SIZE EXYNOS_I2CX_SIZE 90#define EXYNOS_I2C3_SIZE EXYNOS_I2CX_SIZE 91#define EXYNOS_I2C4_SIZE EXYNOS_I2CX_SIZE 92#define EXYNOS_I2C5_SIZE EXYNOS_I2CX_SIZE 93#define EXYNOS_I2C6_SIZE EXYNOS_I2CX_SIZE 94#define EXYNOS_I2C7_SIZE EXYNOS_I2CX_SIZE 95#define EXYNOS_I2C8_SIZE EXYNOS_I2CX_SIZE 96#define EXYNOS_I2C9_SIZE EXYNOS_I2CX_SIZE 97#define EXYNOS_I2C10_SIZE EXYNOS_I2CX_SIZE 98#define EXYNOS_I2C11_SIZE EXYNOS_I2CX_SIZE 99 100/************************ 101 *** Register bitmaps *** 102 ************************/ 103/* control */ 104#define I2CCON_ACK_EN BIT(7) 105#define I2CCON_CLK_SRC BIT(6) 106#define I2CCON_IRQ_EN BIT(5) 107#define I2CCON_IRQ_PEND BIT(4) 108#define I2CCON_PRESCALE(x) (((x) & 0xf) * BIT(0)) 109#define I2CCON_PRESCALE_MASK I2CCON_PRESCALE(0xf) 110/* status */ 111#define I2CSTAT_MODE(x) (((x) & 0x3) * BIT(6)) 112#define I2CSTAT_MODE_SRX I2CSTAT_MODE(0x0) 113#define I2CSTAT_MODE_STX I2CSTAT_MODE(0x1) 114#define I2CSTAT_MODE_MRX I2CSTAT_MODE(0x2) 115#define I2CSTAT_MODE_MTX I2CSTAT_MODE(0x3) 116#define I2CSTAT_MODE_MASK I2CSTAT_MODE(0x3) 117#define I2CSTAT_BUSY BIT(5) 118#define I2CSTAT_ENABLE BIT(4) 119#define I2CSTAT_ARB_FAIL BIT(3) 120#define I2CSTAT_ADDR_SLAVE BIT(2) 121#define I2CSTAT_ADDR_ZERO BIT(1) 122#define I2CSTAT_ACK BIT(0) 123/* address */ 124#define I2CADDR(x) (((x) & 0xff) * BIT(0)) 125#define I2CADDR_MASK I2CADDR(0xff) 126/* data */ 127#define I2CDATA(x) (((x) & 0xff) * BIT(0)) 128#define I2CDATA_MASK I2CDATA(0xff) 129#define I2CDATA_READ(addr) I2CDATA(((addr) & 0xfe) | 1) 130#define I2CDATA_WRITE(addr) I2CDATA(((addr) & 0xfe) | 0) 131/* Line control */ 132#define I2CLC_FILT_EN BIT(2) 133#define I2CLC_SDA_DELAY(x) (((x) & 0x3) * BIT(0)) 134#define I2CLC_SDA_DELAY0CLK I2CLC_SDA_DELAY(0x0) 135#define I2CLC_SDA_DELAY5CLK I2CLC_SDA_DELAY(0x1) 136#define I2CLC_SDA_DELAY10CLK I2CLC_SDA_DELAY(0x2) 137#define I2CLC_SDA_DELAY15CLK I2CLC_SDA_DELAY(0x3) 138#define I2CLC_SDA_DELAY_MASK I2CLC_SDA_DELAY(0x3) 139 140struct exynos_i2c_regs { 141 uint32_t control; /* 0x0000 control register 0x0X */ 142 uint32_t status; /* 0x0004 control/status register 0x00 */ 143 uint32_t address; /* 0x0008 address register 0xXX */ 144 uint32_t data; /* 0x000C tx/rx data shift register 0xXX */ 145 uint32_t line_control; /* 0x0010 multi-master line control register */ 146}; 147 148struct i2c_bus_priv { 149 volatile struct exynos_i2c_regs* regs; 150 const char* tx_buf; 151 int tx_len; 152 int tx_count; 153 char* rx_buf; 154 int rx_len; 155 int rx_count; 156 enum mux_feature mux; 157}; 158 159static struct i2c_bus_priv _i2c[NI2C] = { 160 { .regs = NULL, .mux = MUX_I2C0 }, 161 { .regs = NULL, .mux = MUX_I2C1 }, 162 { .regs = NULL, .mux = MUX_I2C2 }, 163 { .regs = NULL, .mux = MUX_I2C3 }, 164 { .regs = NULL, .mux = MUX_I2C4 }, 165 { .regs = NULL, .mux = MUX_I2C5 }, 166 { .regs = NULL, .mux = MUX_I2C6 }, 167 { .regs = NULL, .mux = MUX_I2C7 }, 168#if defined(CONFIG_PLAT_EXYNOS4) 169#elif defined(CONFIG_PLAT_EXYNOS5) 170 { .regs = NULL, .mux = MUX_I2C8 }, 171 { .regs = NULL, .mux = MUX_I2C9 }, 172 { .regs = NULL, .mux = MUX_I2C10 }, 173 { .regs = NULL, .mux = MUX_I2C11 } 174#else /* EXYNOS? */ 175#error Unknown Exynos based platform 176#endif /* EXYNOSX */ 177}; 178 179static inline struct i2c_bus_priv* 180i2c_bus_get_priv(i2c_bus_t* i2c_bus) { 181 return (struct i2c_bus_priv*)i2c_bus->priv; 182} 183 184static inline int 185irq_pending(struct i2c_bus_priv* dev) 186{ 187 return !!(dev->regs->control & I2CCON_IRQ_PEND); 188} 189 190static inline void 191clear_pending(struct i2c_bus_priv* dev) 192{ 193 uint32_t v = dev->regs->control; 194 v &= ~(I2CCON_IRQ_PEND); 195 dev->regs->control = v; 196} 197 198static inline int 199addressed_as_slave(struct i2c_bus_priv* dev) 200{ 201 return !!(dev->regs->status & I2CSTAT_ADDR_SLAVE); 202} 203 204static inline int 205busy(struct i2c_bus_priv* dev) 206{ 207 return !!(dev->regs->status & I2CSTAT_BUSY); 208} 209 210static inline int 211acked(struct i2c_bus_priv* dev) 212{ 213 return !(dev->regs->status & I2CSTAT_ACK); 214} 215 216static inline int 217enabled(struct i2c_bus_priv* dev) 218{ 219 return !!(dev->regs->status & I2CSTAT_ENABLE); 220} 221 222static void 223master_txstart(struct i2c_bus_priv* dev, int slave) 224{ 225 dev->regs->control |= I2CCON_ACK_EN; 226 /** Configure Master Tx mode **/ 227 dev->regs->status = I2CSTAT_MODE_MTX | I2CSTAT_ENABLE; 228 /* Write slave address */ 229 dev->regs->data = I2CDATA_WRITE(slave); 230 /* Write 0xF0 (M/T Start) to I2CSTAT */ 231 clear_pending(dev); 232 dev->regs->status |= I2CSTAT_BUSY; 233} 234 235static void 236master_rxstart(struct i2c_bus_priv* dev, int slave) 237{ 238 dev->regs->control |= I2CCON_ACK_EN; 239 /** Configure Master Rx mode **/ 240 dev->regs->status = I2CSTAT_ENABLE | I2CSTAT_MODE_MRX; 241 /* Write slave address */ 242 dev->regs->data = I2CDATA_READ(slave); 243 /* Write 0xB0 (M/R Start) to I2CSTAT */ 244 dev->regs->status |= I2CSTAT_BUSY; 245} 246 247static void 248slave_init(struct i2c_bus_priv* dev, char addr) 249{ 250 dev->regs->address = addr; 251 /** Configure Master Rx mode **/ 252 dev->regs->status = I2CSTAT_ENABLE | I2CSTAT_MODE_SRX; 253} 254 255int 256exynos_i2c_read(i2c_bus_t* i2c_bus, void* vdata, size_t len, 257 UNUSED bool send_stop, 258 i2c_callback_fn cb, void* token) 259{ 260 struct i2c_bus_priv* dev = i2c_bus_get_priv(i2c_bus); 261 262 dev->rx_buf = (char*)vdata; 263 dev->rx_len = len; 264 dev->rx_count = 0; 265 i2c_bus->cb = cb; 266 i2c_bus->token = token; 267 268 ZF_LOGD("Reading %d bytes as slave 0x%x", len, dev->regs->address); 269 dev->regs->control |= I2CCON_ACK_EN; 270 271 if (cb == NULL) { 272 /* Read bytes */ 273 while (dev->rx_count < dev->rx_len && busy(dev)) { 274 i2c_handle_irq(i2c_bus); 275 } 276 ZF_LOGD("read %d bytes", dev->rx_count); 277 return dev->rx_count; 278 } else { 279 /* Let the ISR handle it */ 280 return 0; 281 } 282} 283 284static int 285exynos_i2c_write(i2c_bus_t* i2c_bus, const void* vdata, size_t len, 286 UNUSED bool send_stop, 287 i2c_callback_fn cb, void* token) 288{ 289 struct i2c_bus_priv* dev = i2c_bus_get_priv(i2c_bus); 290 291 dev->tx_buf = (char*)vdata; 292 dev->tx_len = len; 293 dev->tx_count = 0; 294 i2c_bus->cb = cb; 295 i2c_bus->token = token; 296 297 ZF_LOGD("Writing %d bytes as slave 0x%x", len, dev->regs->address); 298 dev->regs->control |= I2CCON_ACK_EN; 299 300 if (cb == NULL) { 301 while (dev->tx_count < dev->tx_len && busy(dev)) { 302 i2c_handle_irq(i2c_bus); 303 } 304 ZF_LOGD("wrote %d bytes", dev->tx_count); 305 return dev->tx_count; 306 } else { 307 /* Let the ISR handle it */ 308 return 0; 309 } 310} 311 312static int 313exynos_i2c_master_stop(i2c_bus_t* i2c_bus) 314{ 315 assert(!"Not implemented"); 316 return -1; 317} 318 319/* Exynos4 manual Figure 14-6 p14-9 */ 320static int 321exynos_i2c_start_read(i2c_slave_t* sl, void* vdata, size_t len, 322 UNUSED bool end_with_repeat_start, 323 i2c_callback_fn cb, void* token) 324{ 325 struct i2c_bus_priv* dev; 326 327 assert(sl != NULL && sl->bus != NULL); 328 329 dev = i2c_bus_get_priv(sl->bus); 330 ZF_LOGD("Reading %d bytes from slave@0x%02x", len, sl->address); 331 master_rxstart(dev, sl->address); 332 333 /* Setup the RX descriptor */ 334 dev->rx_buf = (char*)vdata; 335 dev->rx_len = len; 336 dev->rx_count = -1; 337 sl->bus->cb = cb; 338 sl->bus->token = token; 339 340 /* Wait for completion */ 341 if (cb == NULL) { 342 while (busy(dev)) { 343 i2c_handle_irq(sl->bus); 344 } 345 } else { 346 clear_pending(dev); // Clears any interrupts 347 return dev->rx_len; 348 } 349 return dev->rx_count; 350} 351 352/* Exynos4 manual Figure 14-6 p14-8 */ 353static int 354exynos_i2c_start_write(i2c_slave_t* sl, const void* vdata, size_t len, 355 UNUSED bool end_with_repeat_start, 356 i2c_callback_fn cb, void* token) 357{ 358 struct i2c_bus_priv* dev; 359 360 assert(sl != NULL && sl->bus != NULL); 361 362 dev = i2c_bus_get_priv(sl->bus); 363 ZF_LOGD("Writing %d bytes to slave@0x%02x", len, sl->address); 364 master_txstart(dev, sl->address); 365 366 dev->tx_count = -1; 367 dev->tx_len = len; 368 dev->tx_buf = (const char*)vdata; 369 sl->bus->cb = cb; 370 sl->bus->token = token; 371 372 if (cb == NULL) { 373 while (busy(dev)) { 374 i2c_handle_irq(sl->bus); 375 } 376 } else { 377 clear_pending(dev); // Clears any interrupts 378 return dev->tx_len; 379 } 380 return dev->tx_count; 381} 382 383static void 384exynos_i2c_send_stop(i2c_bus_t* i2c_bus, enum i2c_stat status) 385{ 386 struct i2c_bus_priv *dev = i2c_bus_get_priv(i2c_bus); 387 dev->regs->status &= ~(I2CSTAT_BUSY); 388 clear_pending(dev); 389 if (i2c_bus->cb) { 390 i2c_bus->cb(i2c_bus, status, dev->tx_count, i2c_bus->token); 391 } 392} 393 394static enum i2c_mode 395exynos_i2c_probe_aas(i2c_bus_t* i2c_bus) 396{ 397 struct i2c_bus_priv* dev; 398 enum i2c_mode mode = I2CMODE_IDLE; 399 dev = i2c_bus_get_priv(i2c_bus); 400 401 if (addressed_as_slave(dev)) { 402 if ((dev->regs->status & I2CSTAT_MODE_MASK) == I2CSTAT_MODE_STX) { 403 mode = I2CMODE_TX; 404 } else { 405 mode = I2CMODE_RX; 406 } 407 408 ZF_LOGD("Addressed as slave for %s transfer.", 409 (mode == I2CMODE_RX) ? "READ" : "WRITE"); 410 411 /* Call out to the handler if one was registered */ 412 if (i2c_bus->aas_cb) { 413 /* Is there a transfer in flight? */ 414 if (i2c_bus->cb && (dev->tx_len || dev->rx_len)) { 415 size_t bytes; 416 if (mode == I2CMODE_TX) { 417 bytes = dev->tx_count; 418 } else { 419 bytes = dev->rx_count; 420 } 421 i2c_bus->cb(i2c_bus, I2CSTAT_INCOMPLETE, bytes, i2c_bus->token); 422 } 423 i2c_bus->aas_cb(i2c_bus, mode, i2c_bus->aas_token); 424 } 425 /* In read mode, must we perform a dummy read of the received address */ 426 if (mode == I2CMODE_RX) { 427 (void)dev->regs->data; 428 clear_pending(dev); 429 } 430 } 431 return mode; 432} 433 434static void 435exynos_i2c_handle_irq(i2c_bus_t* i2c_bus) 436{ 437 struct i2c_bus_priv* dev; 438 uint32_t v; 439 dev = i2c_bus_get_priv(i2c_bus); 440 441 /* AddressedAsSlave seems to be read_to_clear so process the event immediately */ 442 i2c_probe_aas(i2c_bus); 443 444 /* Anything to do? */ 445 if (!enabled(dev) || !irq_pending(dev)) { 446 return; 447 } 448 449 /* Handle transfer */ 450 switch (dev->regs->status & I2CSTAT_MODE_MASK) { 451 case I2CSTAT_MODE_MRX: 452 if (dev->rx_count < 0) { 453 if (acked(dev)) { 454 /* slave responded to the address */ 455 dev->rx_count = 0; 456 } else { 457 /* No response: Abort */ 458 exynos_i2c_send_stop(i2c_bus, I2CSTAT_ERROR); 459 } 460 } else if (dev->regs->control & I2CCON_ACK_EN) { 461 /* Read from slave */ 462 v = dev->regs->data; 463 *dev->rx_buf++ = v; 464 dev->rx_count++; 465 /* Don't ACK the last byte */ 466 if (dev->rx_count == dev->rx_len) { 467 dev->regs->control &= ~(I2CCON_ACK_EN); 468 } 469 } else { 470 /* Finally, send stop */ 471 exynos_i2c_send_stop(i2c_bus, I2CSTAT_COMPLETE); 472 } 473 break; 474 case I2CSTAT_MODE_MTX: 475 if (acked(dev)) { 476 /* Start pumping out data */ 477 v = *dev->tx_buf++; 478 dev->regs->data = v; 479 dev->tx_count++; 480 if (dev->tx_count == dev->tx_len) { 481 /* Write 0xD0 (M/T Stop) to I2CSTAT */ 482 exynos_i2c_send_stop(i2c_bus, I2CSTAT_COMPLETE); 483 } 484 } else { 485 /* No response: Abort */ 486 exynos_i2c_send_stop(i2c_bus, I2CSTAT_ERROR); 487 } 488 break; 489 case I2CSTAT_MODE_SRX: 490 /* Read in the data */ 491 if (dev->rx_buf) { 492 *dev->rx_buf++ = dev->regs->data; 493 } else { 494 (void)dev->regs->data; 495 } 496 dev->rx_count++; 497 /* Last chance for user to supply another buffer */ 498 if (i2c_bus->cb && (dev->rx_count == dev->rx_len)) { 499 i2c_bus->cb(i2c_bus, I2CSTAT_LASTBYTE, dev->rx_count, i2c_bus->token); 500 } 501 /* If this is STILL the last byte, finish up */ 502 if (dev->rx_count == dev->rx_len) { 503 dev->rx_len = 0; 504 if (i2c_bus->cb) { 505 i2c_bus->cb(i2c_bus, I2CSTAT_COMPLETE, dev->rx_count, i2c_bus->token); 506 } 507 } 508 509 break; 510 case I2CSTAT_MODE_STX: 511 /* Last byte? */ 512 if (!acked(dev)) { 513 enum i2c_stat stat; 514 if (dev->tx_len == dev->tx_count) { 515 stat = I2CSTAT_COMPLETE; 516 } else { 517 stat = I2CSTAT_INCOMPLETE; 518 } 519 /* Now we need to handle the stop. For some reason, we need to prime 520 * the data register first, but this byte will not actually be sent. */ 521 dev->regs->data = 0xff; 522 dev->tx_len = 0; 523 /* Signal the application */ 524 if (i2c_bus->cb) { 525 i2c_bus->cb(i2c_bus, stat, dev->tx_count, i2c_bus->token); 526 } 527 } else if (dev->tx_count == dev->tx_len) { 528 dev->tx_len = 0; 529 if (i2c_bus->cb) { 530 i2c_bus->cb(i2c_bus, I2CSTAT_COMPLETE, dev->tx_count, i2c_bus->token); 531 } 532 } else if (dev->tx_count < dev->tx_len) { 533 /* Call out to user before sending the last byte. We could call out AFTER 534 * sending the last byte, but it is nice to be consitant with RX behaviour */ 535 if (i2c_bus->cb && (dev->tx_count + 1 < dev->tx_len)) { 536 i2c_bus->cb(i2c_bus, I2CSTAT_LASTBYTE, dev->tx_count, i2c_bus->token); 537 } 538 if (dev->tx_buf) { 539 dev->regs->data = *dev->tx_buf++; 540 } else { 541 dev->regs->data = 0x00; 542 } 543 dev->tx_count++; 544 } 545 break; 546 default: 547 assert(!"Unknown I2C mode"); 548 } 549 clear_pending(dev); 550} 551 552static long 553exynos_i2c_set_speed(i2c_bus_t* i2c_bus, UNUSED enum i2c_slave_speed speed) 554{ 555 ZF_LOGF("Not implemented"); 556 return -1; 557} 558 559static int 560exynos_i2c_set_self_slave_address(i2c_bus_t* i2c_bus, int addr) 561{ 562 struct i2c_bus_priv* dev; 563 dev = i2c_bus_get_priv(i2c_bus); 564 slave_init(dev, addr); 565 dev->regs->line_control = BIT(2) | 0x3 ; 566 return 0; 567} 568 569static void 570exynos_i2c_register_slave_event_handler(i2c_bus_t *bus, 571 i2c_aas_callback_fn cb, void *token) 572{ 573 assert(bus != NULL); 574 bus->aas_cb = cb; 575 bus->aas_token = token; 576} 577 578static int 579exynos_i2c_slave_init(i2c_bus_t* i2c_bus, int address, 580 enum i2c_slave_address_size address_size, 581 enum i2c_slave_speed max_speed, 582 uint32_t flags, 583 i2c_slave_t* sl) 584{ 585 assert(sl != NULL); 586 587 if (address_size == I2C_SLAVE_ADDR_7BIT) { 588 address = i2c_extract_address(address); 589 } 590 591 sl->address = address; 592 sl->address_size = address_size; 593 sl->max_speed = max_speed; 594 sl->i2c_opts = flags; 595 sl->bus = i2c_bus; 596 597 sl->slave_read = exynos_i2c_start_read; 598 sl->slave_write = exynos_i2c_start_write; 599 600 return 0; 601} 602 603static int 604i2c_init_common(mux_sys_t* mux, i2c_bus_t* i2c, struct i2c_bus_priv* dev) 605{ 606 /* Check that our memory was mapped */ 607 if (dev->regs == NULL) { 608 return -2; 609 } 610 ZF_LOGD("Memory for regs mapped"); 611 612 /* Configure MUX */ 613 if (mux_sys_valid(mux) && mux_feature_enable(mux, dev->mux, MUX_DIR_NOT_A_GPIO)) { 614 ZF_LOGD("Warning: failed to configure MUX"); 615 } 616 617 /* I2C setup */ 618 dev->regs->control = I2CCON_ACK_EN | 0 * I2CCON_CLK_SRC 619 | I2CCON_PRESCALE(7) | I2CCON_IRQ_EN; 620 dev->regs->line_control = I2CLC_SDA_DELAY15CLK | I2CLC_FILT_EN; 621 dev->regs->address = 0x54; 622 623 i2c->slave_init = exynos_i2c_slave_init; 624 i2c->read = exynos_i2c_read; 625 i2c->write = exynos_i2c_write; 626 i2c->set_speed = exynos_i2c_set_speed; 627 i2c->set_self_slave_address = exynos_i2c_set_self_slave_address; 628 i2c->register_slave_event_handler = exynos_i2c_register_slave_event_handler; 629 i2c->probe_aas = exynos_i2c_probe_aas; 630 i2c->master_stop = exynos_i2c_master_stop; 631 i2c->handle_irq = exynos_i2c_handle_irq; 632 i2c->priv = (void*)dev; 633 634 i2c->cb = NULL; 635 i2c->token = NULL; 636 i2c->aas_cb = NULL; 637 i2c->aas_token = NULL; 638 return 0; 639} 640 641int 642exynos_i2c_init(enum i2c_id id, void* base, mux_sys_t* mux, i2c_bus_t* i2c) 643{ 644 struct i2c_bus_priv* dev = _i2c + id; 645 ZF_LOGD("Mapping i2c %d", id); 646 dev->regs = base; 647 return i2c_init_common(mux, i2c, dev); 648} 649 650int 651i2c_init(enum i2c_id id, ps_io_ops_t* io_ops, i2c_bus_t* i2c) 652{ 653 struct i2c_bus_priv* dev = _i2c + id; 654 mux_sys_t* mux = &io_ops->mux_sys; 655 /* Map memory */ 656 ZF_LOGD("Mapping i2c %d", id); 657 switch (id) { 658 case I2C0: 659 MAP_IF_NULL(io_ops, EXYNOS_I2C0, dev->regs); 660 break; 661 case I2C1: 662 MAP_IF_NULL(io_ops, EXYNOS_I2C1, dev->regs); 663 break; 664 case I2C2: 665 MAP_IF_NULL(io_ops, EXYNOS_I2C2, dev->regs); 666 break; 667 case I2C3: 668 MAP_IF_NULL(io_ops, EXYNOS_I2C3, dev->regs); 669 break; 670 case I2C4: 671 MAP_IF_NULL(io_ops, EXYNOS_I2C4, dev->regs); 672 break; 673 case I2C5: 674 MAP_IF_NULL(io_ops, EXYNOS_I2C5, dev->regs); 675 break; 676 case I2C6: 677 MAP_IF_NULL(io_ops, EXYNOS_I2C6, dev->regs); 678 break; 679 case I2C7: 680 MAP_IF_NULL(io_ops, EXYNOS_I2C7, dev->regs); 681 break; 682#if defined(CONFIG_PLAT_EXYNOS4) 683#elif defined(CONFIG_PLAT_EXYNOS5) 684 case I2C8: 685 MAP_IF_NULL(io_ops, EXYNOS_I2C8, dev->regs); 686 break; 687 case I2C9: 688 MAP_IF_NULL(io_ops, EXYNOS_I2C9, dev->regs); 689 break; 690 case I2C10: 691 MAP_IF_NULL(io_ops, EXYNOS_I2C10, dev->regs); 692 break; 693 case I2C11: 694 MAP_IF_NULL(io_ops, EXYNOS_I2C11, dev->regs); 695 break; 696#else /* EXYNOS? */ 697#error Unknown Exynos based platform 698#endif /* EXYNOSX */ 699 default : 700 return -1; 701 } 702 return i2c_init_common(mux, i2c, dev); 703} 704