1/*
2 * Copyright 2018, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12
13#pragma once
14
15/*
16 * Clocks presumed to actually be gates, add these back into enum clk_id if these are
17 * actually clocks that can have their frequency configured.
18 */
19/*
20    CLK_FUSE
21    CLK_GPU
22    CLK_PCIE
23    CLK_AFI
24    CLK_PCIE2_IOBIST
25    CLK_PCIERX0
26    CLK_PCIERX1
27    CLK_PCIERX2
28    CLK_PCIERX3
29    CLK_PCIERX4
30    CLK_SPDIF_IN
31    CLK_DTV
32    CLK_SE
33    CLK_DP2
34    CLK_APB2APE
35    CLK_CEC
36    CLK_DPAUX1
37    CLK_DPAUX
38    CLK_HDA2HDMICODEC
39    CLK_APE
40    CLK_SATA_OOB
41    CLK_SATA_IOBIST
42    CLK_IQC1
43    CLK_PLLREFE_PLL_REF
44    CLK_XUSB_SS
45    CLK_MIPI_CAL
46    CLK_DSI
47    CLK_DSIB
48    CLK_HSIC_TRK
49    CLK_USB2_TRK
50    CLK_IQC2
51    CLK_32K
52    CLK_ADSP
53    CLK_ADSPNEON
54    CLK_MPHY_L0_RX_LS_BIT
55    CLK_MPHY_L0_TX_LS_3XBIT
56    CLK_MPHY_L0_RX_ANA
57    CLK_MPHY_L1_RX_ANA
58    CLK_NVDISPLAY_DSC
59    CLK_EQOS_AXI
60    CLK_KFUSE
61    CLK_EQOS_RX
62    CLK_M
63 */
64
65enum clk_id {
66    CLK_PLLC_OUT_ISP,
67    CLK_PLLC_OUT_VE,
68    CLK_PLLC_OUT_AON,
69    CLK_SOR_SAFE,
70    CLK_I2S2,
71    CLK_I2S3,
72    CLK_SPDIF_DOUBLER,
73    CLK_SPI3,
74    CLK_I2C1,
75    CLK_I2C5,
76    CLK_SPI1,
77    CLK_VI,
78    CLK_SDMMC1,
79    CLK_SDMMC2,
80    CLK_SDMMC4,
81    CLK_UARTA,
82    CLK_UARTB,
83    CLK_HOST1X,
84    CLK_EMC,
85    CLK_EXTPERIPH4,
86    CLK_SPI4,
87    CLK_I2C3,
88    CLK_SDMMC3,
89    CLK_UARTD,
90    CLK_I2S1,
91    CLK_TSEC,
92    CLK_I2S4,
93    CLK_I2S5,
94    CLK_I2C4,
95    CLK_AHUB,
96    CLK_HDA2CODEC_2X,
97    CLK_EXTPERIPH1,
98    CLK_EXTPERIPH2,
99    CLK_EXTPERIPH3,
100    CLK_I2C_SLOW,
101    CLK_SOR1,
102    CLK_SOR0,
103    CLK_SATA,
104    CLK_HDA,
105    CLK_PLLREFE_OUT,
106    CLK_PLLC4_OUT,
107    CLK_XUSB,
108    CLK_XUSB_DEV,
109    CLK_XUSB_HOST,
110    CLK_DSIA_LP,
111    CLK_DSIB_LP,
112    CLK_DMIC1,
113    CLK_DMIC2,
114    CLK_AUD_MCLK,
115    CLK_I2C6,
116    CLK_UART_FST_MIPI_CAL,
117    CLK_VIC,
118    CLK_SDMMC_LEGACY_TM,
119    CLK_NVDEC,
120    CLK_NVJPG,
121    CLK_NVENC,
122    CLK_QSPI,
123    CLK_VI_I2C,
124    CLK_MAUD,
125    CLK_TSECB,
126    CLK_MPHY_L0_RX_SYMB,
127    CLK_MPHY_L0_TX_SYMB,
128    CLK_MPHY_IOBIST,
129    CLK_MPHY_TX_1MHZ_REF,
130    CLK_MPHY_CORE_PLL_FIXED,
131    CLK_AXI_CBB,
132    CLK_DMIC3,
133    CLK_DMIC4,
134    CLK_DSPK1,
135    CLK_DSPK2,
136    CLK_I2S6,
137    CLK_NVDISPLAY_P0,
138    CLK_NVDISPLAY_DISP,
139    CLK_NVDISPLAYHUB,
140    CLK_NVDISPLAY_P1,
141    CLK_NVDISPLAY_P2,
142    CLK_TACH,
143    CLK_UFSHC,
144    CLK_UFSDEV_REF,
145    CLK_NVCSI,
146    CLK_NVCSILP,
147    CLK_I2C7,
148    CLK_I2C9,
149    CLK_I2C12,
150    CLK_I2C13,
151    CLK_I2C14,
152    CLK_PWM1,
153    CLK_PWM2,
154    CLK_PWM3,
155    CLK_PWM5,
156    CLK_PWM6,
157    CLK_PWM7,
158    CLK_PWM8,
159    CLK_UARTE,
160    CLK_UARTF,
161    CLK_DBGAPB,
162    CLK_BPMP_CPU_NIC,
163    CLK_BPMP_APB,
164    CLK_ACTMON,
165    CLK_AON_CPU_NIC,
166    CLK_CAN1,
167    CLK_CAN1_HOST,
168    CLK_CAN2,
169    CLK_CAN2_HOST,
170    CLK_AON_APB,
171    CLK_UARTC,
172    CLK_UARTG,
173    CLK_AON_UART_FST_MIPI_CAL,
174    CLK_I2C2,
175    CLK_I2C8,
176    CLK_I2C10,
177    CLK_AON_I2C_SLOW,
178    CLK_SPI2,
179    CLK_DMIC5,
180    CLK_AON_TOUCH,
181    CLK_PWM4,
182    CLK_TSC,
183    CLK_MSS_ENCRYPT,
184    CLK_SCE_CPU_NIC,
185    CLK_SCE_APB,
186    CLK_DSIC,
187    CLK_DSIC_LP,
188    CLK_DSID,
189    CLK_DSID_LP,
190    CLK_PEX_SATA_USB_RX_BYP,
191    CLK_SPDIF_OUT,
192    CLK_EQOS_PTP_REF,
193    CLK_EQOS_TX,
194    CLK_USB2_HSIC_TRK,
195    CLK_XUSB_CORE_SS,
196    CLK_XUSB_CORE_DEV,
197    CLK_XUSB_FALCON,
198    CLK_XUSB_FS,
199    CLK_PLL_A_OUT0,
200    CLK_SYNC_I2S1,
201    CLK_SYNC_I2S2,
202    CLK_SYNC_I2S3,
203    CLK_SYNC_I2S4,
204    CLK_SYNC_I2S5,
205    CLK_SYNC_I2S6,
206    CLK_SYNC_DSPK1,
207    CLK_SYNC_DSPK2,
208    CLK_SYNC_DMIC1,
209    CLK_SYNC_DMIC2,
210    CLK_SYNC_DMIC3,
211    CLK_SYNC_DMIC4,
212    CLK_SYNC_SPDIF,
213    CLK_PLLREFE_OUT_GATED,
214    CLK_PLLREFE_OUT1,
215    CLK_PLLD_OUT1,
216    CLK_PLLP_OUT0,
217    CLK_PLLP_OUT5,
218    CLK_PLLA,
219    CLK_ACLK,
220    CLK_PLL_U_48M,
221    CLK_PLL_U_480M,
222    CLK_PLLC4_OUT0,
223    CLK_PLLC4_OUT1,
224    CLK_PLLC4_OUT2,
225    CLK_PLLC4_OUT_MUX,
226    CLK_DFLLDISP_DIV,
227    CLK_PLLDISPHUB_DIV,
228    CLK_PLLP_DIV8,
229    CLK_BPMP_NIC,
230    CLK_PLL_A_OUT1,
231    CLK_GPC2CLK,
232    CLK_PLLE_PWRSEQ,
233    CLK_PLLREFE_REF,
234    CLK_SOR0_OUT,
235    CLK_SOR1_OUT,
236    CLK_PLLREFE_OUT1_DIV5,
237    CLK_UTMIP_PLL_PWRSEQ,
238    CLK_PEX_USB_PAD0_MGMT,
239    CLK_PEX_USB_PAD1_MGMT,
240    CLK_UPHY_PLL0_PWRSEQ,
241    CLK_UPHY_PLL1_PWRSEQ,
242    CLK_PLLREFE_PLLE_PASSTHROUGH,
243    CLK_PLLREFE_PEX,
244    CLK_PLLREFE_IDDQ,
245    CLK_QSPI_OUT,
246    CLK_GPCCLK,
247    CLK_AON_NIC,
248    CLK_SCE_NIC,
249    CLK_PLLE,
250    CLK_PLLC,
251    CLK_PLLP,
252    CLK_PLLD,
253    CLK_PLLD2,
254    CLK_PLLREFE_VCO,
255    CLK_PLLC2,
256    CLK_PLLC3,
257    CLK_PLLDP,
258    CLK_PLLC4_VCO,
259    CLK_PLLA1,
260    CLK_PLLNVCSI,
261    CLK_PLLDISPHUB,
262    CLK_PLLD3,
263    CLK_PLLBPMPCAM,
264    CLK_PLLAON,
265    CLK_PLLU,
266    CLK_PLLC4_VCO_DIV2,
267    CLK_NAFLL_AXI_CBB,
268    CLK_NAFLL_BPMP,
269    CLK_NAFLL_ISP,
270    CLK_NAFLL_NVDEC,
271    CLK_NAFLL_NVENC,
272    CLK_NAFLL_NVJPG,
273    CLK_NAFLL_SCE,
274    CLK_NAFLL_SE,
275    CLK_NAFLL_TSEC,
276    CLK_NAFLL_TSECB,
277    CLK_NAFLL_VI,
278    CLK_NAFLL_VIC,
279    CLK_NAFLL_DISP,
280    CLK_NAFLL_GPU,
281    CLK_NAFLL_MCPU,
282    CLK_NAFLL_BCPU,
283    CLK_PLL_REF,
284    CLK_OSC,
285    CLK_EQOS_RX_INPUT,
286    CLK_DTV_INPUT,
287    CLK_SOR0_PAD_CLKOUT,
288    CLK_SOR1_PAD_CLKOUT,
289    CLK_I2S1_SYNC_INPUT,
290    CLK_I2S2_SYNC_INPUT,
291    CLK_I2S3_SYNC_INPUT,
292    CLK_I2S4_SYNC_INPUT,
293    CLK_I2S5_SYNC_INPUT,
294    CLK_I2S6_SYNC_INPUT,
295    CLK_SPDIFIN_SYNC_INPUT,
296    NCLOCKS
297};
298
299enum clock_gate {
300    CLK_GATE_FUSE,
301    CLK_GATE_GPU,
302    CLK_GATE_PCIE,
303    CLK_GATE_AFI,
304    CLK_GATE_PCIE2_IOBIST,
305    CLK_GATE_PCIERX0,
306    CLK_GATE_PCIERX1,
307    CLK_GATE_PCIERX2,
308    CLK_GATE_PCIERX3,
309    CLK_GATE_PCIERX4,
310    CLK_GATE_PLLC_OUT_ISP,
311    CLK_GATE_PLLC_OUT_VE,
312    CLK_GATE_PLLC_OUT_AON,
313    CLK_GATE_SOR_SAFE,
314    CLK_GATE_I2S2,
315    CLK_GATE_I2S3,
316    CLK_GATE_SPDIF_IN,
317    CLK_GATE_SPDIF_DOUBLER,
318    CLK_GATE_SPI3,
319    CLK_GATE_I2C1,
320    CLK_GATE_I2C5,
321    CLK_GATE_SPI1,
322    CLK_GATE_ISP,
323    CLK_GATE_VI,
324    CLK_GATE_SDMMC1,
325    CLK_GATE_SDMMC2,
326    CLK_GATE_SDMMC4,
327    CLK_GATE_UARTA,
328    CLK_GATE_UARTB,
329    CLK_GATE_HOST1X,
330    CLK_GATE_EMC,
331    CLK_GATE_EXTPERIPH4,
332    CLK_GATE_SPI4,
333    CLK_GATE_I2C3,
334    CLK_GATE_SDMMC3,
335    CLK_GATE_UARTD,
336    CLK_GATE_I2S1,
337    CLK_GATE_DTV,
338    CLK_GATE_TSEC,
339    CLK_GATE_DP2,
340    CLK_GATE_I2S4,
341    CLK_GATE_I2S5,
342    CLK_GATE_I2C4,
343    CLK_GATE_AHUB,
344    CLK_GATE_HDA2CODEC_2X,
345    CLK_GATE_EXTPERIPH1,
346    CLK_GATE_EXTPERIPH2,
347    CLK_GATE_EXTPERIPH3,
348    CLK_GATE_I2C_SLOW,
349    CLK_GATE_SOR1,
350    CLK_GATE_CEC,
351    CLK_GATE_DPAUX1,
352    CLK_GATE_DPAUX,
353    CLK_GATE_SOR0,
354    CLK_GATE_HDA2HDMICODEC,
355    CLK_GATE_SATA,
356    CLK_GATE_SATA_OOB,
357    CLK_GATE_SATA_IOBIST,
358    CLK_GATE_HDA,
359    CLK_GATE_SE,
360    CLK_GATE_APB2APE,
361    CLK_GATE_APE,
362    CLK_GATE_IQC1,
363    CLK_GATE_IQC2,
364    CLK_GATE_PLLREFE_OUT,
365    CLK_GATE_PLLREFE_PLL_REF,
366    CLK_GATE_PLLC4_OUT,
367    CLK_GATE_XUSB,
368    CLK_GATE_XUSB_DEV,
369    CLK_GATE_XUSB_HOST,
370    CLK_GATE_XUSB_SS,
371    CLK_GATE_DSI,
372    CLK_GATE_MIPI_CAL,
373    CLK_GATE_DSIA_LP,
374    CLK_GATE_DSIB,
375    CLK_GATE_DSIB_LP,
376    CLK_GATE_DMIC1,
377    CLK_GATE_DMIC2,
378    CLK_GATE_AUD_MCLK,
379    CLK_GATE_I2C6,
380    CLK_GATE_UART_FST_MIPI_CAL,
381    CLK_GATE_VIC,
382    CLK_GATE_SDMMC_LEGACY_TM,
383    CLK_GATE_NVDEC,
384    CLK_GATE_NVJPG,
385    CLK_GATE_NVENC,
386    CLK_GATE_QSPI,
387    CLK_GATE_VI_I2C,
388    CLK_GATE_HSIC_TRK,
389    CLK_GATE_USB2_TRK,
390    CLK_GATE_MAUD,
391    CLK_GATE_TSECB,
392    CLK_GATE_ADSP,
393    CLK_GATE_ADSPNEON,
394    CLK_GATE_MPHY_L0_RX_SYMB,
395    CLK_GATE_MPHY_L0_RX_LS_BIT,
396    CLK_GATE_MPHY_L0_TX_SYMB,
397    CLK_GATE_MPHY_L0_TX_LS_3XBIT,
398    CLK_GATE_MPHY_L0_RX_ANA,
399    CLK_GATE_MPHY_L1_RX_ANA,
400    CLK_GATE_MPHY_IOBIST,
401    CLK_GATE_MPHY_TX_1MHZ_REF,
402    CLK_GATE_MPHY_CORE_PLL_FIXED,
403    CLK_GATE_AXI_CBB,
404    CLK_GATE_DMIC3,
405    CLK_GATE_DMIC4,
406    CLK_GATE_DSPK1,
407    CLK_GATE_DSPK2,
408    CLK_GATE_I2S6,
409    CLK_GATE_NVDISPLAY_P0,
410    CLK_GATE_NVDISPLAY_DISP,
411    CLK_GATE_NVDISPLAY_DSC,
412    CLK_GATE_NVDISPLAYHUB,
413    CLK_GATE_NVDISPLAY_P1,
414    CLK_GATE_NVDISPLAY_P2,
415    CLK_GATE_TACH,
416    CLK_GATE_EQOS_AXI,
417    CLK_GATE_EQOS_RX,
418    CLK_GATE_UFSHC,
419    CLK_GATE_UFSDEV_REF,
420    CLK_GATE_NVCSI,
421    CLK_GATE_NVCSILP,
422    CLK_GATE_I2C7,
423    CLK_GATE_I2C9,
424    CLK_GATE_I2C12,
425    CLK_GATE_I2C13,
426    CLK_GATE_I2C14,
427    CLK_GATE_PWM1,
428    CLK_GATE_PWM2,
429    CLK_GATE_PWM3,
430    CLK_GATE_PWM5,
431    CLK_GATE_PWM6,
432    CLK_GATE_PWM7,
433    CLK_GATE_PWM8,
434    CLK_GATE_UARTE,
435    CLK_GATE_UARTF,
436    CLK_GATE_DBGAPB,
437    CLK_GATE_BPMP_CPU_NIC,
438    CLK_GATE_BPMP_APB,
439    CLK_GATE_ACTMON,
440    CLK_GATE_AON_CPU_NIC,
441    CLK_GATE_CAN1,
442    CLK_GATE_CAN1_HOST,
443    CLK_GATE_CAN2,
444    CLK_GATE_CAN2_HOST,
445    CLK_GATE_AON_APB,
446    CLK_GATE_UARTC,
447    CLK_GATE_UARTG,
448    CLK_GATE_AON_UART_FST_MIPI_CAL,
449    CLK_GATE_I2C2,
450    CLK_GATE_I2C8,
451    CLK_GATE_I2C10,
452    CLK_GATE_AON_I2C_SLOW,
453    CLK_GATE_SPI2,
454    CLK_GATE_DMIC5,
455    CLK_GATE_AON_TOUCH,
456    CLK_GATE_PWM4,
457    CLK_GATE_TSC,
458    CLK_GATE_MSS_ENCRYPT,
459    CLK_GATE_SCE_CPU_NIC,
460    CLK_GATE_SCE_APB,
461    CLK_GATE_DSIC,
462    CLK_GATE_DSIC_LP,
463    CLK_GATE_DSID,
464    CLK_GATE_DSID_LP,
465    CLK_GATE_PEX_SATA_USB_RX_BYP,
466    CLK_GATE_SPDIF_OUT,
467    CLK_GATE_EQOS_PTP_REF,
468    CLK_GATE_EQOS_TX,
469    CLK_GATE_USB2_HSIC_TRK,
470    CLK_GATE_XUSB_CORE_SS,
471    CLK_GATE_XUSB_CORE_DEV,
472    CLK_GATE_XUSB_FALCON,
473    CLK_GATE_XUSB_FS,
474    CLK_GATE_PLL_A_OUT0,
475    CLK_GATE_SYNC_I2S1,
476    CLK_GATE_SYNC_I2S2,
477    CLK_GATE_SYNC_I2S3,
478    CLK_GATE_SYNC_I2S4,
479    CLK_GATE_SYNC_I2S5,
480    CLK_GATE_SYNC_I2S6,
481    CLK_GATE_SYNC_DSPK1,
482    CLK_GATE_SYNC_DSPK2,
483    CLK_GATE_SYNC_DMIC1,
484    CLK_GATE_SYNC_DMIC2,
485    CLK_GATE_SYNC_DMIC3,
486    CLK_GATE_SYNC_DMIC4,
487    CLK_GATE_SYNC_SPDIF,
488    CLK_GATE_PLLREFE_OUT_GATED,
489    CLK_GATE_PLLREFE_OUT1,
490    CLK_GATE_PLLD_OUT1,
491    CLK_GATE_PLLP_OUT0,
492    CLK_GATE_PLLP_OUT5,
493    CLK_GATE_PLLA,
494    CLK_GATE_ACLK,
495    CLK_GATE_PLL_U_48M,
496    CLK_GATE_PLL_U_480M,
497    CLK_GATE_PLLC4_OUT0,
498    CLK_GATE_PLLC4_OUT1,
499    CLK_GATE_PLLC4_OUT2,
500    CLK_GATE_PLLC4_OUT_MUX,
501    CLK_GATE_DFLLDISP_DIV,
502    CLK_GATE_PLLDISPHUB_DIV,
503    CLK_GATE_PLLP_DIV8,
504    CLK_GATE_BPMP_NIC,
505    CLK_GATE_PLL_A_OUT1,
506    CLK_GATE_GPC2CLK,
507    CLK_GATE_KFUSE,
508    CLK_GATE_PLLE_PWRSEQ,
509    CLK_GATE_PLLREFE_REF,
510    CLK_GATE_SOR0_OUT,
511    CLK_GATE_SOR1_OUT,
512    CLK_GATE_PLLREFE_OUT1_DIV5,
513    CLK_GATE_UTMIP_PLL_PWRSEQ,
514    CLK_GATE_PEX_USB_PAD0_MGMT,
515    CLK_GATE_PEX_USB_PAD1_MGMT,
516    CLK_GATE_UPHY_PLL0_PWRSEQ,
517    CLK_GATE_UPHY_PLL1_PWRSEQ,
518    CLK_GATE_PLLREFE_PLLE_PASSTHROUGH,
519    CLK_GATE_PLLREFE_PEX,
520    CLK_GATE_PLLREFE_IDDQ,
521    CLK_GATE_QSPI_OUT,
522    CLK_GATE_GPCCLK,
523    CLK_GATE_AON_NIC,
524    CLK_GATE_SCE_NIC,
525    CLK_GATE_PLLE,
526    CLK_GATE_PLLC,
527    CLK_GATE_PLLP,
528    CLK_GATE_PLLD,
529    CLK_GATE_PLLD2,
530    CLK_GATE_PLLREFE_VCO,
531    CLK_GATE_PLLC2,
532    CLK_GATE_PLLC3,
533    CLK_GATE_PLLDP,
534    CLK_GATE_PLLC4_VCO,
535    CLK_GATE_PLLA1,
536    CLK_GATE_PLLNVCSI,
537    CLK_GATE_PLLDISPHUB,
538    CLK_GATE_PLLD3,
539    CLK_GATE_PLLBPMPCAM,
540    CLK_GATE_PLLAON,
541    CLK_GATE_PLLU,
542    CLK_GATE_PLLC4_VCO_DIV2,
543    CLK_GATE_NAFLL_AXI_CBB,
544    CLK_GATE_NAFLL_BPMP,
545    CLK_GATE_NAFLL_ISP,
546    CLK_GATE_NAFLL_NVDEC,
547    CLK_GATE_NAFLL_NVENC,
548    CLK_GATE_NAFLL_NVJPG,
549    CLK_GATE_NAFLL_SCE,
550    CLK_GATE_NAFLL_SE,
551    CLK_GATE_NAFLL_TSEC,
552    CLK_GATE_NAFLL_TSECB,
553    CLK_GATE_NAFLL_VI,
554    CLK_GATE_NAFLL_VIC,
555    CLK_GATE_NAFLL_DISP,
556    CLK_GATE_NAFLL_GPU,
557    CLK_GATE_NAFLL_MCPU,
558    CLK_GATE_NAFLL_BCPU,
559    CLK_GATE_32K,
560    CLK_GATE_M,
561    CLK_GATE_PLL_REF,
562    CLK_GATE_OSC,
563    CLK_GATE_EQOS_RX_INPUT,
564    CLK_GATE_DTV_INPUT,
565    CLK_GATE_SOR0_PAD_CLKOUT,
566    CLK_GATE_SOR1_PAD_CLKOUT,
567    CLK_GATE_I2S1_SYNC_INPUT,
568    CLK_GATE_I2S2_SYNC_INPUT,
569    CLK_GATE_I2S3_SYNC_INPUT,
570    CLK_GATE_I2S4_SYNC_INPUT,
571    CLK_GATE_I2S5_SYNC_INPUT,
572    CLK_GATE_I2S6_SYNC_INPUT,
573    CLK_GATE_SPDIFIN_SYNC_INPUT,
574    NCLKGATES
575};
576