1/* 2 * (C) Copyright 2011 Michal Simek 3 * Copyright 2017, DornerWorks, Ltd. 4 * 5 * Ported to seL4 6 * 7 * Michal SIMEK <monstr@monstr.eu> 8 * 9 * Based on Xilinx gmac driver: 10 * (C) Copyright 2011 Xilinx 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14#pragma once 15 16#include <platsupport/io.h> 17 18/* Bit/mask specification */ 19#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 20#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 21#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 22#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 23#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 24 25#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 26#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 27#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 28 29#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 30#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 31#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 32 33/* Wrap bit, last descriptor */ 34#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 35#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 36#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 37 38#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 39#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 40#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 41#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 42 43#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 44#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 45#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 46#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 47#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ 48#define ZYNQ_GEM_NWCFG_COPY_ALL 0x000000010 /* Promiscuous Mode */ 49 50#ifdef CONFIG_ARM64 51# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 52#else 53# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 54#endif 55 56#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 57 ZYNQ_GEM_NWCFG_FDEN | \ 58 ZYNQ_GEM_NWCFG_FSREM | \ 59 ZYNQ_GEM_NWCFG_MDCCLKDIV) 60 61#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 62 63#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 64/* Use full configured addressable space (8 Kb) */ 65#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 66/* Use full configured addressable space (4 Kb) */ 67#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 68/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 69#define ZYNQ_GEM_DMACR_RXBUF 0x00180000 70 71#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 72 ZYNQ_GEM_DMACR_RXSIZE | \ 73 ZYNQ_GEM_DMACR_TXSIZE | \ 74 ZYNQ_GEM_DMACR_RXBUF) 75 76#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 77 78/* Use MII register 1 (MII status register) to detect PHY */ 79#define PHY_DETECT_REG 1 80 81/* Mask used to verify certain PHY features (or register contents) 82 * in the register above: 83 * 0x1000: 10Mbps full duplex support 84 * 0x0800: 10Mbps half duplex support 85 * 0x0008: Auto-negotiation support 86 */ 87#define PHY_DETECT_MASK 0x1808 88 89/* TX BD status masks */ 90#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 91#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 92#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 93 94/* Clock frequencies for different speeds */ 95#define ZYNQ_GEM_FREQUENCY_10 2500000UL 96#define ZYNQ_GEM_FREQUENCY_100 25000000UL 97#define ZYNQ_GEM_FREQUENCY_1000 125000000UL 98 99#define ZYNQ_GEM_IXR_FRAMERX (1 << 1) 100#define ZYNQ_GEM_IXR_TXCOMPLETE (1 << 7) 101 102#define ZYNQ_GEM_TXSR_TXGO (1 << 3) 103 104/* Device registers */ 105struct zynq_gem_regs { 106 u32 nwctrl; /* 0x0 - Network Control reg */ 107 u32 nwcfg; /* 0x4 - Network Config reg */ 108 u32 nwsr; /* 0x8 - Network Status reg */ 109 u32 reserved1; 110 u32 dmacr; /* 0x10 - DMA Control reg */ 111 u32 txsr; /* 0x14 - TX Status reg */ 112 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 113 u32 txqbase; /* 0x1c - TX Q Base address reg */ 114 u32 rxsr; /* 0x20 - RX Status reg */ 115 u32 isr; 116 u32 ier; 117 u32 idr; /* 0x2c - Interrupt Disable reg */ 118 u32 reserved3; 119 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 120 u32 reserved4[18]; 121 u32 hashl; /* 0x80 - Hash Low address reg */ 122 u32 hashh; /* 0x84 - Hash High address reg */ 123#define LADDR_LOW 0 124#define LADDR_HIGH 1 125 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 126 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 127 u32 reserved6[18]; 128#define STAT_SIZE 44 129 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 130 u32 reserved7[164]; 131 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 132 u32 reserved8[15]; 133 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 134}; 135 136/* BD descriptors */ 137struct emac_bd { 138 u32 addr; /* Next descriptor pointer */ 139 u32 status; 140}; 141 142#define RX_BUF 32 143/* Page table entries are set to 1MB, or multiples of 1MB 144 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 145 */ 146#define BD_SPACE 0x100000 147/* BD separation space */ 148#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 149 150/* Setup the first free TX descriptor */ 151#define TX_FREE_DESC 2 152 153struct eth_device *zynq_gem_initialize(phys_addr_t base_addr, 154 int phy_addr, u32 emio); 155int zynq_gem_init(struct eth_device *dev); 156int zynq_gem_setup_mac(struct eth_device *dev); 157int zynq_gem_start_send(struct eth_device *dev); 158int zynq_gem_recv_enabled(struct eth_device *dev); 159void zynq_gem_recv_enable(struct eth_device *dev); 160void zynq_gem_halt(struct eth_device *dev); 161void zynq_set_gem_ioops(ps_io_ops_t *io_ops); 162void zynq_gem_prom_enable(struct eth_device *dev); 163void zynq_gem_prom_disable(struct eth_device *dev); 164