1/*
2 * Copyright 2019, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12
13#include <assert.h>
14#include <stdbool.h>
15
16#include <utils/util.h>
17
18#include "../../../irqchip.h"
19
20#define ARM_GIC_INT_CELL_COUNT 3
21
22#define SPI_IRQ_TYPE 0
23#define PPI_IRQ_TYPE 1
24
25/* These offsets are in the context of the normal 'interrupts' property,
26 * for the 'interrupts-extended' property, we add one to each */
27typedef enum {
28    INT_TYPE_OFFSET,
29    INT_OFFSET
30} interrupt_cell_offset;
31
32typedef enum {
33    EXT_INT_CONTROLLER_OFFSET,
34    EXT_INT_TYPE_OFFSET,
35    EXT_INT_OFFSET
36} ext_interrupt_cell_offset;
37
38/* Note for extended interrupts, we expect the common case that the interrupt controller phandles
39 * for each block in the property is the same as the GICs phandle */
40static int parse_arm_gic_interrupts(char *dtb_blob, int node_offset, int intr_controller_phandle,
41                                    irq_walk_cb_fn_t callback, void *token)
42{
43    bool is_extended = false;
44    int prop_len = 0;
45    const void *interrupts_prop = get_interrupts_prop(dtb_blob, node_offset, &is_extended, &prop_len);
46    assert(interrupts_prop != NULL);
47    int total_cells = prop_len / sizeof(uint32_t);
48
49    int stride = ARM_GIC_INT_CELL_COUNT + (is_extended == true);
50    int num_interrupts = total_cells / stride;
51
52    assert(total_cells % stride == 0);
53
54    for (int i = 0; i < num_interrupts; i++) {
55        ps_irq_t curr_irq = {0};
56        const void *curr = interrupts_prop + (i * stride * sizeof(uint32_t));
57        curr_irq.type = PS_INTERRUPT;
58        uint32_t irq_type = 0;
59        uint32_t irq = 0;
60        if (is_extended) {
61            if (READ_CELL(1, curr, EXT_INT_CONTROLLER_OFFSET) != intr_controller_phandle) {
62                /* Bail, we hit the uncommon case where this device has interrupts routed to
63                 * different interrupt controllers */
64                return -EINVAL;
65            }
66            irq_type = READ_CELL(1, curr, EXT_INT_TYPE_OFFSET);
67            irq = READ_CELL(1, curr, EXT_INT_OFFSET);
68        } else {
69            irq_type = READ_CELL(1, curr, INT_TYPE_OFFSET);
70            irq = READ_CELL(1, curr, INT_OFFSET);
71        }
72        curr_irq.irq.number = irq + (irq_type == SPI_IRQ_TYPE ? 32 : 0);
73        int error = callback(curr_irq, i, num_interrupts, token);
74        if (error) {
75            return error;
76        }
77    }
78
79    return 0;
80}
81
82char *arm_gic_compatible_list[] = {
83    "arm,gic-400",
84    "arm,cortex-a9-gic",
85    "arm,cortex-a15-gic",
86    NULL
87};
88DEFINE_IRQCHIP_PARSER(arm_gic, arm_gic_compatible_list, parse_arm_gic_interrupts);
89