1/* 2 * Copyright 2020, DornerWorks 3 * 4 * This software may be distributed and modified according to the terms of 5 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 6 * See "LICENSE_BSD2.txt" for details. 7 * 8 * @TAG(DORNERWORKS_BSD) 9 */ 10 11#pragma once 12#include <autoconf.h> 13 14enum chardev_id { 15 UART0, 16 UART1, 17 UART2, 18 UART3, 19 PS_SERIAL_DEFAULT = UART3 20}; 21 22/* 23 * Depending on whether or not the Divisor Latch Access Bit (DLAB) is set 24 * in the line_control (LCR) register (bit 7) the first two registers will 25 * have different functions. 26 * If DLAB is not set in the LCR: 27 * reg[0]: receive or transmit buffer 28 * If written to: tranmit buffer 29 * If read : receive buffer 30 * reg[1]: interrupt enable register 31 * If the DLAB is set in the LCR: 32 * reg[0]: LSB of the divisor 33 * reg[1]: MSB of the divisor 34 * The interrupt id and fifo control registers are related 35 * If the 3rd register is written to, it affects the fifo control 36 * If it is read from, the interrupt id register contents are returned 37 */ 38struct uart { 39 union { 40 uint32_t rx_buffer; 41 uint32_t tx_buffer; 42 uint32_t divisor_latch_lsb; 43 }; 44 union { 45 uint32_t interrupt_enable; 46 uint32_t divisor_latch_msb; 47 }; 48 union { 49 uint32_t interrupt_id; 50 uint32_t fifo_control; 51 }; 52 uint32_t line_control ; 53 uint32_t modem_control ; 54 uint32_t line_status; 55 uint32_t modem_status; 56 uint32_t scratch; 57 uint32_t RESERVED ; 58 uint32_t multi_mode_interrupt_enable; 59 uint32_t multi_mode_interrupt_id; 60 uint32_t RESERVED_1 ; 61 uint32_t multi_mode_control_0; 62 uint32_t multi_mode_control_1; 63 uint32_t multi_mode_control_2; 64 uint32_t fractional_divisor; 65 uint32_t glitch_filter; 66 uint32_t transmitter_time_guard; 67 uint32_t receiver_time_out; 68 uint32_t address; 69}; 70typedef volatile struct uart uart_regs_t; 71 72 73#define UART0_PADDR 0x20000000 74#define UART1_PADDR 0x20100000 75#define UART2_PADDR 0x20102000 76#define UART3_PADDR 0x20104000 77 78#define UART0_IRQ 90 79#define UART1_IRQ 91 80#define UART2_IRQ 92 81#define UART3_IRQ 93 82 83#define DEFAULT_SERIAL_PADDR UART3_PADDR 84#define DEFAULT_SERIAL_INTERRUPT UART3_IRQ 85 86/* Relevant Register Masks * 87/ 88/* Line Control Register */ 89#define LCR_WORD_LEN_5 0b00 90#define LCR_WORD_LEN_6 0b01 91#define LCR_WORD_LEN_7 0b10 92#define LCR_WORD_LEN_8 0b11 93#define LCR_DIV_LATCH_MASK (1 << 7) 94 95/* Modem Control Register */ 96#define MCR_DTR_MASK (1 << 0) 97#define MCR_RTS_MASK (1 << 1) 98 99/* Multi Mode Control Register 0 */ 100#define MM0_ENABLE_FRAC_MASK (1 << 7) 101 102/* Line Status Register */ 103#define LSR_DATA_READY_MASK (1 << 0) 104#define LSR_TX_HOLD_REG_EMPTY_MASK (1 << 5) 105