1272343Sngie/*
2272343Sngie * Copyright 2014, General Dynamics C4 Systems
3272343Sngie *
4272343Sngie * SPDX-License-Identifier: GPL-2.0-only
5272343Sngie */
6272343Sngie
7272343Sngie#include <arch/machine.h>
8272343Sngie
9static inline word_t readACR(void)
10{
11    word_t ACR;
12    asm volatile("mrc p15,0,%0,c1,c0,1" : "=r"(ACR));
13    return ACR;
14}
15
16static inline void writeACR(word_t ACR)
17{
18    asm volatile("mcr p15,0,%0,c1,c0,1" : : "r"(ACR));
19}
20
21void initL2Cache(void)
22{
23    cleanInvalidateL1Caches();
24
25    /*
26     * Set the L2EN bit in the Auxially Control Register.
27     *
28     * We assume the C bit is already set in the system control register (from
29     * head.S), and that the L2 Cache Auxilliary Control Register is correct
30     * (as per reset).
31     */
32    writeACR(readACR() | 0x2);
33
34    cleanInvalidateL1Caches();
35}
36
37void plat_cleanL2Range(paddr_t start, paddr_t end) {}
38void plat_invalidateL2Range(paddr_t start, paddr_t end) {}
39void plat_cleanInvalidateL2Range(paddr_t start, paddr_t end) {}
40void plat_cleanInvalidateL2Cache(void) {}
41