1/* 2 * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7#pragma once 8 9#include <plat/machine/devices_gen.h> 10 11/*the paddr address of the TX2 SMMU*/ 12#define SMMU_TX2_PADDR 0x12000000 13 14#define SMMU_PAGE_4KB 0x1000 15#define SMMU_PAGE_64KB 0x10000 16 17/*the high-level physical address layout according to SMMU definition*/ 18#define SMMU_GLOBAL_SIZE(num_page, page_size) ((num_page) * (page_size)) 19#define SMMU_CB_SIZE(num_page, page_size) ((num_page) * (page_size)) 20#define SMMU_CB_BASE_PADDR(global_size) (SMMU_TX2_PADDR + (global_size)) 21 22/*SMMU's physical address space layout, defined by SMMU v2 standard*/ 23#define SMMU_GR0_PADDR SMMU_TX2_PADDR 24#define SMMU_GR1_PADDR(page_size) ((SMMU_GR0_PADDR) + 1 * (page_size)) 25#define SMMU_GID_PADDR(page_size) ((SMMU_GR0_PADDR) + 2 * (page_size)) 26#define SMMU_PM_PADDR(page_size) ((SMMU_GR0_PADDR) + 3 * (page_size)) 27#define SMMU_SSD_PADDR(page_size) ((SMMU_GR0_PADDR) + 4 * (page_size)) 28#define SMMU_CBn_PADDR(cb_base, n ,page_size) ((cb_base) + n * (page_size)) 29 30/* SMMU's virtual address space layout in kernel address space, 31 * mapped by boot code.*/ 32#define SMMU_GR0_PPTR SMMU_PPTR 33#define SMMU_GR1_PPTR (SMMU_PPTR + 1 * (SMMU_PAGE_4KB)) 34#define SMMU_GID_PPTR (SMMU_PPTR + 2 * (SMMU_PAGE_4KB)) 35#define SMMU_PM_PPTR (SMMU_PPTR + 3 * (SMMU_PAGE_4KB)) 36#define SMMU_SSD_PPTR (SMMU_PPTR + 4 * (SMMU_PAGE_4KB)) 37#define SSMU_CB_BASE_PPTR (SMMU_PPTR + 5 * (SMMU_PAGE_4KB)) 38#define SMMU_CBn_BASE_PPTR(n) ((SSMU_CB_BASE_PPTR) + (n) * (SMMU_PAGE_4KB)) 39 40/*global register space 0 registers*/ 41#define SMMU_sCR0 0x000 42#define SMMU_SCR1 0x004 43#define SMMU_sCR2 0x008 44#define SMMU_sACR 0x010 45#define SMMU_IDR0 0x020 46#define SMMU_IDR1 0x024 47#define SMMU_IDR2 0x028 48#define SMMU_IDR3 0x02c 49#define SMMU_IDR4 0x030 50#define SMMU_IDR5 0x034 51#define SMMU_IDR6 0x038 52#define SMMU_IDR7 0x03c 53#define SMMU_sGFAR 0x040 54#define SMMU_sGFSR 0x048 55#define SMMU_sGFSRRESTORE 0x04c 56#define SMMU_sGFSYNR0 0x050 57#define SMMU_sGFSYNR1 0x054 58#define SMMU_sGFSYNR2 0x058 59#define SMMU_STLBIALL 0x060 60#define SMMU_TLBIVMID 0x064 61#define SMMU_TLBIALLNSNH 0x068 62#define SMMU_TLBIALLH 0x06c 63#define SMMU_sTLBGSYNC 0x070 64#define SMMU_sTLBGSTATUS 0x074 65#define SMMU_TLBIVAH 0x078 66#define SMMU_STLBIVALM 0x0a0 67#define SMMU_STLBIVAM 0x0a8 68#define SMMU_TLBIVALH64 0x0b0 69#define SMMU_TLBIVMIDS1 0x0b8 70#define SMMU_STLBIALLM 0x0bc 71#define SMMU_TLBIVAH64 0x0c0 72#define SMMU_sGATS1UR 0x100 73#define SMMU_sGATS1UW 0x108 74#define SMMU_sGATS1PR 0x110 75#define SMMU_sGATS1PW 0x118 76#define SMMU_sGATS12UR 0x120 77#define SMMU_sGATS12UW 0x128 78#define SMMU_sGATS12PR 0x130 79#define SMMU_sGATS12PW 0x138 80#define SMMU_sGPAR 0x180 81#define SMMU_sGATSR 0x188 82 83/*SMMU_SMRn, stream matching register 0 to 127*/ 84#define SMMU_SMRn(n) (0x800 + (n) * 0x4) 85 86/*SMMU_S2CRn, stream-to-context register 0 to 127*/ 87#define SMMU_S2CRn(n) (0xc00 + (n) * 0x4) 88 89/*global register space 1*/ 90/*SMMU_CBARn, context bank attribute register 0 to 127*/ 91#define SMMU_CBARn(n) (0x000 + (n) * 0x4) 92 93/*SMMU_CBFRSYNRAn, context bank fault restricted syndrome register A 0 to 127*/ 94#define SMMU_CBFRSYNRAn(n) (0x400 + (n) * 0x4) 95 96/*SMMU_CBA2Rn, context bank attribute registers 0 to 127*/ 97#define SMMU_CBA2Rn(n) (0x800 + (n) * 0x4) 98 99/*stage 1 and stage 2 translation context bank address space*/ 100#define SMMU_CBn_SCTLR 0x000 101#define SMMU_CBn_ACTLR 0x004 102#define SMMU_CBn_RESUME 0x008 103#define SMMU_CBn_TCR2 0x010 104#define SMMU_CBn_TTBR0 0x020 105#define SMMU_CBn_TTBR1 0x028 106#define SMMU_CBn_TCR 0x030 107#define SMMU_CBn_CONTEXTIDR 0x034 108 109/*the SMMU_CBn_MAIRm registers are used for AArch32 Long-descriptor or the AArch64*/ 110#define SMMU_CBn_MAIR0 0x038 111#define SMMU_CBn_MAIR1 0x03c 112/*the SMMU_CBn_PRRR and SMMU_CBn_NMRR registers are used for AArch32*/ 113#define SMMU_CBn_PRRR 0x038 114#define SMMU_CBn_NMRR 0x03c 115 116#define SMMU_CBn_PAR 0x050 117#define SMMU_CBn_FSR 0x058 118#define SMMU_CBn_FSRRESTORE 0x05c 119#define SMMU_CBn_FAR 0x060 120#define SMMU_CBn_FSYNR0 0x068 121#define SMMU_CBn_FSYNR1 0x06c 122#define SMMU_CBn_IPAFAR 0x070 123 124#define SMMU_CBn_TLBIVA 0x600 125#define SMMU_CBn_TLBIVAA 0x608 126#define SMMU_CBn_TLBIASID 0x610 127#define SMMU_CBn_TLBIALL 0x618 128#define SMMU_CBn_TLBIVAL 0x620 129#define SMMU_CBn_TLBIVAAL 0x628 130#define SMMU_CBn_TLBIIPAS2 0x630 131#define SMMU_CBn_TLBIIPAS2L 0x638 132#define SMMU_CBn_TLBSYNC 0x7f0 133#define SMMU_CBn_TLBSTATUS 0x7f4 134 135/*SMMU_CR0 non-secure register 0 bit assignments*/ 136#define CR0_VMID16EN BIT(31) 137#define CR0_HYPMODE BIT(30) 138#define CR0_WACFG(v) ((v) & 0x3 << 26) 139#define CR0_RACFG(v) ((v) & 0x3 << 24) 140#define CR0_SHCFG(v) ((v) & 0x3 << 22) 141#define CR0_SMCFCFG BIT(21) 142#define CR0_MTCFG BIT(20) 143#define CR0_MemAttr(v) ((v) & 0xf << 16) 144#define CR0_BSU(v) ((v) & 0x3 << 14) 145#define CR0_FB BIT(13) 146#define CR0_PTM BIT(12) 147#define CR0_VMIDPNE BIT(11) 148#define CR0_USFCFG BIT(10) 149#define CR0_GSE BIT(9) 150#define CR0_STALLD BIT(8) 151#define CR0_TRANSIENTCFG(v) ((v) & 0x3 << 6) 152#define CR0_GCFGFIE BIT(5) 153#define CR0_GCFGFRE BIT(4) 154#define CR0_EXIDENABLE BIT(3) 155#define CR0_GFIE BIT(2) 156#define CR0_GFRE BIT(1) 157#define CR0_CLIENTPD BIT(0) 158#define CR0_BSU_ALL 3 159 160/*SMMU_IDR0 (read only) read mask*/ 161#define IDR0_SES BIT(31) 162#define IDR0_S1TS BIT(30) 163#define IDR0_S2TS BIT(29) 164#define IDR0_NTS BIT(28) 165#define IDR0_SMS BIT(27) 166#define IDR0_ATOSNS BIT(26) 167#define IDR0_PTFS (0x3 << 24) 168#define IDR0_PTFS_VAL(v) ((v) >> 24) 169#define IDR0_NUMIRPT (0xff << 16) 170#define IDR0_NUMIRPT_VAL(v) ((v) >> 16) 171#define IDR0_EXSMRGS BIT(15) 172#define IDR0_CTTW BIT(14) 173#define IDR0_BTM BIT(13) 174#define IDR0_NUMSIDB (0xf << 9) 175#define IDR0_NUMSIDB_VAL(v) ((v) >> 9) 176#define IDR0_EXIDS BIT(8) 177#define IDR0_NUMSMRG 0xff 178 179/*PTFS bits*/ 180#define PTFS_AARCH32S_AARCH32L 0x0 181#define PTFS_AARCH32L_ONLY 0x1 182#define PTFS_NO_AARCH32 0x2 183 184/*SMMU_IDR1 (read only) read mask*/ 185#define IDR1_PAGESIZE BIT(31) 186#define IDR1_NUMPAGENDXB (0x7 << 28) 187#define IDR1_NUMPAGENDXB_VAL(v) ((v) >> 28) 188#define IDR1_HAFDBS (0x3 << 24) 189#define IDR1_NUMS2CB (0xff << 16) 190#define IDR1_NUMS2CB_VAL(v) ((v) >> 16) 191#define IDR1_SMCD BIT(15) 192#define IDR1_SSDTP (0x3 << 12) 193#define IDR1_NUMSSDNDXB (0xf << 8) 194#define IDR1_NUMCB 0xff 195 196/*SMMU_IDR2 (read only) read mask*/ 197#define IDR2_VMID16S BIT(15) 198#define IDR2_PTFSV8_64 BIT(14) 199#define IDR2_PTFSV8_16 BIT(13) 200#define IDR2_PTFSV8_4 BIT(12) 201#define IDR2_UBS (0xf << 8) 202#define IDR2_UBS_VAL(v) ((v) >> 8) 203#define IDR2_OAS (0xf << 4) 204#define IDR2_OAS_VAL(v) ((v) >> 4) 205#define IDR2_IAS 0xf 206 207/*OAS bits*/ 208#define IDR2_OAS_32 0x0 209#define IDR2_OAS_36 0x1 210#define IDR2_OAS_40 0x2 211#define IDR2_OAS_42 0x3 212#define IDR2_OAS_44 0x4 213#define IDR2_OAS_48 0x5 214 215/*IAS bits*/ 216#define IDR2_IAS_32 0x0 217#define IDR2_IAS_36 0x1 218#define IDR2_IAS_40 0x2 219#define IDR2_IAS_42 0x3 220#define IDR2_IAS_44 0x4 221#define IDR2_IAS_48 0x5 222 223/*SMMU_IDR7*/ 224#define IDR7_MAJOR (0xf << 4) 225#define IDR7_MAJOR_VAL(v) ((v) >> 4) 226#define IDR7_MINOR (0xf) 227 228/*SMMU_sGFSR r/w bit mask, write 1 to clear*/ 229#define GFSR_MULTI BIT(31) 230#define GFSR_UUT BIT(8) 231#define GFSR_PF BIT(7) 232#define GFSR_EF BIT(6) 233#define GFSR_CAF BIT(5) 234#define GFSR_UCIF BIT(4) 235#define GFSR_UCBF BIT(3) 236#define GFSR_SMCF BIT(2) 237#define GFSR_USF BIT(1) 238#define GFSR_ICF BIT(0) 239 240/*SMMU_S2CRn, r/w bit mask for translation context*/ 241#define S2CR_TRANSIENTCFG_SET(v) ((v) << 28) 242#define S2CR_INSTCFG_SET(v) ((v) << 26) 243#define S2CR_PRIVCFG_SET(v) ((v) << 24) 244#define S2CR_WACFG_SET(v) ((v) << 22) 245#define S2CR_RACFG_SET(v) ((v) << 20) 246#define S2CR_NSCFG_SET(v) ((v) << 18) 247#define S2CR_TYPE_SET(v) ((v) << 16) 248#define S2CR_MemAttr_SET(v) ((v) << 12) 249#define S2CR_MTCFG_SET(v) ((v) << 11) 250#define S2CR_EXIDVALID_SET(v) ((v) << 10) 251#define S2CR_SHCFG_SET(v) ((v) << 8) 252#define S2CR_CBNDX_SET(v) ((v) & 0xff) 253 254/*SMMU_S2CRn PRIVCFG values*/ 255#define S2CR_PRIVCFG_DEFAULT 0x0 256 257/*SMMU_S2CRn type values*/ 258#define S2CR_TYPE_CB 0x0 259#define S2CR_TYPE_BYPASS 0x1 260#define S2CR_TYPE_FAULT 0x2 261 262/*SMMU_SMRn, r/w bit mask for stream match*/ 263#define SMR_VALID_SET(v) ((v) << 31) 264#define SMR_MASK_SET(v) ((v) & 0x7fff << 16) 265#define SMR_ID_SET(v) ((v) & 0x7fff) 266/*valid /invalid*/ 267#define SMR_VALID_EN 0x1 268#define SMR_VALID_DIS 0x0 269 270/*SMMU_ACR, SMMU-500*/ 271#define ACR_CACHE_LOCK BIT(26) 272#define ACR_S2CRB_TLBEN BIT(10) 273#define ACR_SMTNMB_TLBEN BIT(8) 274 275/*SMMU_CBn_FSR, write 1 to clear*/ 276#define CBn_FSR_MULTI BIT(31) 277#define CBn_FSR_SS BIT(30) 278#define CBn_FSR_UUT BIT(8) 279#define CBn_FSR_ASF BIT(7) 280#define CBn_FSR_TLBLKF BIT(6) 281#define CBn_FSR_TLBLMCF BIT(5) 282#define CBn_FSR_EF BIT(4) 283#define CBn_FSR_PF BIT(3) 284#define CBn_FSR_AFF BIT(2) 285#define CBn_FSR_TF BIT(1) 286 287#define CBn_FSR_CLEAR_ALL (CBn_FSR_MULTI | CBn_FSR_SS | \ 288 CBn_FSR_UUT | CBn_FSR_ASF | CBn_FSR_TLBLKF | \ 289 CBn_FSR_TLBLMCF | CBn_FSR_EF | CBn_FSR_PF | \ 290 CBn_FSR_AFF | CBn_FSR_TF) 291 292/*SMMU_CBn_ACTLR defined in SMMU500*/ 293#define CBn_ACTLR_CPRE BIT(1) 294#define CBn_ACTLR_CMTLB BIT(0) 295 296/*mask for invalidate all TLB entries, used by GR0 registers*/ 297#define SMMU_TLB_INVALL_MASK 0xffffffff 298 299/*mask for init the TLB sync msg*/ 300#define SMMU_TLB_SYNC_MASK 0xffffffff 301 302/*TLB sync status used in SMMU_sTLBGSTATUS and SMMU_CBn_TLBSTATUS*/ 303#define TLBSTATUS_GSACTIVE BIT(0) 304/*the kernel loops N times before declear a TLB invalidation failure*/ 305#define TLBSYNC_LOOP 1000 306 307 308 309/*SMMU_CBARn*/ 310#define CBARn_TYPE_SET(v) ((v) << 16) 311#define CBARn_BPSHCFG_SET(v) ((v) << 8) 312#define CBARn_VMID_SET(v) ((v) & 0xff) 313 314#define CBARn_TYPE_STAGE2 0 315#define CBARn_TYPE_STAGE1 1 /*stage 1 with stage 2 by pass*/ 316 317#define CBARn_BPSHCFG_OUTER 1 318#define CBARn_BPSHCFG_INNER 2 319#define CBARn_BPSHCFG_NONE 3 320 321#define CBARn_MemAttr_SET(v) ((v) << 12) 322#define MemAttr_OWB_IWB 0xf /*outer & inner write-back cacheable*/ 323 324/*SMMU_CBA2Rn*/ 325#define CBA2Rn_VMID_SET(v) (((v) & 0xffff) << 16) 326#define CBA2Rn_VA64_SET 1 327 328/*SMMU_CBn_TCR stage1/2 when SMMU_CBn_CBA2R.VA64 is 1*/ 329#define CBn_TCR_TG1_SET(v) ((v) << 30) 330#define CBn_TCR_SH1_SET(v) ((v) << 28) 331#define CBn_TCR_ORGN1_SET(v) ((v) << 26) 332#define CBn_TCR_IRGN1_SET(v) ((v) << 24) 333#define CBn_TCR_EPD1_DIS (1 << 23) /*translation disabled for TTBR1 region*/ 334#define CBn_TCR_A1_EN (1 << 22) 335#define CBn_TCR_T1SZ_SET(v) (((v) & 0x3f) << 16) 336#define CBn_TCR_TG0_SET(v) ((v) << 14) 337#define CBn_TCR_SH0_SET(v) ((v) << 12) 338#define CBn_TCR_ORGN0_SET(v) ((v) << 10) 339#define CBn_TCR_IRGN0_SET(v) ((v) << 8) 340#define CBn_TCR_T0SZ_SET(v) ((v) & 0x3f) 341 342 343#define CBn_TCR_TG_4K 0 344#define CBn_TCR_TG_64K 1 345#define CBn_TCR_TG_16K 2 346 347#define CBn_TCR_SH_NONE 0 348#define CBn_TCR_SH_OUTER 2 349#define CBn_TCR_SH_INNER 3 350 351#define CBn_TCR_GN_NCACHE 0 352#define CBn_TCR_GN_WB_WA_CACHE 1 353#define CBn_TCR_GN_WT_CACHE 2 354#define CBn_TCR_GN_WB_NWA_CACHE 3 355 356/*SMMU_CBn_TCR stage 2 when SMMU_CBn_CBA2R.VA64 is 1*/ 357#define CBn_TCR_PASize_SET(v) ((v) << 16) 358#define CBn_TCR_SL0_SET(v) ((v) << 6) 359#define CBn_TCR_SL0_4KB_L2 0 360#define CBn_TCR_SL0_4KB_L1 1 361#define CBn_TCR_SL0_4KB_L0 2 362 363/*SMMU_CBn_TCR2*/ 364#define CBn_TCR2_SEP_SET(v) ((v) << 15) 365#define CBn_TCR2_AS_SET(v) ((v) << 4) 366#define CBn_TCR2_PASize_SET(v) (v) 367 368 369#define CBn_TCR2_SEP_UPSTREAM_SIZE 7 370#define CBn_TCR2_AS_16 1 371#define CBn_TCR2_PASize_32 0 372#define CBn_TCR2_PASize_36 1 373#define CBn_TCR2_PASize_40 2 374#define CBn_TCR2_PASize_42 3 375#define CBn_TCR2_PASize_44 4 376#define CBn_TCR2_PASize_48 5 377 378 379 380/*SMMU_CBn_TTBRm*/ 381#define CBn_TTBRm_ASID_SET(v) (((v) & 0xffffull) << 48) 382 383/*SMMU_CBn_MAIRm, 384this is the same as the MAIR in core*/ 385 386/*MAIR0*/ 387#define CBn_MAIRm_ATTR_DEVICE_nGnRnE 0x00 388#define CBn_MAIRm_ATTR_ID_DEVICE_nGnRnE 0 389 390#define CBn_MAIRm_ATTR_DEVICE_nGnRE 0x04 391#define CBn_MAIRm_ATTR_ID_DEVICE_nGnRE 1 392 393#define CBn_MAIRm_ATTR_DEVICE_GRE 0xc 394#define CBn_MAIRm_ATTR_ID_DEVICE_GRE 2 395 396#define CBn_MAIRm_ATTR_NC 0x44 /*non-cacheable normal memory*/ 397#define CBn_MAIRm_ATTR_ID_NC 3 /*index for non-cacheable attribute*/ 398 399/*MAIR1*/ 400/*R/W allocate, normal memory, outer/innner write back*/ 401#define CBn_MAIRm_ATTR_CACHE 0xff 402#define CBn_MAIRm_ATTR_ID_CACHE 0 403 404/*8 bit per attribute*/ 405#define CBn_MAIRm_ATTR_SHIFT(n) ((n) << 3) 406 407/*SMMU_CBn_SCTLR*/ 408#define CBn_SCTLR_CFIE (1 << 6) 409#define CBn_SCTLR_CFRE (1 << 5) 410#define CBn_SCTLR_AFE (1 << 2) 411#define CBn_SCTLR_TRE (1 << 1) 412#define CBn_SCTLR_M 1 413 414/*SMMU_CBn_TLBIASID*/ 415#define CBn_TLBIASID_SET(v) ((v) & 0xffff) 416 417/*SMMU_TLBIVMID*/ 418#define TLBIVMID_SET(v) ((v) & 0xffff) 419 420/*SMMU_CBn_TLBIVA*/ 421#define CBn_TLBIVA_SET(asid, vaddr) (((asid) & 0xffff) << 48 | ((vaddr) >> 12 & 0xfffffffffff)) 422 423/*SMMU_CBn_TLBIIPAS2*/ 424#define CBn_TLBIIPAS2_SET(vaddr) ((vaddr) >> 12 & 0xfffffffff) 425 426void smmu_cb_assign_vspace(word_t cb, vspace_root_t *vspace, asid_t asid); 427void smmu_sid_bind_cb(word_t sid, word_t cb); 428void plat_smmu_init(void); 429void smmu_tlb_invalidate_all(void); 430void smmu_tlb_invalidate_cb(int cb, asid_t asid); 431void smmu_tlb_invalidate_cb_va(int cb, asid_t asid, vptr_t vaddr); 432void smmu_cb_disable(word_t cb, asid_t asid); 433void smmu_sid_unbind(word_t sid); 434void smmu_read_fault_state(uint32_t *status, uint32_t *syndrome_0, uint32_t *syndrome_1); 435void smmu_clear_fault_state(void); 436void smmu_cb_read_fault_state(int cb, uint32_t *status, word_t *address); 437void smmu_cb_clear_fault_state(int cb); 438