1#
2# Copyright 2017, Data61
3# Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4# ABN 41 687 119 230.
5#
6# This software may be distributed and modified according to the terms of
7# the GNU General Public License version 2. Note that NO WARRANTY is provided.
8# See "LICENSE_GPLv2.txt" for details.
9#
10# @TAG(DATA61_GPL)
11#
12
13cmake_minimum_required(VERSION 3.7.2)
14
15config_choice(KernelArmSel4Arch ARM_SEL4_ARCH "Architecture mode for building the kernel"
16    "aarch32;KernelSel4ArchAarch32;ARCH_AARCH32;KernelArchARM"
17    "aarch64;KernelSel4ArchAarch64;ARCH_AARCH64;KernelArchARM"
18    "arm_hyp;KernelSel4ArchArmHyp;ARCH_ARM_HYP;KernelArchARM;KernelArmHypervisorSupport"
19)
20
21config_choice(KernelARMPlatform ARM_PLAT "Select the platform for the architecture"
22    "sabre;KernelPlatformSabre;PLAT_SABRE;KernelSel4ArchAarch32"
23    "kzm;KernelPlatformKZM;PLAT_KZM;KernelSel4ArchAarch32"
24    "omap3;KernelPlatformOMAP3;PLAT_OMAP3;KernelSel4ArchAarch32"
25    "am335x;KernelPlatformAM335X;PLAT_AM335X;KernelSel4ArchAarch32"
26    "exynos4;KernelPlatformExynos4;PLAT_EXYNOS4;KernelSel4ArchAarch32"
27    "exynos5410;KernelPlatformExynos5410;PLAT_EXYNOS5410;KernelSel4ArchAarch32 OR KernelSel4ArchArmHyp"
28    "exynos5422;KernelPlatformExynos5422;PLAT_EXYNOS5422;KernelSel4ArchAarch32"
29    "exynos5250;KernelPlatformExynos5250;PLAT_EXYNOS5250;KernelSel4ArchAarch32"
30    "apq8064;KernelPlatformAPQ8064;PLAT_APQ8064;KernelSel4ArchAarch32"
31    "wandq;KernelPlatformWandQ;PLAT_WANDQ;KernelSel4ArchAarch32"
32    "imx7sabre;KernelPlatformImx7Sabre;PLAT_IMX7_SABRE;KernelSel4ArchAarch32"
33    "zynq7000;KernelPlatformZynq7000;PLAT_ZYNQ7000;KernelSel4ArchAarch32"
34    "zynqmp;KernelPlatformZynqmp;PLAT_ZYNQMP;KernelArchARM"
35    "ultra96;KernelPlatformUltra96;PLAT_ULTRA96;KernelArchARM"
36    "allwinnera20;KernelPlatformAllwinnerA20;PLAT_ALLWINNERA20;KernelSel4ArchAarch32"
37    "tk1;KernelPlatformTK1;PLAT_TK1;KernelSel4ArchAarch32 OR KernelSel4ArchArmHyp"
38    "hikey;KernelPlatformHikey;PLAT_HIKEY;KernelArchARM"
39    "rpi3;KernelPlatformRpi3;PLAT_BCM2837;KernelArchARM"
40    "tx1;KernelPlatformTx1;PLAT_TX1;KernelSel4ArchAarch64"
41    "tx2;KernelPlatformTx2;PLAT_TX2;KernelSel4ArchAarch64"
42)
43
44if(KernelArchARM)
45    config_set(KernelSel4Arch SEL4_ARCH "${KernelArmSel4Arch}")
46endif()
47
48# arm-hyp masquerades as an aarch32 build
49if(KernelSel4ArchArmHyp)
50    config_set(KernelSel4ArmHypAarch32 ARCH_AARCH32 ON)
51    set(KernelSel4ArchAarch32 ON CACHE INTERNAL "")
52else()
53    config_set(KernelSel4ArmHypAarch32 ARCH_AARCH32 OFF)
54endif()
55
56if(KernelSel4ArchAarch32 OR KernelSel4ArchArmHyp)
57    set_kernel_32()
58elseif(KernelSel4ArchAarch64)
59    set_kernel_64()
60endif()
61
62# Include all the platforms. For all of the common variables we set a default value here
63# and let the platforms override them.
64set(KernelArmMachFeatureModifiers "" CACHE INTERNAL "")
65set(KernelArmMach "" CACHE INTERNAL "")
66set(KernelArmCortexA7 OFF)
67set(KernelArmCortexA8 OFF)
68set(KernelArmCortexA9 OFF)
69set(KernelArmCortexA15 OFF)
70set(KernelArmCortexA53 OFF)
71set(KernelArmCortexA57 OFF)
72set(KernelArchArmV6 OFF)
73set(KernelArchArmV7a OFF)
74set(KernelArchArmV7ve OFF)
75set(KernelArchArmV8a OFF)
76set(KernelArm1136JF_S OFF)
77include(src/plat/imx6/config.cmake)
78include(src/plat/imx7/config.cmake)
79include(src/plat/imx31/config.cmake)
80include(src/plat/omap3/config.cmake)
81include(src/plat/exynos4/config.cmake)
82include(src/plat/exynos5/config.cmake)
83include(src/plat/am335x/config.cmake)
84include(src/plat/hikey/config.cmake)
85include(src/plat/apq8064/config.cmake)
86include(src/plat/bcm2837/config.cmake)
87include(src/plat/tk1/config.cmake)
88include(src/plat/tx1/config.cmake)
89include(src/plat/tx2/config.cmake)
90include(src/plat/zynq7000/config.cmake)
91include(src/plat/zynqmp/config.cmake)
92
93# Now enshrine all the common variables in the config
94config_set(KernelArmCortexA7 ARM_CORTEX_A7 "${KernelArmCortexA7}")
95config_set(KernelArmCortexA8 ARM_CORTEX_A8 "${KernelArmCortexA8}")
96config_set(KernelArmCortexA9 ARM_CORTEX_A9 "${KernelArmCortexA9}")
97config_set(KernelArmCortexA15 ARM_CORTEX_A15 "${KernelArmCortexA15}")
98config_set(KernelArmCortexA53 ARM_CORTEX_A53 "${KernelArmCortexA53}")
99config_set(KernelArmCortexA57 ARM_CORTEX_A57 "${KernelArmCortexA57}")
100config_set(KernelArm1136JF_S ARM1136JF_S "${KernelArm1136JF_S}")
101config_set(KernelArchArmV6 ARCH_ARM_V6 "${KernelArchArmV6}")
102config_set(KernelArchArmV7a ARCH_ARM_V7A "${KernelArchArmV7a}")
103config_set(KernelArchArmV7ve ARCH_ARM_V7VE "${KernelArchArmV7ve}")
104config_set(KernelArchArmV8a ARCH_ARM_V8A "${KernelArchArmV8a}")
105
106set(KernelArmCPU "" CACHE INTERNAL "")
107set(KernelArmArmV "" CACHE INTERNAL "")
108
109# Check for v7ve before v7a as v7ve is a superset and we want to set the
110# actual armv to that, but leave armv7a config enabled for anything that
111# checks directly against it
112if(KernelArchArmV7ve)
113    set(KernelArmArmV "armv7ve" CACHE INTERNAL "")
114elseif(KernelArchArmV7a)
115    set(KernelArmArmV "armv7-a" CACHE INTERNAL "")
116elseif(KernelArchArmV8a)
117    set(KernelArmArmV "armv8-a" CACHE INTERNAL "")
118elseif(KernelArchArmV6)
119    set(KernelArmArmV "armv6" CACHE INTERNAL "")
120endif()
121if(KernelArmCortexA7)
122    set(KernelArmCPU "cortex-a7" CACHE INTERNAL "")
123elseif(KernelArmCortexA8)
124    set(KernelArmCPU "cortex-a8" CACHE INTERNAL "")
125elseif(KernelArmCortexA9)
126    set(KernelArmCPU "cortex-a9" CACHE INTERNAL "")
127elseif(KernelArmCortexA15)
128    set(KernelArmCPU "cortex-a15" CACHE INTERNAL "")
129elseif(KernelArmCortexA53)
130    set(KernelArmCPU "cortex-a53" CACHE INTERNAL "")
131elseif(KernelArmCortexA57)
132    set(KernelArmCPU "cortex-a57" CACHE INTERNAL "")
133elseif(KernelArm1136JF_S)
134    set(KernelArmCPU "arm1136jf-s" CACHE INTERNAL "")
135endif()
136if(KernelArchARM)
137    config_set(KernelArmMach ARM_MACH "${KernelArmMach}")
138endif()
139
140include(src/arch/arm/armv/armv6/config.cmake)
141include(src/arch/arm/armv/armv7-a/config.cmake)
142include(src/arch/arm/armv/armv8-a/config.cmake)
143
144config_choice(KernelIPCBufferLocation KERNEL_IPC_BUFFER_LOCATION
145    "Controls how the location of the IPC buffer is provided to the user for aarch32 \
146    globals_frame-> Put the address of the IPC buffer in a dedicated frame that is \
147        read only at user level. This works on all ARM platforms \
148    threadID_register-> Put the address of the IPC buffer in the user readable/writeable \
149        ThreadID register. When enabled this has the result of the kernel overwriting \
150        any value the user writes to this register."
151    "threadID_register;KernelIPCBufferThreadID;IPC_BUF_TPIDRURW;KernelSel4ArchAarch32;NOT KernelArchArmV6"
152    "globals_frame;KernelIPCBufferGlobalsFrame;IPC_BUF_GLOBALS_FRAME;KernelSel4ArchAarch32"
153)
154
155config_option(KernelDangerousCodeInjectionOnUndefInstr DANGEROUS_CODE_INJECTION_ON_UNDEF_INSTR
156    "Replaces the undefined instruction handler with a call to a function pointer in r8. \
157    This is an alternative mechanism to the code injection syscall. On ARMv6 the syscall \
158    interferes with the caches and branch predictor in such a way that it is unsuitable \
159    for benchmarking. This option has no effect on non-ARMv6 platforms."
160    DEFAULT OFF
161    DEPENDS "KernelArchArmV6;NOT KernelVerificationBuild"
162)
163
164config_option(KernelDebugDisableL2Cache DEBUG_DISABLE_L2_CACHE
165    "Do not enable the L2 cache on startup for debugging purposes."
166    DEFAULT OFF
167    DEPENDS "KernelArchARM"
168)
169config_option(KernelDebugDisableL1ICache DEBUG_DISABLE_L1_ICACHE
170    "Do not enable the L1 instruction cache on startup for debugging purposes."
171    DEFAULT OFF
172    DEPENDS "KernelArchARM;KernelDebugDisableL2Cache"
173)
174config_option(KernelDebugDisableL1DCache DEBUG_DISABLE_L1_DCACHE
175    "Do not enable the L1 data cache on startup for debugging purposes."
176    DEFAULT OFF
177    DEPENDS "KernelArchARM;KernelDebugDisableL2Cache"
178)
179config_option(KernelDebugDisableBranchPrediction DEBUG_DISABLE_BRANCH_PREDICTION
180    "Do not enable branch prediction (also called program flow control) on startup. \
181    This makes execution time more deterministic at the expense of dramatically decreasing \
182    performance. Primary use is for debugging."
183    DEFAULT OFF
184    DEPENDS "KernelArchARM"
185)
186
187config_option(KernelArmHypervisorSupport ARM_HYPERVISOR_SUPPORT
188    "Build as Hypervisor. Utilise ARM virtualisation extensions to build the kernel as a hypervisor"
189    DEFAULT OFF
190    DEPENDS "KernelArmCortexA15"
191)
192
193config_option(KernelArmHypEnableVCPUCP14SaveAndRestore ARM_HYP_ENABLE_VCPU_CP14_SAVE_AND_RESTORE
194    "Trap, but don't save/restore VCPUs' CP14 accesses \
195    This allows us to turn off the save and restore of VCPU threads' CP14 \
196    context for performance (or other) reasons, we can just turn them off \
197    and trap them instead, and have the VCPUs' accesses to CP14 \
198    intercepted and delivered to the VM Monitor as fault messages"
199    DEFAULT ON
200    DEPENDS "KernelArmHypervisorSupport;NOT KernelVerificationBuild" DEFAULT_DISABLED OFF
201)
202
203config_option(KernelArmErrata430973 ARM_ERRATA_430973
204    "Enable workaround for 430973 Cortex-A8 (r1p0..r1p2) erratum \
205    Enables a workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum. Error occurs \
206    if code containing ARM/Thumb interworking branch is replaced by different code \
207    at the same virtual address."
208    DEFAULT OFF
209    DEPENDS "KernelArchARM;KernelArmCortexA8"
210)
211
212config_option(KernelArmErrata773022 ARM_ERRATA_773022
213    "Enable workaround for 773022 Cortex-A15 (r0p0..r0p4) erratum \
214    Enables a workaround for the 773022 Cortex-A15 (r0p0..r0p4) erratum. Error occurs \
215    on rare sequences of instructions and results in the loop buffer delivering \
216    incorrect instructions. The work around is to disable the loop buffer"
217    DEFAULT ON
218    DEPENDS "KernelArchARM;KernelArmCortexA15" DEFAULT_DISABLED OFF
219)
220
221config_option(KernelArmSMMU ARM_SMMU
222    "Enable SystemMMU for the Tegra TK1 SoC"
223    DEFAULT OFF
224    DEPENDS "KernelPlatformTK1"
225)
226
227config_option(KernelArmEnableA9Prefetcher ENABLE_A9_PREFETCHER
228    "Enable Cortex-A9 prefetcher \
229    Cortex-A9 has an L1 and L2 prefetcher. By default \
230    they are disabled. This config options allows \
231    them to be turned on. Enabling the prefetchers \
232    requires that the kernel be in secure mode. ARM \
233    documents indicate that as of r4p1 version of \
234    Cortex-A9 the bits used to enable the prefetchers \
235    no longer exist, it is not clear if this is just \
236    a document error or not."
237    DEFAULT OFF
238    DEPENDS "KernelArmCortexA9"
239)
240
241config_option(KernelArmExportPMUUser EXPORT_PMU_USER
242    "PL0 access to PMU. \
243    Grant user access to Performance Monitoring Unit. \
244    WARNING: While useful for evaluating performance, \
245    this option opens timing and covert channels."
246    DEFAULT OFF
247    DEPENDS "KernelArchArmV7a OR KernelArchArmV8a;NOT KernelArmCortexA8"
248)
249
250config_option(KernelArmExportPCNTUser EXPORT_PCNT_USER
251    "PL0 access to generic timer CNTPCT and CNTFRQ. \
252    Grant user access to physical counter and counter \
253    frequency registers of the generic timer. \
254    WARNING: selecting this option opens a timing \
255    channel"
256    DEFAULT OFF
257    DEPENDS "KernelArmCortexA15"
258)
259
260config_option(KernelArmExportVCNTUser EXPORT_VCNT_USER
261    "PL0 access to generic timer CNTVCT and CNTFRQ. \
262    Grant user access to virtual counter and counter \
263    frequency registers of the generic timer. \
264    WARNING: selecting this option opens a timing \
265    channel"
266    DEFAULT OFF
267    DEPENDS "KernelArmCortexA15 OR KernelArmCortexA53"
268)
269
270config_option(KernelARMSMMUInterruptEnable SMMU_INTERRUPT_ENABLE
271    "Enable SMMU interrupts. \
272    SMMU interrupts currently only serve a debug purpose as \
273    they are not forwarded to user level. Enabling this will \
274    cause some fault types to print out a message in the kernel. \
275    WARNING: Printing fault information is slow and rapid faults \
276    can result in all time spent in the kernel printing fault \
277    messages"
278    DEFAULT "${KernelDebugBuild}"
279    DEPENDS "KernelArmSMMU" DEFAULT_DISABLED OFF
280)
281
282config_option(KernelAArch32FPUEnableContextSwitch AARCH32_FPU_ENABLE_CONTEXT_SWITCH
283    "Enable hardware VFP and SIMD context switch \
284        This enables the VFP and SIMD context switch on platforms with \
285        hardware support, allowing the user to execute hardware VFP and SIMD \
286        operations in a multithreading environment, instead of relying on \
287        software emulation of FPU/VFP from the C library (e.g. mfloat-abi=soft)."
288    DEFAULT ON
289    DEPENDS "KernelSel4ArchAarch32;NOT KernelArchArmV6;NOT KernelVerificationBuild"
290    DEFAULT_DISABLED OFF
291)
292
293if(KernelAArch32FPUEnableContextSwitch)
294    set(KernelHaveFPU ON)
295endif()
296
297# TODO: this config has no business being in the build system, and should
298# be moved to C headers, but for now must be emulated here for compatibility
299if(KernelBenchmarksTrackUtilisation AND KernelArchARM)
300    config_set(KernelArmEnablePMUOverflowInterrupt ARM_ENABLE_PMU_OVERFLOW_INTERRUPT ON)
301else()
302    config_set(KernelArmEnablePMUOverflowInterrupt ARM_ENABLE_PMU_OVERFLOW_INTERRUPT OFF)
303endif()
304
305
306add_sources(
307    DEP "KernelArchARM"
308    PREFIX src/arch/arm
309    CFILES
310        c_traps.c
311        api/faults.c
312        benchmark/benchmark.c
313        kernel/boot.c
314        kernel/thread.c
315        machine/cache.c
316        machine/errata.c
317        machine/io.c
318        machine/debug.c
319        object/interrupt.c
320        object/tcb.c
321        object/iospace.c
322        object/vcpu.c
323        smp/ipi.c
324)
325
326add_sources(
327    DEP "KernelArmCortexA9"
328    CFILES src/arch/arm/machine/l2c_310.c
329)
330
331add_sources(
332    DEP "KernelArmCortexA9;NOT KernelPlatformExynos4"
333    CFILES src/arch/arm/machine/global_timer.c
334)
335
336add_sources(
337    DEP "KernelArmCortexA15 OR KernelArmCortexA7 OR KernelArmCortexA57 OR KernelArmCortexA9 OR KernelPlatformHikey OR KernelPlatformZynqmp"
338    CFILES src/arch/arm/machine/gic_pl390.c
339)
340
341add_bf_source_old("KernelArchARM" "structures.bf" "include/arch/arm" "arch/object")
342add_bf_source_old("KernelArchARM" "hardware.bf" "include/plat/${KernelPlatform}" "plat/machine")
343
344include(src/arch/arm/32/config.cmake)
345include(src/arch/arm/64/config.cmake)
346