1/*
2 * Copyright 2018, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * Copyright 2018, DornerWorks
7 *
8 * This software may be distributed and modified according to the terms of
9 * the GNU General Public License version 2. Note that NO WARRANTY is provided.
10 * See "LICENSE_GPLv2.txt" for details.
11 *
12 * @TAG(DATA61_DORNERWORKS_GPL)
13 */
14
15/*
16 *
17 * Copyright 2016, 2017 Hesham Almatary, Data61/CSIRO <hesham.almatary@data61.csiro.au>
18 * Copyright 2015, 2016 Hesham Almatary <heshamelmatary@gmail.com>
19 */
20
21#ifndef __ARCH_MODEL_STATEDATA_H
22#define __ARCH_MODEL_STATEDATA_H
23
24#include <config.h>
25#include <types.h>
26#include <util.h>
27#include <object/structures.h>
28#include <arch/types.h>
29#include <plat/machine/devices.h>
30
31
32NODE_STATE_BEGIN(archNodeState)
33/* TODO: add RISCV-dependent fields here */
34/* Bitmask of all cores should receive the reschedule IPI */
35NODE_STATE_DECLARE(word_t, ipiReschedulePending);
36NODE_STATE_END(archNodeState);
37
38extern asid_pool_t *riscvKSASIDTable[BIT(asidHighBits)];
39
40/* Kernel Page Tables */
41extern pte_t kernel_root_pageTable[BIT(PT_INDEX_BITS)] VISIBLE;
42
43/* If our PADDR_LOAD is not 1GiB aligned then we need to introduce a level2 pagetable
44 * in order to map in our kernel image at KERNEL_BASE */
45#if CONFIG_PT_LEVELS == 3 && !IS_ALIGNED(PADDR_LOAD, RISCV_GET_LVL_PGSIZE_BITS(1))
46#define RISCV_KERNEL_WINDOW_LEVEL2_PT
47extern pte_t kernel_image_level2_pt[BIT(PT_INDEX_BITS)];
48#endif
49#endif
50