1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the GNU General Public License version 2. Note that NO WARRANTY is provided. 8 * See "LICENSE_GPLv2.txt" for details. 9 * 10 * @TAG(DATA61_GPL) 11 */ 12 13#ifndef __ARCH_MODEL_SMP_H_ 14#define __ARCH_MODEL_SMP_H_ 15 16#include <config.h> 17#include <mode/smp/smp.h> 18#include <model/smp.h> 19 20#ifdef ENABLE_SMP_SUPPORT 21static inline cpu_id_t cpuIndexToID(word_t index) 22{ 23 return BIT(index); 24} 25 26static inline bool_t 27try_arch_atomic_exchange(void* ptr, void *new_val, void **prev, int success_memorder, int failure_memorder) 28{ 29 uint32_t atomic_status; 30 void *temp; 31 32 asm volatile ( 33 LD_EX "%[prev_output], [%[ptr_val]] \n\t" /* ret = *ptr */ 34 ST_EX "%" OP_WIDTH "[atomic_var], %[new_val] , [%[ptr_val]] \n\t" /* *ptr = new */ 35 : [atomic_var] "=&r"(atomic_status), [prev_output]"=&r"(temp) /* output */ 36 : [ptr_val] "r"(ptr), [new_val] "r" (new_val) /* input */ 37 : 38 ); 39 40 *prev = temp; 41 42 /* Atomic operation success */ 43 if (likely(!atomic_status)) { 44 __atomic_thread_fence(success_memorder); 45 } else { 46 /* Atomic operation failure */ 47 __atomic_thread_fence(failure_memorder); 48 } 49 50 /* On ARM if an atomic operation succeeds, it returns 0 */ 51 return (atomic_status == 0); 52} 53 54#endif /* ENABLE_SMP_SUPPORT */ 55 56#endif /* __ARCH_MODEL_SMP_H_ */ 57