1/*
2 * Copyright 2014, General Dynamics C4 Systems
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 */
6
7#include <config.h>
8#include <machine/assembler.h>
9
10#if defined(CONFIG_ARM_CORTEX_A15) || defined(CONFIG_ARM_CORTEX_A7)
11  /* The hardware does not support tlb locking */
12
13#else
14
15.code 32
16.section .text, "ax"
17.global lockTLBEntryCritical
18
19.balign (16*4)
20BEGIN_FUNC(lockTLBEntryCritical)
21
22 /* lockTLBEntryCritical should lie within a single page so that spurious TLB walks do
23 * not interfere. Aligning to a 64-byte instruction boundary will suffice, as
24 * the critical section (i.e. this function) fits within 64 bytes.
25 */
26    /* Invalidate both I & D TLB entry */
27    mcr p15, 0, r0, c8, c7, 1
28
29    /* Now lock it! */
30    mcr p15, 0, r1, c10, c0, 1 /* Start locking walked I-TLB entries. */
31    mcr p15, 0, r0, c10, c1, 1 /* Load I-TLB entry. */
32    mcr p15, 0, r2, c10, c0, 1 /* Finish locking walked I-TLB entries. */
33
34    mcr p15, 0, r1, c10, c0, 0 /* Start locking walked D-TLB entries. */
35    mcr p15, 0, r0, c10, c1, 0 /* Load D-TLB entry. */
36    mcr p15, 0, r2, c10, c0, 0 /* Finish locking walked D-TLB entries. */
37
38    bx lr
39END_FUNC(lockTLBEntryCritical)
40
41#endif /* ARM_CORTEX_A15 */
42