1(* mips - generated by L3 - Mon Jul 03 10:13:58 2017 *) 2 3structure mips :> mips = 4struct 5 6structure Map = MutableMap 7 8(* ------------------------------------------------------------------------- 9 Type declarations 10 ------------------------------------------------------------------------- *) 11 12type Index = { Index: BitsN.nbit, P: bool, index'rst: BitsN.nbit } 13 14type Random = { Random: BitsN.nbit, random'rst: BitsN.nbit } 15 16type Wired = { Wired: BitsN.nbit, wired'rst: BitsN.nbit } 17 18type EntryLo = 19 { C: BitsN.nbit, D: bool, G: bool, PFN: BitsN.nbit, V: bool, 20 entrylo'rst: BitsN.nbit } 21 22type PageMask = { Mask: BitsN.nbit, pagemask'rst: BitsN.nbit } 23 24type EntryHi = 25 { ASID: BitsN.nbit, R: BitsN.nbit, VPN2: BitsN.nbit, 26 entryhi'rst: BitsN.nbit } 27 28type StatusRegister = 29 { BEV: bool, CU0: bool, CU1: bool, ERL: bool, EXL: bool, FR: bool, 30 IE: bool, IM: BitsN.nbit, KSU: BitsN.nbit, KX: bool, RE: bool, 31 SX: bool, UX: bool, statusregister'rst: BitsN.nbit } 32 33type ConfigRegister = 34 { AR: BitsN.nbit, AT: BitsN.nbit, BE: bool, K0: BitsN.nbit, M: bool, 35 MT: BitsN.nbit, configregister'rst: BitsN.nbit } 36 37type ConfigRegister1 = 38 { C2: bool, CA: bool, DA: BitsN.nbit, DL: BitsN.nbit, DS: BitsN.nbit, 39 EP: bool, FP: bool, IA: BitsN.nbit, IL: BitsN.nbit, IS: BitsN.nbit, 40 M: bool, MD: bool, MMUSize: BitsN.nbit, PC: bool, WR: bool } 41 42type ConfigRegister2 = 43 { M: bool, SA: BitsN.nbit, SL: BitsN.nbit, SS: BitsN.nbit, 44 SU: BitsN.nbit, TA: BitsN.nbit, TL: BitsN.nbit, TS: BitsN.nbit, 45 TU: BitsN.nbit } 46 47type ConfigRegister3 = 48 { DSPP: bool, LPA: bool, M: bool, MT: bool, SM: bool, SP: bool, 49 TL: bool, ULRI: bool, VEIC: bool, VInt: bool, 50 configregister3'rst: BitsN.nbit } 51 52type ConfigRegister6 = 53 { LTLB: bool, TLBSize: BitsN.nbit, configregister6'rst: BitsN.nbit } 54 55type CauseRegister = 56 { BD: bool, CE: BitsN.nbit, ExcCode: BitsN.nbit, IP: BitsN.nbit, 57 TI: bool, causeregister'rst: BitsN.nbit } 58 59type Context = 60 { BadVPN2: BitsN.nbit, PTEBase: BitsN.nbit, context'rst: BitsN.nbit } 61 62type XContext = 63 { BadVPN2: BitsN.nbit, PTEBase: BitsN.nbit, R: BitsN.nbit, 64 xcontext'rst: BitsN.nbit } 65 66type HWREna = 67 { CC: bool, CCRes: bool, CPUNum: bool, UL: bool, hwrena'rst: BitsN.nbit 68 } 69 70type CP0 = 71 { BadVAddr: BitsN.nbit, Cause: CauseRegister, Compare: BitsN.nbit, 72 Config: ConfigRegister, Config1: ConfigRegister1, 73 Config2: ConfigRegister2, Config3: ConfigRegister3, 74 Config6: ConfigRegister6, Context: Context, Count: BitsN.nbit, 75 Debug: BitsN.nbit, EPC: BitsN.nbit, EntryHi: EntryHi, 76 EntryLo0: EntryLo, EntryLo1: EntryLo, ErrCtl: BitsN.nbit, 77 ErrorEPC: BitsN.nbit, HWREna: HWREna, Index: Index, 78 LLAddr: BitsN.nbit, PRId: BitsN.nbit, PageMask: PageMask, 79 Random: Random, Status: StatusRegister, UsrLocal: BitsN.nbit, 80 Wired: Wired, XContext: XContext } 81 82datatype ExceptionType 83 = Int | Mod | TLBL | TLBS | AdEL | AdES | Sys | Bp | ResI | CpU | Ov 84 | Tr | XTLBRefillL | XTLBRefillS 85 86datatype LorS = LOAD | STORE 87 88type FCSR = 89 { ABS2008: bool, CauseE: bool, CauseI: bool, CauseO: bool, CauseU: bool, 90 CauseV: bool, CauseZ: bool, EnableI: bool, EnableO: bool, 91 EnableU: bool, EnableV: bool, EnableZ: bool, FCC: BitsN.nbit, 92 FS: bool, FlagI: bool, FlagO: bool, FlagU: bool, FlagV: bool, 93 FlagZ: bool, NAN2008: bool, RM: BitsN.nbit, fcsr'rst: BitsN.nbit } 94 95type FIR = 96 { ASE: bool, D: bool, F64: bool, L: bool, PS: bool, PrID: BitsN.nbit, 97 Rev: BitsN.nbit, S: bool, W: bool, fir'rst: BitsN.nbit } 98 99datatype Branch 100 = BEQ of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 101 | BEQL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 102 | BGEZ of BitsN.nbit * BitsN.nbit 103 | BGEZAL of BitsN.nbit * BitsN.nbit 104 | BGEZALL of BitsN.nbit * BitsN.nbit 105 | BGEZL of BitsN.nbit * BitsN.nbit 106 | BGTZ of BitsN.nbit * BitsN.nbit 107 | BGTZL of BitsN.nbit * BitsN.nbit 108 | BLEZ of BitsN.nbit * BitsN.nbit 109 | BLEZL of BitsN.nbit * BitsN.nbit 110 | BLTZ of BitsN.nbit * BitsN.nbit 111 | BLTZAL of BitsN.nbit * BitsN.nbit 112 | BLTZALL of BitsN.nbit * BitsN.nbit 113 | BLTZL of BitsN.nbit * BitsN.nbit 114 | BNE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 115 | BNEL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 116 | J of BitsN.nbit 117 | JAL of BitsN.nbit 118 | JALR of BitsN.nbit * BitsN.nbit 119 | JR of BitsN.nbit 120 121datatype CP 122 = DMFC0 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 123 | DMTC0 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 124 | MFC0 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 125 | MTC0 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 126 127datatype Store 128 = SB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 129 | SC of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 130 | SCD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 131 | SD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 132 | SDL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 133 | SDR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 134 | SH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 135 | SW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 136 | SWL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 137 | SWR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 138 139datatype Load 140 = LB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 141 | LBU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 142 | LD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 143 | LDL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 144 | LDR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 145 | LH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 146 | LHU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 147 | LL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 148 | LLD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 149 | LW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 150 | LWL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 151 | LWR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 152 | LWU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 153 154datatype Trap 155 = TEQ of BitsN.nbit * BitsN.nbit 156 | TEQI of BitsN.nbit * BitsN.nbit 157 | TGE of BitsN.nbit * BitsN.nbit 158 | TGEI of BitsN.nbit * BitsN.nbit 159 | TGEIU of BitsN.nbit * BitsN.nbit 160 | TGEU of BitsN.nbit * BitsN.nbit 161 | TLT of BitsN.nbit * BitsN.nbit 162 | TLTI of BitsN.nbit * BitsN.nbit 163 | TLTIU of BitsN.nbit * BitsN.nbit 164 | TLTU of BitsN.nbit * BitsN.nbit 165 | TNE of BitsN.nbit * BitsN.nbit 166 | TNEI of BitsN.nbit * BitsN.nbit 167 168datatype Shift 169 = DSLL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 170 | DSLL32 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 171 | DSLLV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 172 | DSRA of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 173 | DSRA32 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 174 | DSRAV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 175 | DSRL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 176 | DSRL32 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 177 | DSRLV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 178 | SLL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 179 | SLLV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 180 | SRA of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 181 | SRAV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 182 | SRL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 183 | SRLV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 184 185datatype MultDiv 186 = DDIV of BitsN.nbit * BitsN.nbit 187 | DDIVU of BitsN.nbit * BitsN.nbit 188 | DIV of BitsN.nbit * BitsN.nbit 189 | DIVU of BitsN.nbit * BitsN.nbit 190 | DMULT of BitsN.nbit * BitsN.nbit 191 | DMULTU of BitsN.nbit * BitsN.nbit 192 | MADD of BitsN.nbit * BitsN.nbit 193 | MADDU of BitsN.nbit * BitsN.nbit 194 | MFHI of BitsN.nbit 195 | MFLO of BitsN.nbit 196 | MSUB of BitsN.nbit * BitsN.nbit 197 | MSUBU of BitsN.nbit * BitsN.nbit 198 | MTHI of BitsN.nbit 199 | MTLO of BitsN.nbit 200 | MUL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 201 | MULT of BitsN.nbit * BitsN.nbit 202 | MULTU of BitsN.nbit * BitsN.nbit 203 204datatype ArithR 205 = ADD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 206 | ADDU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 207 | AND of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 208 | DADD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 209 | DADDU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 210 | DSUB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 211 | DSUBU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 212 | MOVN of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 213 | MOVZ of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 214 | NOR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 215 | OR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 216 | SLT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 217 | SLTU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 218 | SUB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 219 | SUBU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 220 | XOR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 221 222datatype ArithI 223 = ADDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 224 | ADDIU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 225 | ANDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 226 | DADDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 227 | DADDIU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 228 | LUI of BitsN.nbit * BitsN.nbit 229 | ORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 230 | SLTI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 231 | SLTIU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 232 | XORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 233 234datatype COP1 235 = ABS_D of BitsN.nbit * BitsN.nbit 236 | ABS_S of BitsN.nbit * BitsN.nbit 237 | ADD_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 238 | ADD_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 239 | BC1F of BitsN.nbit * BitsN.nbit 240 | BC1FL of BitsN.nbit * BitsN.nbit 241 | BC1T of BitsN.nbit * BitsN.nbit 242 | BC1TL of BitsN.nbit * BitsN.nbit 243 | CEIL_L_D of BitsN.nbit * BitsN.nbit 244 | CEIL_L_S of BitsN.nbit * BitsN.nbit 245 | CEIL_W_D of BitsN.nbit * BitsN.nbit 246 | CEIL_W_S of BitsN.nbit * BitsN.nbit 247 | CFC1 of BitsN.nbit * BitsN.nbit 248 | CTC1 of BitsN.nbit * BitsN.nbit 249 | CVT_D_L of BitsN.nbit * BitsN.nbit 250 | CVT_D_S of BitsN.nbit * BitsN.nbit 251 | CVT_D_W of BitsN.nbit * BitsN.nbit 252 | CVT_L_D of BitsN.nbit * BitsN.nbit 253 | CVT_L_S of BitsN.nbit * BitsN.nbit 254 | CVT_S_D of BitsN.nbit * BitsN.nbit 255 | CVT_S_L of BitsN.nbit * BitsN.nbit 256 | CVT_S_W of BitsN.nbit * BitsN.nbit 257 | CVT_W_D of BitsN.nbit * BitsN.nbit 258 | CVT_W_S of BitsN.nbit * BitsN.nbit 259 | C_cond_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 260 | C_cond_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 261 | DIV_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 262 | DIV_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 263 | DMFC1 of BitsN.nbit * BitsN.nbit 264 | DMTC1 of BitsN.nbit * BitsN.nbit 265 | FLOOR_L_D of BitsN.nbit * BitsN.nbit 266 | FLOOR_L_S of BitsN.nbit * BitsN.nbit 267 | FLOOR_W_D of BitsN.nbit * BitsN.nbit 268 | FLOOR_W_S of BitsN.nbit * BitsN.nbit 269 | LDC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 270 | LDXC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 271 | LWC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 272 | LWXC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 273 | MADD_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 274 | MADD_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 275 | MFC1 of BitsN.nbit * BitsN.nbit 276 | MOVF of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 277 | MOVF_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 278 | MOVF_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 279 | MOVN_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 280 | MOVN_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 281 | MOVT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 282 | MOVT_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 283 | MOVT_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 284 | MOVZ_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 285 | MOVZ_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 286 | MOV_D of BitsN.nbit * BitsN.nbit 287 | MOV_S of BitsN.nbit * BitsN.nbit 288 | MSUB_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 289 | MSUB_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 290 | MTC1 of BitsN.nbit * BitsN.nbit 291 | MUL_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 292 | MUL_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 293 | NEG_D of BitsN.nbit * BitsN.nbit 294 | NEG_S of BitsN.nbit * BitsN.nbit 295 | ROUND_L_D of BitsN.nbit * BitsN.nbit 296 | ROUND_L_S of BitsN.nbit * BitsN.nbit 297 | ROUND_W_D of BitsN.nbit * BitsN.nbit 298 | ROUND_W_S of BitsN.nbit * BitsN.nbit 299 | SDC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 300 | SDXC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 301 | SQRT_D of BitsN.nbit * BitsN.nbit 302 | SQRT_S of BitsN.nbit * BitsN.nbit 303 | SUB_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 304 | SUB_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 305 | SWC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 306 | SWXC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 307 | TRUNC_L_D of BitsN.nbit * BitsN.nbit 308 | TRUNC_L_S of BitsN.nbit * BitsN.nbit 309 | TRUNC_W_D of BitsN.nbit * BitsN.nbit 310 | TRUNC_W_S of BitsN.nbit * BitsN.nbit 311 | UnknownFPInstruction 312 313datatype instruction 314 = ArithI of ArithI 315 | ArithR of ArithR 316 | BREAK 317 | Branch of Branch 318 | CACHE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 319 | COP1 of COP1 320 | CP of CP 321 | ERET 322 | Load of Load 323 | MultDiv of MultDiv 324 | RDHWR of BitsN.nbit * BitsN.nbit 325 | ReservedInstruction 326 | SYNC of BitsN.nbit 327 | SYSCALL 328 | Shift of Shift 329 | Store of Store 330 | TLBP 331 | TLBR 332 | TLBWI 333 | TLBWR 334 | Trap of Trap 335 | Unpredictable 336 | WAIT 337 338datatype maybe_instruction 339 = FAIL of string | OK of instruction | WORD32 of BitsN.nbit 340 341(* ------------------------------------------------------------------------- 342 Casting maps (for enumerated types) 343 ------------------------------------------------------------------------- *) 344 345structure Cast = 346struct 347fun natToExceptionType x = 348 case Nat.toInt x of 349 0 => Int 350 | 1 => Mod 351 | 2 => TLBL 352 | 3 => TLBS 353 | 4 => AdEL 354 | 5 => AdES 355 | 6 => Sys 356 | 7 => Bp 357 | 8 => ResI 358 | 9 => CpU 359 | 10 => Ov 360 | 11 => Tr 361 | 12 => XTLBRefillL 362 | 13 => XTLBRefillS 363 | _ => raise Fail "natToExceptionType" 364 365fun natToLorS x = 366 case Nat.toInt x of 367 0 => LOAD | 1 => STORE | _ => raise Fail "natToLorS" 368 369fun ExceptionTypeToNat x = 370 case x of 371 Int => 0 372 | Mod => 1 373 | TLBL => 2 374 | TLBS => 3 375 | AdEL => 4 376 | AdES => 5 377 | Sys => 6 378 | Bp => 7 379 | ResI => 8 380 | CpU => 9 381 | Ov => 10 382 | Tr => 11 383 | XTLBRefillL => 12 384 | XTLBRefillS => 13 385 386fun LorSToNat x = 387 case x of 388 LOAD => 0 | STORE => 1 389 390fun ExceptionTypeToString x = 391 case x of 392 Int => "Int" 393 | Mod => "Mod" 394 | TLBL => "TLBL" 395 | TLBS => "TLBS" 396 | AdEL => "AdEL" 397 | AdES => "AdES" 398 | Sys => "Sys" 399 | Bp => "Bp" 400 | ResI => "ResI" 401 | CpU => "CpU" 402 | Ov => "Ov" 403 | Tr => "Tr" 404 | XTLBRefillL => "XTLBRefillL" 405 | XTLBRefillS => "XTLBRefillS" 406 407fun LorSToString x = 408 case x of 409 LOAD => "LOAD" | STORE => "STORE" 410 411fun stringToExceptionType x = 412 case x of 413 "Int" => Int 414 | "Mod" => Mod 415 | "TLBL" => TLBL 416 | "TLBS" => TLBS 417 | "AdEL" => AdEL 418 | "AdES" => AdES 419 | "Sys" => Sys 420 | "Bp" => Bp 421 | "ResI" => ResI 422 | "CpU" => CpU 423 | "Ov" => Ov 424 | "Tr" => Tr 425 | "XTLBRefillL" => XTLBRefillL 426 | "XTLBRefillS" => XTLBRefillS 427 | _ => raise Fail "stringToExceptionType" 428 429fun stringToLorS x = 430 case x of 431 "LOAD" => LOAD | "STORE" => STORE | _ => raise Fail "stringToLorS" 432end 433 434(* ------------------------------------------------------------------------- 435 Record update functions 436 ------------------------------------------------------------------------- *) 437 438fun Index_Index_rupd ({Index, P, index'rst}: Index, x') = 439 {Index = x', P = P, index'rst = index'rst}: Index 440 441fun Index_P_rupd ({Index, P, index'rst}: Index, x') = 442 {Index = Index, P = x', index'rst = index'rst}: Index 443 444fun Index_index'rst_rupd ({Index, P, index'rst}: Index, x') = 445 {Index = Index, P = P, index'rst = x'}: Index 446 447fun Random_Random_rupd ({Random, random'rst}: Random, x') = 448 {Random = x', random'rst = random'rst}: Random 449 450fun Random_random'rst_rupd ({Random, random'rst}: Random, x') = 451 {Random = Random, random'rst = x'}: Random 452 453fun Wired_Wired_rupd ({Wired, wired'rst}: Wired, x') = 454 {Wired = x', wired'rst = wired'rst}: Wired 455 456fun Wired_wired'rst_rupd ({Wired, wired'rst}: Wired, x') = 457 {Wired = Wired, wired'rst = x'}: Wired 458 459fun EntryLo_C_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = 460 {C = x', D = D, G = G, PFN = PFN, V = V, entrylo'rst = entrylo'rst} 461 : EntryLo 462 463fun EntryLo_D_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = 464 {C = C, D = x', G = G, PFN = PFN, V = V, entrylo'rst = entrylo'rst} 465 : EntryLo 466 467fun EntryLo_G_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = 468 {C = C, D = D, G = x', PFN = PFN, V = V, entrylo'rst = entrylo'rst} 469 : EntryLo 470 471fun EntryLo_PFN_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = 472 {C = C, D = D, G = G, PFN = x', V = V, entrylo'rst = entrylo'rst} 473 : EntryLo 474 475fun EntryLo_V_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = 476 {C = C, D = D, G = G, PFN = PFN, V = x', entrylo'rst = entrylo'rst} 477 : EntryLo 478 479fun EntryLo_entrylo'rst_rupd ({C, D, G, PFN, V, entrylo'rst} 480 : EntryLo, x') = 481 {C = C, D = D, G = G, PFN = PFN, V = V, entrylo'rst = x'}: EntryLo 482 483fun PageMask_Mask_rupd ({Mask, pagemask'rst}: PageMask, x') = 484 {Mask = x', pagemask'rst = pagemask'rst}: PageMask 485 486fun PageMask_pagemask'rst_rupd ({Mask, pagemask'rst}: PageMask, x') = 487 {Mask = Mask, pagemask'rst = x'}: PageMask 488 489fun EntryHi_ASID_rupd ({ASID, R, VPN2, entryhi'rst}: EntryHi, x') = 490 {ASID = x', R = R, VPN2 = VPN2, entryhi'rst = entryhi'rst}: EntryHi 491 492fun EntryHi_R_rupd ({ASID, R, VPN2, entryhi'rst}: EntryHi, x') = 493 {ASID = ASID, R = x', VPN2 = VPN2, entryhi'rst = entryhi'rst}: EntryHi 494 495fun EntryHi_VPN2_rupd ({ASID, R, VPN2, entryhi'rst}: EntryHi, x') = 496 {ASID = ASID, R = R, VPN2 = x', entryhi'rst = entryhi'rst}: EntryHi 497 498fun EntryHi_entryhi'rst_rupd ({ASID, R, VPN2, entryhi'rst}: EntryHi, x') = 499 {ASID = ASID, R = R, VPN2 = VPN2, entryhi'rst = x'}: EntryHi 500 501fun StatusRegister_BEV_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, 502 KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = 503 {BEV = x', CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, 504 IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 505 statusregister'rst = statusregister'rst}: StatusRegister 506 507fun StatusRegister_CU0_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, 508 KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = 509 {BEV = BEV, CU0 = x', CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, 510 IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 511 statusregister'rst = statusregister'rst}: StatusRegister 512 513fun StatusRegister_CU1_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, 514 KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = 515 {BEV = BEV, CU0 = CU0, CU1 = x', ERL = ERL, EXL = EXL, FR = FR, IE = IE, 516 IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 517 statusregister'rst = statusregister'rst}: StatusRegister 518 519fun StatusRegister_ERL_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, 520 KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = 521 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = x', EXL = EXL, FR = FR, IE = IE, 522 IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 523 statusregister'rst = statusregister'rst}: StatusRegister 524 525fun StatusRegister_EXL_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, 526 KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = 527 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = x', FR = FR, IE = IE, 528 IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 529 statusregister'rst = statusregister'rst}: StatusRegister 530 531fun StatusRegister_FR_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, 532 RE, SX, UX, statusregister'rst}: StatusRegister, x') = 533 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = x', 534 IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 535 statusregister'rst = statusregister'rst}: StatusRegister 536 537fun StatusRegister_IE_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, 538 RE, SX, UX, statusregister'rst}: StatusRegister, x') = 539 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, 540 IE = x', IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 541 statusregister'rst = statusregister'rst}: StatusRegister 542 543fun StatusRegister_IM_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, 544 RE, SX, UX, statusregister'rst}: StatusRegister, x') = 545 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, 546 IE = IE, IM = x', KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 547 statusregister'rst = statusregister'rst}: StatusRegister 548 549fun StatusRegister_KSU_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, 550 KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = 551 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, 552 IE = IE, IM = IM, KSU = x', KX = KX, RE = RE, SX = SX, UX = UX, 553 statusregister'rst = statusregister'rst}: StatusRegister 554 555fun StatusRegister_KX_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, 556 RE, SX, UX, statusregister'rst}: StatusRegister, x') = 557 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, 558 IE = IE, IM = IM, KSU = KSU, KX = x', RE = RE, SX = SX, UX = UX, 559 statusregister'rst = statusregister'rst}: StatusRegister 560 561fun StatusRegister_RE_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, 562 RE, SX, UX, statusregister'rst}: StatusRegister, x') = 563 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, 564 IE = IE, IM = IM, KSU = KSU, KX = KX, RE = x', SX = SX, UX = UX, 565 statusregister'rst = statusregister'rst}: StatusRegister 566 567fun StatusRegister_SX_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, 568 RE, SX, UX, statusregister'rst}: StatusRegister, x') = 569 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, 570 IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = x', UX = UX, 571 statusregister'rst = statusregister'rst}: StatusRegister 572 573fun StatusRegister_UX_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, 574 RE, SX, UX, statusregister'rst}: StatusRegister, x') = 575 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, 576 IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = x', 577 statusregister'rst = statusregister'rst}: StatusRegister 578 579fun StatusRegister_statusregister'rst_rupd ({BEV, CU0, CU1, ERL, EXL, FR, 580 IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = 581 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, 582 IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 583 statusregister'rst = x'}: StatusRegister 584 585fun ConfigRegister_AR_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} 586 : ConfigRegister, x') = 587 {AR = x', AT = AT, BE = BE, K0 = K0, M = M, MT = MT, 588 configregister'rst = configregister'rst}: ConfigRegister 589 590fun ConfigRegister_AT_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} 591 : ConfigRegister, x') = 592 {AR = AR, AT = x', BE = BE, K0 = K0, M = M, MT = MT, 593 configregister'rst = configregister'rst}: ConfigRegister 594 595fun ConfigRegister_BE_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} 596 : ConfigRegister, x') = 597 {AR = AR, AT = AT, BE = x', K0 = K0, M = M, MT = MT, 598 configregister'rst = configregister'rst}: ConfigRegister 599 600fun ConfigRegister_K0_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} 601 : ConfigRegister, x') = 602 {AR = AR, AT = AT, BE = BE, K0 = x', M = M, MT = MT, 603 configregister'rst = configregister'rst}: ConfigRegister 604 605fun ConfigRegister_M_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} 606 : ConfigRegister, x') = 607 {AR = AR, AT = AT, BE = BE, K0 = K0, M = x', MT = MT, 608 configregister'rst = configregister'rst}: ConfigRegister 609 610fun ConfigRegister_MT_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} 611 : ConfigRegister, x') = 612 {AR = AR, AT = AT, BE = BE, K0 = K0, M = M, MT = x', 613 configregister'rst = configregister'rst}: ConfigRegister 614 615fun ConfigRegister_configregister'rst_rupd ({AR, AT, BE, K0, M, MT, 616 configregister'rst}: ConfigRegister, x') = 617 {AR = AR, AT = AT, BE = BE, K0 = K0, M = M, MT = MT, 618 configregister'rst = x'}: ConfigRegister 619 620fun ConfigRegister1_C2_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 621 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 622 {C2 = x', CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 623 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 624 : ConfigRegister1 625 626fun ConfigRegister1_CA_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 627 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 628 {C2 = C2, CA = x', DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 629 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 630 : ConfigRegister1 631 632fun ConfigRegister1_DA_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 633 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 634 {C2 = C2, CA = CA, DA = x', DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 635 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 636 : ConfigRegister1 637 638fun ConfigRegister1_DL_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 639 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 640 {C2 = C2, CA = CA, DA = DA, DL = x', DS = DS, EP = EP, FP = FP, IA = IA, 641 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 642 : ConfigRegister1 643 644fun ConfigRegister1_DS_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 645 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 646 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = x', EP = EP, FP = FP, IA = IA, 647 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 648 : ConfigRegister1 649 650fun ConfigRegister1_EP_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 651 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 652 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = x', FP = FP, IA = IA, 653 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 654 : ConfigRegister1 655 656fun ConfigRegister1_FP_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 657 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 658 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = x', IA = IA, 659 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 660 : ConfigRegister1 661 662fun ConfigRegister1_IA_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 663 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 664 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = x', 665 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 666 : ConfigRegister1 667 668fun ConfigRegister1_IL_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 669 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 670 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 671 IL = x', IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 672 : ConfigRegister1 673 674fun ConfigRegister1_IS_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 675 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 676 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 677 IL = IL, IS = x', M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 678 : ConfigRegister1 679 680fun ConfigRegister1_M_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 681 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 682 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 683 IL = IL, IS = IS, M = x', MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} 684 : ConfigRegister1 685 686fun ConfigRegister1_MD_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 687 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 688 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 689 IL = IL, IS = IS, M = M, MD = x', MMUSize = MMUSize, PC = PC, WR = WR} 690 : ConfigRegister1 691 692fun ConfigRegister1_MMUSize_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, 693 M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = 694 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 695 IL = IL, IS = IS, M = M, MD = MD, MMUSize = x', PC = PC, WR = WR} 696 : ConfigRegister1 697 698fun ConfigRegister1_PC_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 699 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 700 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 701 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = x', WR = WR} 702 : ConfigRegister1 703 704fun ConfigRegister1_WR_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, 705 MD, MMUSize, PC, WR}: ConfigRegister1, x') = 706 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, 707 IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = x'} 708 : ConfigRegister1 709 710fun ConfigRegister2_M_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} 711 : ConfigRegister2, x') = 712 {M = x', SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, TS = TS, 713 TU = TU}: ConfigRegister2 714 715fun ConfigRegister2_SA_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} 716 : ConfigRegister2, x') = 717 {M = M, SA = x', SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, TS = TS, 718 TU = TU}: ConfigRegister2 719 720fun ConfigRegister2_SL_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} 721 : ConfigRegister2, x') = 722 {M = M, SA = SA, SL = x', SS = SS, SU = SU, TA = TA, TL = TL, TS = TS, 723 TU = TU}: ConfigRegister2 724 725fun ConfigRegister2_SS_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} 726 : ConfigRegister2, x') = 727 {M = M, SA = SA, SL = SL, SS = x', SU = SU, TA = TA, TL = TL, TS = TS, 728 TU = TU}: ConfigRegister2 729 730fun ConfigRegister2_SU_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} 731 : ConfigRegister2, x') = 732 {M = M, SA = SA, SL = SL, SS = SS, SU = x', TA = TA, TL = TL, TS = TS, 733 TU = TU}: ConfigRegister2 734 735fun ConfigRegister2_TA_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} 736 : ConfigRegister2, x') = 737 {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = x', TL = TL, TS = TS, 738 TU = TU}: ConfigRegister2 739 740fun ConfigRegister2_TL_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} 741 : ConfigRegister2, x') = 742 {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = x', TS = TS, 743 TU = TU}: ConfigRegister2 744 745fun ConfigRegister2_TS_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} 746 : ConfigRegister2, x') = 747 {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, TS = x', 748 TU = TU}: ConfigRegister2 749 750fun ConfigRegister2_TU_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} 751 : ConfigRegister2, x') = 752 {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, TS = TS, 753 TU = x'}: ConfigRegister2 754 755fun ConfigRegister3_DSPP_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 756 VInt, configregister3'rst}: ConfigRegister3, x') = 757 {DSPP = x', LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, 758 ULRI = ULRI, VEIC = VEIC, VInt = VInt, 759 configregister3'rst = configregister3'rst}: ConfigRegister3 760 761fun ConfigRegister3_LPA_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 762 VInt, configregister3'rst}: ConfigRegister3, x') = 763 {DSPP = DSPP, LPA = x', M = M, MT = MT, SM = SM, SP = SP, TL = TL, 764 ULRI = ULRI, VEIC = VEIC, VInt = VInt, 765 configregister3'rst = configregister3'rst}: ConfigRegister3 766 767fun ConfigRegister3_M_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 768 VInt, configregister3'rst}: ConfigRegister3, x') = 769 {DSPP = DSPP, LPA = LPA, M = x', MT = MT, SM = SM, SP = SP, TL = TL, 770 ULRI = ULRI, VEIC = VEIC, VInt = VInt, 771 configregister3'rst = configregister3'rst}: ConfigRegister3 772 773fun ConfigRegister3_MT_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 774 VInt, configregister3'rst}: ConfigRegister3, x') = 775 {DSPP = DSPP, LPA = LPA, M = M, MT = x', SM = SM, SP = SP, TL = TL, 776 ULRI = ULRI, VEIC = VEIC, VInt = VInt, 777 configregister3'rst = configregister3'rst}: ConfigRegister3 778 779fun ConfigRegister3_SM_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 780 VInt, configregister3'rst}: ConfigRegister3, x') = 781 {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = x', SP = SP, TL = TL, 782 ULRI = ULRI, VEIC = VEIC, VInt = VInt, 783 configregister3'rst = configregister3'rst}: ConfigRegister3 784 785fun ConfigRegister3_SP_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 786 VInt, configregister3'rst}: ConfigRegister3, x') = 787 {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = x', TL = TL, 788 ULRI = ULRI, VEIC = VEIC, VInt = VInt, 789 configregister3'rst = configregister3'rst}: ConfigRegister3 790 791fun ConfigRegister3_TL_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 792 VInt, configregister3'rst}: ConfigRegister3, x') = 793 {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = x', 794 ULRI = ULRI, VEIC = VEIC, VInt = VInt, 795 configregister3'rst = configregister3'rst}: ConfigRegister3 796 797fun ConfigRegister3_ULRI_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 798 VInt, configregister3'rst}: ConfigRegister3, x') = 799 {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, 800 ULRI = x', VEIC = VEIC, VInt = VInt, 801 configregister3'rst = configregister3'rst}: ConfigRegister3 802 803fun ConfigRegister3_VEIC_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 804 VInt, configregister3'rst}: ConfigRegister3, x') = 805 {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, 806 ULRI = ULRI, VEIC = x', VInt = VInt, 807 configregister3'rst = configregister3'rst}: ConfigRegister3 808 809fun ConfigRegister3_VInt_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, 810 VInt, configregister3'rst}: ConfigRegister3, x') = 811 {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, 812 ULRI = ULRI, VEIC = VEIC, VInt = x', 813 configregister3'rst = configregister3'rst}: ConfigRegister3 814 815fun ConfigRegister3_configregister3'rst_rupd ({DSPP, LPA, M, MT, SM, SP, 816 TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = 817 {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, 818 ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = x'} 819 : ConfigRegister3 820 821fun ConfigRegister6_LTLB_rupd ({LTLB, TLBSize, configregister6'rst} 822 : ConfigRegister6, x') = 823 {LTLB = x', TLBSize = TLBSize, configregister6'rst = configregister6'rst} 824 : ConfigRegister6 825 826fun ConfigRegister6_TLBSize_rupd ({LTLB, TLBSize, configregister6'rst} 827 : ConfigRegister6, x') = 828 {LTLB = LTLB, TLBSize = x', configregister6'rst = configregister6'rst} 829 : ConfigRegister6 830 831fun ConfigRegister6_configregister6'rst_rupd ({LTLB, TLBSize, 832 configregister6'rst}: ConfigRegister6, x') = 833 {LTLB = LTLB, TLBSize = TLBSize, configregister6'rst = x'} 834 : ConfigRegister6 835 836fun CauseRegister_BD_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst} 837 : CauseRegister, x') = 838 {BD = x', CE = CE, ExcCode = ExcCode, IP = IP, TI = TI, 839 causeregister'rst = causeregister'rst}: CauseRegister 840 841fun CauseRegister_CE_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst} 842 : CauseRegister, x') = 843 {BD = BD, CE = x', ExcCode = ExcCode, IP = IP, TI = TI, 844 causeregister'rst = causeregister'rst}: CauseRegister 845 846fun CauseRegister_ExcCode_rupd ({BD, CE, ExcCode, IP, TI, 847 causeregister'rst}: CauseRegister, x') = 848 {BD = BD, CE = CE, ExcCode = x', IP = IP, TI = TI, 849 causeregister'rst = causeregister'rst}: CauseRegister 850 851fun CauseRegister_IP_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst} 852 : CauseRegister, x') = 853 {BD = BD, CE = CE, ExcCode = ExcCode, IP = x', TI = TI, 854 causeregister'rst = causeregister'rst}: CauseRegister 855 856fun CauseRegister_TI_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst} 857 : CauseRegister, x') = 858 {BD = BD, CE = CE, ExcCode = ExcCode, IP = IP, TI = x', 859 causeregister'rst = causeregister'rst}: CauseRegister 860 861fun CauseRegister_causeregister'rst_rupd ({BD, CE, ExcCode, IP, TI, 862 causeregister'rst}: CauseRegister, x') = 863 {BD = BD, CE = CE, ExcCode = ExcCode, IP = IP, TI = TI, 864 causeregister'rst = x'}: CauseRegister 865 866fun Context_BadVPN2_rupd ({BadVPN2, PTEBase, context'rst}: Context, x') = 867 {BadVPN2 = x', PTEBase = PTEBase, context'rst = context'rst}: Context 868 869fun Context_PTEBase_rupd ({BadVPN2, PTEBase, context'rst}: Context, x') = 870 {BadVPN2 = BadVPN2, PTEBase = x', context'rst = context'rst}: Context 871 872fun Context_context'rst_rupd ({BadVPN2, PTEBase, context'rst} 873 : Context, x') = 874 {BadVPN2 = BadVPN2, PTEBase = PTEBase, context'rst = x'}: Context 875 876fun XContext_BadVPN2_rupd ({BadVPN2, PTEBase, R, xcontext'rst} 877 : XContext, x') = 878 {BadVPN2 = x', PTEBase = PTEBase, R = R, xcontext'rst = xcontext'rst} 879 : XContext 880 881fun XContext_PTEBase_rupd ({BadVPN2, PTEBase, R, xcontext'rst} 882 : XContext, x') = 883 {BadVPN2 = BadVPN2, PTEBase = x', R = R, xcontext'rst = xcontext'rst} 884 : XContext 885 886fun XContext_R_rupd ({BadVPN2, PTEBase, R, xcontext'rst}: XContext, x') = 887 {BadVPN2 = BadVPN2, PTEBase = PTEBase, R = x', 888 xcontext'rst = xcontext'rst}: XContext 889 890fun XContext_xcontext'rst_rupd ({BadVPN2, PTEBase, R, xcontext'rst} 891 : XContext, x') = 892 {BadVPN2 = BadVPN2, PTEBase = PTEBase, R = R, xcontext'rst = x'} 893 : XContext 894 895fun HWREna_CC_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst}: HWREna, x') = 896 {CC = x', CCRes = CCRes, CPUNum = CPUNum, UL = UL, 897 hwrena'rst = hwrena'rst}: HWREna 898 899fun HWREna_CCRes_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst}: HWREna, x') = 900 {CC = CC, CCRes = x', CPUNum = CPUNum, UL = UL, hwrena'rst = hwrena'rst} 901 : HWREna 902 903fun HWREna_CPUNum_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst}: HWREna, x') = 904 {CC = CC, CCRes = CCRes, CPUNum = x', UL = UL, hwrena'rst = hwrena'rst} 905 : HWREna 906 907fun HWREna_UL_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst}: HWREna, x') = 908 {CC = CC, CCRes = CCRes, CPUNum = CPUNum, UL = x', 909 hwrena'rst = hwrena'rst}: HWREna 910 911fun HWREna_hwrena'rst_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst} 912 : HWREna, x') = 913 {CC = CC, CCRes = CCRes, CPUNum = CPUNum, UL = UL, hwrena'rst = x'} 914 : HWREna 915 916fun CP0_BadVAddr_rupd ({BadVAddr, Cause, Compare, Config, Config1, 917 Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, 918 EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, 919 PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 920 {BadVAddr = x', Cause = Cause, Compare = Compare, Config = Config, 921 Config1 = Config1, Config2 = Config2, Config3 = Config3, 922 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 923 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 924 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 925 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 926 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 927 XContext = XContext}: CP0 928 929fun CP0_Cause_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 930 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 931 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 932 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 933 {BadVAddr = BadVAddr, Cause = x', Compare = Compare, Config = Config, 934 Config1 = Config1, Config2 = Config2, Config3 = Config3, 935 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 936 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 937 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 938 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 939 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 940 XContext = XContext}: CP0 941 942fun CP0_Compare_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 943 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 944 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 945 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 946 {BadVAddr = BadVAddr, Cause = Cause, Compare = x', Config = Config, 947 Config1 = Config1, Config2 = Config2, Config3 = Config3, 948 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 949 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 950 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 951 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 952 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 953 XContext = XContext}: CP0 954 955fun CP0_Config_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 956 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 957 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 958 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 959 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = x', 960 Config1 = Config1, Config2 = Config2, Config3 = Config3, 961 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 962 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 963 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 964 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 965 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 966 XContext = XContext}: CP0 967 968fun CP0_Config1_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 969 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 970 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 971 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 972 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 973 Config1 = x', Config2 = Config2, Config3 = Config3, Config6 = Config6, 974 Context = Context, Count = Count, Debug = Debug, EPC = EPC, 975 EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 976 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 977 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 978 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 979 XContext = XContext}: CP0 980 981fun CP0_Config2_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 982 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 983 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 984 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 985 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 986 Config1 = Config1, Config2 = x', Config3 = Config3, Config6 = Config6, 987 Context = Context, Count = Count, Debug = Debug, EPC = EPC, 988 EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 989 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 990 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 991 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 992 XContext = XContext}: CP0 993 994fun CP0_Config3_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 995 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 996 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 997 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 998 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 999 Config1 = Config1, Config2 = Config2, Config3 = x', Config6 = Config6, 1000 Context = Context, Count = Count, Debug = Debug, EPC = EPC, 1001 EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1002 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1003 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1004 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1005 XContext = XContext}: CP0 1006 1007fun CP0_Config6_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1008 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1009 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1010 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1011 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1012 Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = x', 1013 Context = Context, Count = Count, Debug = Debug, EPC = EPC, 1014 EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1015 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1016 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1017 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1018 XContext = XContext}: CP0 1019 1020fun CP0_Context_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1021 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1022 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1023 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1024 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1025 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1026 Config6 = Config6, Context = x', Count = Count, Debug = Debug, 1027 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1028 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1029 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1030 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1031 XContext = XContext}: CP0 1032 1033fun CP0_Count_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1034 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1035 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1036 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1037 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1038 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1039 Config6 = Config6, Context = Context, Count = x', Debug = Debug, 1040 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1041 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1042 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1043 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1044 XContext = XContext}: CP0 1045 1046fun CP0_Debug_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1047 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1048 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1049 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1050 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1051 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1052 Config6 = Config6, Context = Context, Count = Count, Debug = x', 1053 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1054 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1055 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1056 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1057 XContext = XContext}: CP0 1058 1059fun CP0_EPC_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1060 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1061 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1062 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1063 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1064 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1065 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1066 EPC = x', EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1067 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1068 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1069 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1070 XContext = XContext}: CP0 1071 1072fun CP0_EntryHi_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1073 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1074 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1075 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1076 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1077 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1078 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1079 EPC = EPC, EntryHi = x', EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1080 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1081 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1082 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1083 XContext = XContext}: CP0 1084 1085fun CP0_EntryLo0_rupd ({BadVAddr, Cause, Compare, Config, Config1, 1086 Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, 1087 EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, 1088 PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1089 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1090 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1091 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1092 EPC = EPC, EntryHi = EntryHi, EntryLo0 = x', EntryLo1 = EntryLo1, 1093 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1094 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1095 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1096 XContext = XContext}: CP0 1097 1098fun CP0_EntryLo1_rupd ({BadVAddr, Cause, Compare, Config, Config1, 1099 Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, 1100 EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, 1101 PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1102 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1103 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1104 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1105 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = x', 1106 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1107 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1108 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1109 XContext = XContext}: CP0 1110 1111fun CP0_ErrCtl_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1112 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1113 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1114 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1115 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1116 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1117 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1118 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1119 ErrCtl = x', ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1120 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1121 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1122 XContext = XContext}: CP0 1123 1124fun CP0_ErrorEPC_rupd ({BadVAddr, Cause, Compare, Config, Config1, 1125 Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, 1126 EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, 1127 PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1128 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1129 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1130 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1131 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1132 ErrCtl = ErrCtl, ErrorEPC = x', HWREna = HWREna, Index = Index, 1133 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1134 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1135 XContext = XContext}: CP0 1136 1137fun CP0_HWREna_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1138 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1139 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1140 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1141 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1142 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1143 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1144 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1145 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = x', Index = Index, 1146 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1147 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1148 XContext = XContext}: CP0 1149 1150fun CP0_Index_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1151 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1152 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1153 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1154 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1155 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1156 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1157 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1158 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = x', 1159 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1160 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1161 XContext = XContext}: CP0 1162 1163fun CP0_LLAddr_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1164 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1165 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1166 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1167 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1168 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1169 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1170 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1171 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1172 LLAddr = x', PRId = PRId, PageMask = PageMask, Random = Random, 1173 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1174 XContext = XContext}: CP0 1175 1176fun CP0_PRId_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1177 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1178 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1179 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1180 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1181 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1182 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1183 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1184 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1185 LLAddr = LLAddr, PRId = x', PageMask = PageMask, Random = Random, 1186 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1187 XContext = XContext}: CP0 1188 1189fun CP0_PageMask_rupd ({BadVAddr, Cause, Compare, Config, Config1, 1190 Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, 1191 EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, 1192 PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1193 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1194 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1195 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1196 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1197 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1198 LLAddr = LLAddr, PRId = PRId, PageMask = x', Random = Random, 1199 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1200 XContext = XContext}: CP0 1201 1202fun CP0_Random_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1203 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1204 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1205 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1206 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1207 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1208 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1209 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1210 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1211 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = x', 1212 Status = Status, UsrLocal = UsrLocal, Wired = Wired, 1213 XContext = XContext}: CP0 1214 1215fun CP0_Status_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1216 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1217 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1218 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1219 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1220 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1221 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1222 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1223 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1224 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1225 Status = x', UsrLocal = UsrLocal, Wired = Wired, XContext = XContext} 1226 : CP0 1227 1228fun CP0_UsrLocal_rupd ({BadVAddr, Cause, Compare, Config, Config1, 1229 Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, 1230 EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, 1231 PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1232 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1233 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1234 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1235 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1236 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1237 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1238 Status = Status, UsrLocal = x', Wired = Wired, XContext = XContext} 1239 : CP0 1240 1241fun CP0_Wired_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, 1242 Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, 1243 EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, 1244 Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1245 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1246 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1247 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1248 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1249 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1250 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1251 Status = Status, UsrLocal = UsrLocal, Wired = x', XContext = XContext} 1252 : CP0 1253 1254fun CP0_XContext_rupd ({BadVAddr, Cause, Compare, Config, Config1, 1255 Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, 1256 EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, 1257 PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = 1258 {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, 1259 Config1 = Config1, Config2 = Config2, Config3 = Config3, 1260 Config6 = Config6, Context = Context, Count = Count, Debug = Debug, 1261 EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, 1262 ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, 1263 LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, 1264 Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = x'} 1265 : CP0 1266 1267fun FCSR_ABS2008_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1268 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1269 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1270 {ABS2008 = x', CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1271 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1272 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1273 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1274 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1275 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1276 1277fun FCSR_CauseE_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1278 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1279 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1280 {ABS2008 = ABS2008, CauseE = x', CauseI = CauseI, CauseO = CauseO, 1281 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1282 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1283 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1284 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1285 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1286 1287fun FCSR_CauseI_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1288 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1289 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1290 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = x', CauseO = CauseO, 1291 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1292 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1293 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1294 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1295 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1296 1297fun FCSR_CauseO_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1298 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1299 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1300 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = x', 1301 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1302 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1303 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1304 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1305 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1306 1307fun FCSR_CauseU_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1308 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1309 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1310 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1311 CauseU = x', CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1312 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1313 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1314 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1315 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1316 1317fun FCSR_CauseV_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1318 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1319 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1320 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1321 CauseU = CauseU, CauseV = x', CauseZ = CauseZ, EnableI = EnableI, 1322 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1323 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1324 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1325 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1326 1327fun FCSR_CauseZ_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1328 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1329 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1330 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1331 CauseU = CauseU, CauseV = CauseV, CauseZ = x', EnableI = EnableI, 1332 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1333 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1334 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1335 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1336 1337fun FCSR_EnableI_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1338 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1339 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1340 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1341 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = x', 1342 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1343 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1344 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1345 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1346 1347fun FCSR_EnableO_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1348 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1349 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1350 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1351 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1352 EnableO = x', EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, 1353 FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, 1354 FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, 1355 fcsr'rst = fcsr'rst}: FCSR 1356 1357fun FCSR_EnableU_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1358 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1359 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1360 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1361 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1362 EnableO = EnableO, EnableU = x', EnableV = EnableV, EnableZ = EnableZ, 1363 FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, 1364 FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, 1365 fcsr'rst = fcsr'rst}: FCSR 1366 1367fun FCSR_EnableV_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1368 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1369 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1370 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1371 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1372 EnableO = EnableO, EnableU = EnableU, EnableV = x', EnableZ = EnableZ, 1373 FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, 1374 FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, 1375 fcsr'rst = fcsr'rst}: FCSR 1376 1377fun FCSR_EnableZ_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1378 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1379 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1380 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1381 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1382 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = x', 1383 FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, 1384 FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, 1385 fcsr'rst = fcsr'rst}: FCSR 1386 1387fun FCSR_FCC_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1388 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1389 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1390 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1391 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1392 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1393 EnableZ = EnableZ, FCC = x', FS = FS, FlagI = FlagI, FlagO = FlagO, 1394 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1395 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1396 1397fun FCSR_FS_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1398 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1399 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1400 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1401 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1402 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1403 EnableZ = EnableZ, FCC = FCC, FS = x', FlagI = FlagI, FlagO = FlagO, 1404 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1405 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1406 1407fun FCSR_FlagI_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1408 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1409 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1410 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1411 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1412 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1413 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = x', FlagO = FlagO, 1414 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1415 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1416 1417fun FCSR_FlagO_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1418 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1419 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1420 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1421 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1422 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1423 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = x', 1424 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1425 RM = RM, fcsr'rst = fcsr'rst}: FCSR 1426 1427fun FCSR_FlagU_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1428 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1429 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1430 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1431 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1432 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1433 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1434 FlagU = x', FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, 1435 fcsr'rst = fcsr'rst}: FCSR 1436 1437fun FCSR_FlagV_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1438 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1439 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1440 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1441 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1442 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1443 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1444 FlagU = FlagU, FlagV = x', FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, 1445 fcsr'rst = fcsr'rst}: FCSR 1446 1447fun FCSR_FlagZ_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1448 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1449 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1450 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1451 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1452 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1453 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1454 FlagU = FlagU, FlagV = FlagV, FlagZ = x', NAN2008 = NAN2008, RM = RM, 1455 fcsr'rst = fcsr'rst}: FCSR 1456 1457fun FCSR_NAN2008_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1458 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1459 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1460 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1461 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1462 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1463 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1464 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = x', RM = RM, 1465 fcsr'rst = fcsr'rst}: FCSR 1466 1467fun FCSR_RM_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1468 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1469 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1470 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1471 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1472 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1473 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1474 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1475 RM = x', fcsr'rst = fcsr'rst}: FCSR 1476 1477fun FCSR_fcsr'rst_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, 1478 CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, 1479 FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = 1480 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, 1481 CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, 1482 EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, 1483 EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, 1484 FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, 1485 RM = RM, fcsr'rst = x'}: FCSR 1486 1487fun FIR_ASE_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} 1488 : FIR, x') = 1489 {ASE = x', D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, 1490 S = S, W = W, fir'rst = fir'rst}: FIR 1491 1492fun FIR_D_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst}: FIR, x') = 1493 {ASE = ASE, D = x', F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, 1494 S = S, W = W, fir'rst = fir'rst}: FIR 1495 1496fun FIR_F64_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} 1497 : FIR, x') = 1498 {ASE = ASE, D = D, F64 = x', L = L, PS = PS, PrID = PrID, Rev = Rev, 1499 S = S, W = W, fir'rst = fir'rst}: FIR 1500 1501fun FIR_L_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst}: FIR, x') = 1502 {ASE = ASE, D = D, F64 = F64, L = x', PS = PS, PrID = PrID, Rev = Rev, 1503 S = S, W = W, fir'rst = fir'rst}: FIR 1504 1505fun FIR_PS_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} 1506 : FIR, x') = 1507 {ASE = ASE, D = D, F64 = F64, L = L, PS = x', PrID = PrID, Rev = Rev, 1508 S = S, W = W, fir'rst = fir'rst}: FIR 1509 1510fun FIR_PrID_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} 1511 : FIR, x') = 1512 {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = x', Rev = Rev, 1513 S = S, W = W, fir'rst = fir'rst}: FIR 1514 1515fun FIR_Rev_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} 1516 : FIR, x') = 1517 {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = x', 1518 S = S, W = W, fir'rst = fir'rst}: FIR 1519 1520fun FIR_S_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst}: FIR, x') = 1521 {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, 1522 S = x', W = W, fir'rst = fir'rst}: FIR 1523 1524fun FIR_W_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst}: FIR, x') = 1525 {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, 1526 S = S, W = x', fir'rst = fir'rst}: FIR 1527 1528fun FIR_fir'rst_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} 1529 : FIR, x') = 1530 {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, 1531 S = S, W = W, fir'rst = x'}: FIR 1532 1533(* ------------------------------------------------------------------------- 1534 Exceptions 1535 ------------------------------------------------------------------------- *) 1536 1537exception UNPREDICTABLE of string 1538 1539(* ------------------------------------------------------------------------- 1540 Global variables (state) 1541 ------------------------------------------------------------------------- *) 1542 1543val BranchDelay = ref (NONE): ((BitsN.nbit option) option) ref 1544 1545val BranchTo = ref (NONE): ((bool * BitsN.nbit) option) ref 1546 1547val CP0 = ref 1548 ({BadVAddr = BitsN.B(0x0,64), 1549 Cause = 1550 {BD = false, CE = BitsN.B(0x0,2), ExcCode = BitsN.B(0x0,5), 1551 IP = BitsN.B(0x0,8), TI = false, 1552 causeregister'rst = BitsN.B(0x0,15)}, Compare = BitsN.B(0x0,32), 1553 Config = 1554 {AR = BitsN.B(0x0,3), AT = BitsN.B(0x0,2), BE = false, 1555 K0 = BitsN.B(0x0,3), M = false, MT = BitsN.B(0x0,3), 1556 configregister'rst = BitsN.B(0x0,19)}, 1557 Config1 = 1558 {C2 = false, CA = false, DA = BitsN.B(0x0,3), DL = BitsN.B(0x0,3), 1559 DS = BitsN.B(0x0,3), EP = false, FP = false, IA = BitsN.B(0x0,3), 1560 IL = BitsN.B(0x0,3), IS = BitsN.B(0x0,3), M = false, MD = false, 1561 MMUSize = BitsN.B(0x0,6), PC = false, WR = false}, 1562 Config2 = 1563 {M = false, SA = BitsN.B(0x0,4), SL = BitsN.B(0x0,4), 1564 SS = BitsN.B(0x0,4), SU = BitsN.B(0x0,4), TA = BitsN.B(0x0,4), 1565 TL = BitsN.B(0x0,4), TS = BitsN.B(0x0,4), TU = BitsN.B(0x0,3)}, 1566 Config3 = 1567 {DSPP = false, LPA = false, M = false, MT = false, SM = false, 1568 SP = false, TL = false, ULRI = false, VEIC = false, VInt = false, 1569 configregister3'rst = BitsN.B(0x0,22)}, 1570 Config6 = 1571 {LTLB = false, TLBSize = BitsN.B(0x0,16), 1572 configregister6'rst = BitsN.B(0x0,15)}, 1573 Context = 1574 {BadVPN2 = BitsN.B(0x0,19), PTEBase = BitsN.B(0x0,41), 1575 context'rst = BitsN.B(0x0,4)}, Count = BitsN.B(0x0,32), 1576 Debug = BitsN.B(0x0,32), EPC = BitsN.B(0x0,64), 1577 EntryHi = 1578 {ASID = BitsN.B(0x0,8), R = BitsN.B(0x0,2), VPN2 = BitsN.B(0x0,27), 1579 entryhi'rst = BitsN.B(0x0,27)}, 1580 EntryLo0 = 1581 {C = BitsN.B(0x0,3), D = false, G = false, PFN = BitsN.B(0x0,28), 1582 V = false, entrylo'rst = BitsN.B(0x0,30)}, 1583 EntryLo1 = 1584 {C = BitsN.B(0x0,3), D = false, G = false, PFN = BitsN.B(0x0,28), 1585 V = false, entrylo'rst = BitsN.B(0x0,30)}, 1586 ErrCtl = BitsN.B(0x0,32), ErrorEPC = BitsN.B(0x0,64), 1587 HWREna = 1588 {CC = false, CCRes = false, CPUNum = false, UL = false, 1589 hwrena'rst = BitsN.B(0x0,28)}, 1590 Index = 1591 {Index = BitsN.B(0x0,8), P = false, index'rst = BitsN.B(0x0,23)}, 1592 LLAddr = BitsN.B(0x0,64), PRId = BitsN.B(0x0,32), 1593 PageMask = {Mask = BitsN.B(0x0,12), pagemask'rst = BitsN.B(0x0,20)}, 1594 Random = {Random = BitsN.B(0x0,8), random'rst = BitsN.B(0x0,24)}, 1595 Status = 1596 {BEV = false, CU0 = false, CU1 = false, ERL = false, EXL = false, 1597 FR = false, IE = false, IM = BitsN.B(0x0,8), KSU = BitsN.B(0x0,2), 1598 KX = false, RE = false, SX = false, UX = false, 1599 statusregister'rst = BitsN.B(0x0,11)}, UsrLocal = BitsN.B(0x0,64), 1600 Wired = {Wired = BitsN.B(0x0,8), wired'rst = BitsN.B(0x0,24)}, 1601 XContext = 1602 {BadVPN2 = BitsN.B(0x0,27), PTEBase = BitsN.B(0x0,31), 1603 R = BitsN.B(0x0,2), xcontext'rst = BitsN.B(0x0,4)}}): CP0 ref 1604 1605val FGR = ref (Map.mkMap(SOME 32,BitsN.B(0x0,64))) 1606 : (BitsN.nbit Map.map) ref 1607 1608val LLbit = ref (NONE): (bool option) ref 1609 1610val MEM = ref (Map.mkMap(SOME 18446744073709551616,BitsN.B(0x0,8))) 1611 : (BitsN.nbit Map.map) ref 1612 1613val PC = ref (BitsN.B(0x0,64)): BitsN.nbit ref 1614 1615val exceptionSignalled = ref (false): bool ref 1616 1617val fcsr = ref 1618 ({ABS2008 = false, CauseE = false, CauseI = false, CauseO = false, 1619 CauseU = false, CauseV = false, CauseZ = false, EnableI = false, 1620 EnableO = false, EnableU = false, EnableV = false, EnableZ = false, 1621 FCC = BitsN.B(0x0,8), FS = false, FlagI = false, FlagO = false, 1622 FlagU = false, FlagV = false, FlagZ = false, NAN2008 = false, 1623 RM = BitsN.B(0x0,2), fcsr'rst = BitsN.B(0x0,3)}): FCSR ref 1624 1625val fir = ref 1626 ({ASE = false, D = false, F64 = false, L = false, PS = false, 1627 PrID = BitsN.B(0x0,8), Rev = BitsN.B(0x0,8), S = false, W = false, 1628 fir'rst = BitsN.B(0x0,9)}): FIR ref 1629 1630val gpr = ref (Map.mkMap(SOME 32,BitsN.B(0x0,64))) 1631 : (BitsN.nbit Map.map) ref 1632 1633val hi = ref (NONE): (BitsN.nbit option) ref 1634 1635val lo = ref (NONE): (BitsN.nbit option) ref 1636 1637(* ------------------------------------------------------------------------- 1638 Main specification 1639 ------------------------------------------------------------------------- *) 1640 1641local 1642 fun tuple'32 [t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16, 1643 t17,t18,t19,t20,t21,t22,t23,t24,t25,t26,t27,t28,t29,t30, 1644 t31] = 1645 (t0, 1646 (t1, 1647 (t2, 1648 (t3, 1649 (t4, 1650 (t5, 1651 (t6, 1652 (t7, 1653 (t8, 1654 (t9, 1655 (t10, 1656 (t11, 1657 (t12, 1658 (t13, 1659 (t14, 1660 (t15, 1661 (t16, 1662 (t17, 1663 (t18, 1664 (t19, 1665 (t20, 1666 (t21, 1667 (t22, 1668 (t23, 1669 (t24,(t25,(t26,(t27,(t28,(t29,(t30,t31))))))))))))))))))))))))))))))) 1670 | tuple'32 (_: bool list) = raise Fail "tuple'32" 1671in 1672 val boolify'32 = tuple'32 o BitsN.toList 1673end 1674 1675local 1676 fun tuple'5 [t0,t1,t2,t3,t4] = (t0,(t1,(t2,(t3,t4)))) 1677 | tuple'5 (_: bool list) = raise Fail "tuple'5" 1678in 1679 val boolify'5 = tuple'5 o BitsN.toList 1680end 1681 1682local 1683 fun tuple'26 [t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16, 1684 t17,t18,t19,t20,t21,t22,t23,t24,t25] = 1685 (t0, 1686 (t1, 1687 (t2, 1688 (t3, 1689 (t4, 1690 (t5, 1691 (t6, 1692 (t7, 1693 (t8, 1694 (t9, 1695 (t10, 1696 (t11, 1697 (t12, 1698 (t13, 1699 (t14, 1700 (t15, 1701 (t16, 1702 (t17,(t18,(t19,(t20,(t21,(t22,(t23,(t24,t25))))))))))))))))))))))))) 1703 | tuple'26 (_: bool list) = raise Fail "tuple'26" 1704in 1705 val boolify'26 = tuple'26 o BitsN.toList 1706end 1707 1708fun rec'Index x = 1709 {Index = BitsN.bits(7,0) x, P = BitsN.bit(x,31), 1710 index'rst = BitsN.bits(30,8) x}; 1711 1712fun reg'Index x = 1713 case x of 1714 {Index = Index, P = P, index'rst = index'rst} => 1715 BitsN.concat[BitsN.fromBit P,index'rst,Index]; 1716 1717fun write'rec'Index (_,x) = reg'Index x; 1718 1719fun write'reg'Index (_,x) = rec'Index x; 1720 1721fun rec'Random x = 1722 {Random = BitsN.bits(7,0) x, random'rst = BitsN.bits(31,8) x}; 1723 1724fun reg'Random x = 1725 case x of 1726 {Random = Random, random'rst = random'rst} => 1727 BitsN.@@(random'rst,Random); 1728 1729fun write'rec'Random (_,x) = reg'Random x; 1730 1731fun write'reg'Random (_,x) = rec'Random x; 1732 1733fun rec'Wired x = 1734 {Wired = BitsN.bits(7,0) x, wired'rst = BitsN.bits(31,8) x}; 1735 1736fun reg'Wired x = 1737 case x of 1738 {Wired = Wired, wired'rst = wired'rst} => BitsN.@@(wired'rst,Wired); 1739 1740fun write'rec'Wired (_,x) = reg'Wired x; 1741 1742fun write'reg'Wired (_,x) = rec'Wired x; 1743 1744fun rec'EntryLo x = 1745 {C = BitsN.bits(5,3) x, D = BitsN.bit(x,2), G = BitsN.bit(x,0), 1746 PFN = BitsN.bits(33,6) x, V = BitsN.bit(x,1), 1747 entrylo'rst = BitsN.bits(63,34) x}; 1748 1749fun reg'EntryLo x = 1750 case x of 1751 {C = C, D = D, G = G, PFN = PFN, V = V, entrylo'rst = entrylo'rst} => 1752 BitsN.concat 1753 [entrylo'rst,PFN,C,BitsN.fromBit D,BitsN.fromBit V, 1754 BitsN.fromBit G]; 1755 1756fun write'rec'EntryLo (_,x) = reg'EntryLo x; 1757 1758fun write'reg'EntryLo (_,x) = rec'EntryLo x; 1759 1760fun rec'PageMask x = 1761 {Mask = BitsN.bits(24,13) x, 1762 pagemask'rst = BitsN.@@(BitsN.bits(12,0) x,BitsN.bits(31,25) x)}; 1763 1764fun reg'PageMask x = 1765 case x of 1766 {Mask = Mask, pagemask'rst = pagemask'rst} => 1767 BitsN.concat 1768 [BitsN.bits(6,0) pagemask'rst,Mask,BitsN.bits(19,7) pagemask'rst]; 1769 1770fun write'rec'PageMask (_,x) = reg'PageMask x; 1771 1772fun write'reg'PageMask (_,x) = rec'PageMask x; 1773 1774fun rec'EntryHi x = 1775 {ASID = BitsN.bits(7,0) x, R = BitsN.bits(63,62) x, 1776 VPN2 = BitsN.bits(39,13) x, 1777 entryhi'rst = BitsN.@@(BitsN.bits(12,8) x,BitsN.bits(61,40) x)}; 1778 1779fun reg'EntryHi x = 1780 case x of 1781 {ASID = ASID, R = R, VPN2 = VPN2, entryhi'rst = entryhi'rst} => 1782 BitsN.concat 1783 [R,BitsN.bits(21,0) entryhi'rst,VPN2, 1784 BitsN.bits(26,22) entryhi'rst,ASID]; 1785 1786fun write'rec'EntryHi (_,x) = reg'EntryHi x; 1787 1788fun write'reg'EntryHi (_,x) = rec'EntryHi x; 1789 1790fun rec'StatusRegister x = 1791 {BEV = BitsN.bit(x,22), CU0 = BitsN.bit(x,28), CU1 = BitsN.bit(x,29), 1792 ERL = BitsN.bit(x,2), EXL = BitsN.bit(x,1), FR = BitsN.bit(x,26), 1793 IE = BitsN.bit(x,0), IM = BitsN.bits(15,8) x, KSU = BitsN.bits(4,3) x, 1794 KX = BitsN.bit(x,7), RE = BitsN.bit(x,25), SX = BitsN.bit(x,6), 1795 UX = BitsN.bit(x,5), 1796 statusregister'rst = 1797 BitsN.concat 1798 [BitsN.bits(21,16) x,BitsN.bits(24,23) x,BitsN.bits(27,27) x, 1799 BitsN.bits(31,30) x]}; 1800 1801fun reg'StatusRegister x = 1802 case x of 1803 {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, 1804 IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, 1805 statusregister'rst = statusregister'rst} => 1806 BitsN.concat 1807 [BitsN.bits(1,0) statusregister'rst,BitsN.fromBit CU1, 1808 BitsN.fromBit CU0,BitsN.bits(2,2) statusregister'rst, 1809 BitsN.fromBit FR,BitsN.fromBit RE, 1810 BitsN.bits(4,3) statusregister'rst,BitsN.fromBit BEV, 1811 BitsN.bits(10,5) statusregister'rst,IM,BitsN.fromBit KX, 1812 BitsN.fromBit SX,BitsN.fromBit UX,KSU,BitsN.fromBit ERL, 1813 BitsN.fromBit EXL,BitsN.fromBit IE]; 1814 1815fun write'rec'StatusRegister (_,x) = reg'StatusRegister x; 1816 1817fun write'reg'StatusRegister (_,x) = rec'StatusRegister x; 1818 1819fun rec'ConfigRegister x = 1820 {AR = BitsN.bits(12,10) x, AT = BitsN.bits(14,13) x, 1821 BE = BitsN.bit(x,15), K0 = BitsN.bits(2,0) x, M = BitsN.bit(x,31), 1822 MT = BitsN.bits(9,7) x, 1823 configregister'rst = BitsN.@@(BitsN.bits(6,3) x,BitsN.bits(30,16) x)}; 1824 1825fun reg'ConfigRegister x = 1826 case x of 1827 {AR = AR, AT = AT, BE = BE, K0 = K0, M = M, MT = MT, 1828 configregister'rst = configregister'rst} => 1829 BitsN.concat 1830 [BitsN.fromBit M,BitsN.bits(14,0) configregister'rst, 1831 BitsN.fromBit BE,AT,AR,MT,BitsN.bits(18,15) configregister'rst, 1832 K0]; 1833 1834fun write'rec'ConfigRegister (_,x) = reg'ConfigRegister x; 1835 1836fun write'reg'ConfigRegister (_,x) = rec'ConfigRegister x; 1837 1838fun rec'ConfigRegister1 x = 1839 {C2 = BitsN.bit(x,6), CA = BitsN.bit(x,2), DA = BitsN.bits(9,7) x, 1840 DL = BitsN.bits(12,10) x, DS = BitsN.bits(15,13) x, 1841 EP = BitsN.bit(x,1), FP = BitsN.bit(x,0), IA = BitsN.bits(18,16) x, 1842 IL = BitsN.bits(21,19) x, IS = BitsN.bits(24,22) x, 1843 M = BitsN.bit(x,31), MD = BitsN.bit(x,5), 1844 MMUSize = BitsN.bits(30,25) x, PC = BitsN.bit(x,4), WR = BitsN.bit(x,3)}; 1845 1846fun reg'ConfigRegister1 x = 1847 case x of 1848 {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, 1849 IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, 1850 PC = PC, WR = WR} => 1851 BitsN.concat 1852 [BitsN.fromBit M,MMUSize,IS,IL,IA,DS,DL,DA,BitsN.fromBit C2, 1853 BitsN.fromBit MD,BitsN.fromBit PC,BitsN.fromBit WR, 1854 BitsN.fromBit CA,BitsN.fromBit EP,BitsN.fromBit FP]; 1855 1856fun write'rec'ConfigRegister1 (_,x) = reg'ConfigRegister1 x; 1857 1858fun write'reg'ConfigRegister1 (_,x) = rec'ConfigRegister1 x; 1859 1860fun rec'ConfigRegister2 x = 1861 {M = BitsN.bit(x,31), SA = BitsN.bits(3,0) x, SL = BitsN.bits(7,4) x, 1862 SS = BitsN.bits(11,8) x, SU = BitsN.bits(15,12) x, 1863 TA = BitsN.bits(19,16) x, TL = BitsN.bits(23,20) x, 1864 TS = BitsN.bits(27,24) x, TU = BitsN.bits(30,28) x}; 1865 1866fun reg'ConfigRegister2 x = 1867 case x of 1868 {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, 1869 TS = TS, TU = TU} => 1870 BitsN.concat[BitsN.fromBit M,TU,TS,TL,TA,SU,SS,SL,SA]; 1871 1872fun write'rec'ConfigRegister2 (_,x) = reg'ConfigRegister2 x; 1873 1874fun write'reg'ConfigRegister2 (_,x) = rec'ConfigRegister2 x; 1875 1876fun rec'ConfigRegister3 x = 1877 {DSPP = BitsN.bit(x,10), LPA = BitsN.bit(x,7), M = BitsN.bit(x,31), 1878 MT = BitsN.bit(x,2), SM = BitsN.bit(x,1), SP = BitsN.bit(x,4), 1879 TL = BitsN.bit(x,0), ULRI = BitsN.bit(x,13), VEIC = BitsN.bit(x,6), 1880 VInt = BitsN.bit(x,5), 1881 configregister3'rst = 1882 BitsN.concat 1883 [BitsN.bits(3,3) x,BitsN.bits(9,8) x,BitsN.bits(12,11) x, 1884 BitsN.bits(30,14) x]}; 1885 1886fun reg'ConfigRegister3 x = 1887 case x of 1888 {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, 1889 ULRI = ULRI, VEIC = VEIC, VInt = VInt, 1890 configregister3'rst = configregister3'rst} => 1891 BitsN.concat 1892 [BitsN.fromBit M,BitsN.bits(16,0) configregister3'rst, 1893 BitsN.fromBit ULRI,BitsN.bits(18,17) configregister3'rst, 1894 BitsN.fromBit DSPP,BitsN.bits(20,19) configregister3'rst, 1895 BitsN.fromBit LPA,BitsN.fromBit VEIC,BitsN.fromBit VInt, 1896 BitsN.fromBit SP,BitsN.bits(21,21) configregister3'rst, 1897 BitsN.fromBit MT,BitsN.fromBit SM,BitsN.fromBit TL]; 1898 1899fun write'rec'ConfigRegister3 (_,x) = reg'ConfigRegister3 x; 1900 1901fun write'reg'ConfigRegister3 (_,x) = rec'ConfigRegister3 x; 1902 1903fun rec'ConfigRegister6 x = 1904 {LTLB = BitsN.bit(x,2), TLBSize = BitsN.bits(31,16) x, 1905 configregister6'rst = BitsN.@@(BitsN.bits(1,0) x,BitsN.bits(15,3) x)}; 1906 1907fun reg'ConfigRegister6 x = 1908 case x of 1909 {LTLB = LTLB, TLBSize = TLBSize, 1910 configregister6'rst = configregister6'rst} => 1911 BitsN.concat 1912 [TLBSize,BitsN.bits(12,0) configregister6'rst,BitsN.fromBit LTLB, 1913 BitsN.bits(14,13) configregister6'rst]; 1914 1915fun write'rec'ConfigRegister6 (_,x) = reg'ConfigRegister6 x; 1916 1917fun write'reg'ConfigRegister6 (_,x) = rec'ConfigRegister6 x; 1918 1919fun rec'CauseRegister x = 1920 {BD = BitsN.bit(x,31), CE = BitsN.bits(29,28) x, 1921 ExcCode = BitsN.bits(6,2) x, IP = BitsN.bits(15,8) x, 1922 TI = BitsN.bit(x,30), 1923 causeregister'rst = 1924 BitsN.concat[BitsN.bits(1,0) x,BitsN.bits(7,7) x,BitsN.bits(27,16) x]}; 1925 1926fun reg'CauseRegister x = 1927 case x of 1928 {BD = BD, CE = CE, ExcCode = ExcCode, IP = IP, TI = TI, 1929 causeregister'rst = causeregister'rst} => 1930 BitsN.concat 1931 [BitsN.fromBit BD,BitsN.fromBit TI,CE, 1932 BitsN.bits(11,0) causeregister'rst,IP, 1933 BitsN.bits(12,12) causeregister'rst,ExcCode, 1934 BitsN.bits(14,13) causeregister'rst]; 1935 1936fun write'rec'CauseRegister (_,x) = reg'CauseRegister x; 1937 1938fun write'reg'CauseRegister (_,x) = rec'CauseRegister x; 1939 1940fun rec'Context x = 1941 {BadVPN2 = BitsN.bits(22,4) x, PTEBase = BitsN.bits(63,23) x, 1942 context'rst = BitsN.bits(3,0) x}; 1943 1944fun reg'Context x = 1945 case x of 1946 {BadVPN2 = BadVPN2, PTEBase = PTEBase, context'rst = context'rst} => 1947 BitsN.concat[PTEBase,BadVPN2,context'rst]; 1948 1949fun write'rec'Context (_,x) = reg'Context x; 1950 1951fun write'reg'Context (_,x) = rec'Context x; 1952 1953fun rec'XContext x = 1954 {BadVPN2 = BitsN.bits(30,4) x, PTEBase = BitsN.bits(63,33) x, 1955 R = BitsN.bits(32,31) x, xcontext'rst = BitsN.bits(3,0) x}; 1956 1957fun reg'XContext x = 1958 case x of 1959 {BadVPN2 = BadVPN2, PTEBase = PTEBase, R = R, 1960 xcontext'rst = xcontext'rst} => 1961 BitsN.concat[PTEBase,R,BadVPN2,xcontext'rst]; 1962 1963fun write'rec'XContext (_,x) = reg'XContext x; 1964 1965fun write'reg'XContext (_,x) = rec'XContext x; 1966 1967fun rec'HWREna x = 1968 {CC = BitsN.bit(x,2), CCRes = BitsN.bit(x,3), CPUNum = BitsN.bit(x,0), 1969 UL = BitsN.bit(x,29), 1970 hwrena'rst = 1971 BitsN.concat 1972 [BitsN.bits(1,1) x,BitsN.bits(28,4) x,BitsN.bits(31,30) x]}; 1973 1974fun reg'HWREna x = 1975 case x of 1976 {CC = CC, CCRes = CCRes, CPUNum = CPUNum, UL = UL, 1977 hwrena'rst = hwrena'rst} => 1978 BitsN.concat 1979 [BitsN.bits(1,0) hwrena'rst,BitsN.fromBit UL, 1980 BitsN.bits(26,2) hwrena'rst,BitsN.fromBit CCRes, 1981 BitsN.fromBit CC,BitsN.bits(27,27) hwrena'rst, 1982 BitsN.fromBit CPUNum]; 1983 1984fun write'rec'HWREna (_,x) = reg'HWREna x; 1985 1986fun write'reg'HWREna (_,x) = rec'HWREna x; 1987 1988fun ConditionalBranch (b,offset) = 1989 BranchTo := 1990 (Option.SOME 1991 (if b 1992 then (false, 1993 BitsN.+ 1994 (BitsN.+((!PC),BitsN.B(0x4,64)), 1995 BitsN.<<(BitsN.signExtend 64 offset,2))) 1996 else (true,BitsN.+((!PC),BitsN.B(0x4,64))))); 1997 1998fun ConditionalBranchLikely (b,offset) = 1999 if b 2000 then BranchTo := 2001 (Option.SOME 2002 (false, 2003 BitsN.+ 2004 (BitsN.+((!PC),BitsN.B(0x4,64)), 2005 BitsN.<<(BitsN.signExtend 64 offset,2)))) 2006 else if Option.isSome (!BranchDelay) 2007 then BranchTo := (Option.SOME(true,BitsN.+((!PC),BitsN.B(0x8,64)))) 2008 else PC := (BitsN.+((!PC),BitsN.B(0x4,64))); 2009 2010fun NotWordValue value = 2011 let 2012 val top = BitsN.bits(63,31) value 2013 in 2014 (not(top = (BitsN.B(0x0,33)))) andalso 2015 (not(top = (BitsN.B(0x1FFFFFFFF,33)))) 2016 end; 2017 2018fun ExceptionCode ExceptionType = 2019 let 2020 val x0 = #Cause((!CP0) : CP0) 2021 in 2022 CP0 := 2023 (CP0_Cause_rupd 2024 ((!CP0), 2025 CauseRegister_ExcCode_rupd 2026 (x0, 2027 case ExceptionType of 2028 Int => BitsN.B(0x0,5) 2029 | Mod => BitsN.B(0x1,5) 2030 | TLBL => BitsN.B(0x2,5) 2031 | TLBS => BitsN.B(0x3,5) 2032 | AdEL => BitsN.B(0x4,5) 2033 | AdES => BitsN.B(0x5,5) 2034 | Sys => BitsN.B(0x8,5) 2035 | Bp => BitsN.B(0x9,5) 2036 | ResI => BitsN.B(0xA,5) 2037 | CpU => BitsN.B(0xB,5) 2038 | Ov => BitsN.B(0xC,5) 2039 | Tr => BitsN.B(0xD,5) 2040 | XTLBRefillL => BitsN.B(0x2,5) 2041 | XTLBRefillS => BitsN.B(0x3,5)))) 2042 end; 2043 2044fun SignalException ExceptionType = 2045 ( if not(#EXL((#Status((!CP0) : CP0)) : StatusRegister)) 2046 then case (!BranchDelay) of 2047 Option.SOME(Option.SOME _) => 2048 ( CP0 := 2049 (CP0_EPC_rupd((!CP0),BitsN.-((!PC),BitsN.B(0x4,64)))) 2050 ; let 2051 val x0 = #Cause((!CP0) : CP0) 2052 in 2053 CP0 := 2054 (CP0_Cause_rupd((!CP0),CauseRegister_BD_rupd(x0,true))) 2055 end 2056 ) 2057 | _ => 2058 ( CP0 := (CP0_EPC_rupd((!CP0),(!PC))) 2059 ; let 2060 val x0 = #Cause((!CP0) : CP0) 2061 in 2062 CP0 := 2063 (CP0_Cause_rupd((!CP0),CauseRegister_BD_rupd(x0,false))) 2064 end 2065 ) 2066 else () 2067 ; let 2068 val vectorOffset = 2069 if ((ExceptionType = XTLBRefillL) orelse 2070 (ExceptionType = XTLBRefillS)) andalso 2071 (not(#EXL((#Status((!CP0) : CP0)) : StatusRegister))) 2072 then BitsN.B(0x80,30) 2073 else BitsN.B(0x180,30) 2074 in 2075 ( ExceptionCode ExceptionType 2076 ; let 2077 val x0 = #Status((!CP0) : CP0) 2078 in 2079 CP0 := 2080 (CP0_Status_rupd((!CP0),StatusRegister_EXL_rupd(x0,true))) 2081 end 2082 ; let 2083 val vectorBase = 2084 if #BEV((#Status((!CP0) : CP0)) : StatusRegister) 2085 then BitsN.B(0xFFFFFFFFBFC00200,64) 2086 else BitsN.B(0xFFFFFFFF80000000,64) 2087 in 2088 ( BranchDelay := NONE 2089 ; PC := 2090 (BitsN.- 2091 (BitsN.@@ 2092 (BitsN.bits(63,30) vectorBase, 2093 BitsN.+(BitsN.bits(29,0) vectorBase,vectorOffset)), 2094 BitsN.B(0x4,64))) 2095 ; exceptionSignalled := true 2096 ) 2097 end 2098 ) 2099 end 2100 ); 2101 2102fun SignalCP1UnusableException () = 2103 ( let 2104 val x0 = #Cause((!CP0) : CP0) 2105 in 2106 CP0 := 2107 (CP0_Cause_rupd((!CP0),CauseRegister_CE_rupd(x0,BitsN.B(0x1,2)))) 2108 end 2109 ; SignalException CpU 2110 ); 2111 2112fun UserMode () = 2113 ((#KSU((#Status((!CP0) : CP0)) : StatusRegister)) = (BitsN.B(0x2,2))) andalso 2114 (not((#EXL((#Status((!CP0) : CP0)) : StatusRegister)) orelse 2115 (#ERL((#Status((!CP0) : CP0)) : StatusRegister)))); 2116 2117fun SupervisorMode () = 2118 ((#KSU((#Status((!CP0) : CP0)) : StatusRegister)) = (BitsN.B(0x1,2))) andalso 2119 (not((#EXL((#Status((!CP0) : CP0)) : StatusRegister)) orelse 2120 (#ERL((#Status((!CP0) : CP0)) : StatusRegister)))); 2121 2122fun KernelMode () = 2123 ((#KSU((#Status((!CP0) : CP0)) : StatusRegister)) = (BitsN.B(0x0,2))) orelse 2124 ((#EXL((#Status((!CP0) : CP0)) : StatusRegister)) orelse 2125 (#ERL((#Status((!CP0) : CP0)) : StatusRegister))); 2126 2127fun GPR n = 2128 if n = (BitsN.B(0x0,5)) 2129 then BitsN.B(0x0,64) 2130 else Map.lookup((!gpr),BitsN.toNat n); 2131 2132fun write'GPR (value,n) = 2133 if not(n = (BitsN.B(0x0,5))) 2134 then gpr := (Map.update((!gpr),BitsN.toNat n,value)) 2135 else (); 2136 2137fun HI () = 2138 case (!hi) of Option.SOME v => v | NONE => raise UNPREDICTABLE "HI"; 2139 2140fun write'HI value = hi := (Option.SOME value); 2141 2142fun LO () = 2143 case (!lo) of Option.SOME v => v | NONE => raise UNPREDICTABLE "LO"; 2144 2145fun write'LO value = lo := (Option.SOME value); 2146 2147fun CPR (n,(reg,sel)) = 2148 case (n,(reg,sel)) of 2149 (0,(BitsN.B(0x8,_),BitsN.B(0x0,_))) => #BadVAddr((!CP0) : CP0) 2150 | (0,(BitsN.B(0x9,_),BitsN.B(0x0,_))) => 2151 BitsN.fromNat(BitsN.toNat(#Count((!CP0) : CP0)),64) 2152 | (0,(BitsN.B(0xB,_),BitsN.B(0x0,_))) => 2153 BitsN.fromNat(BitsN.toNat(#Compare((!CP0) : CP0)),64) 2154 | (0,(BitsN.B(0xC,_),BitsN.B(0x0,_))) => 2155 BitsN.fromNat 2156 (BitsN.toNat(reg'StatusRegister(#Status((!CP0) : CP0))),64) 2157 | (0,(BitsN.B(0xD,_),BitsN.B(0x0,_))) => 2158 BitsN.fromNat 2159 (BitsN.toNat(reg'CauseRegister(#Cause((!CP0) : CP0))),64) 2160 | (0,(BitsN.B(0xE,_),BitsN.B(0x0,_))) => #EPC((!CP0) : CP0) 2161 | (0,(BitsN.B(0xF,_),BitsN.B(0x0,_))) => 2162 BitsN.fromNat(BitsN.toNat(#PRId((!CP0) : CP0)),64) 2163 | (0,(BitsN.B(0x10,_),BitsN.B(0x0,_))) => 2164 BitsN.fromNat 2165 (BitsN.toNat(reg'ConfigRegister(#Config((!CP0) : CP0))),64) 2166 | (0,(BitsN.B(0x11,_),BitsN.B(0x0,_))) => #LLAddr((!CP0) : CP0) 2167 | (0,(BitsN.B(0x17,_),BitsN.B(0x0,_))) => 2168 BitsN.fromNat(BitsN.toNat(#Debug((!CP0) : CP0)),64) 2169 | (0,(BitsN.B(0x1A,_),BitsN.B(0x0,_))) => 2170 BitsN.fromNat(BitsN.toNat(#ErrCtl((!CP0) : CP0)),64) 2171 | (0,(BitsN.B(0x1E,_),BitsN.B(0x0,_))) => #ErrorEPC((!CP0) : CP0) 2172 | _ => BitsN.B(0x0,64); 2173 2174fun write'CPR (value,(n,(reg,sel))) = 2175 case (n,(reg,sel)) of 2176 (0,(BitsN.B(0x9,_),BitsN.B(0x0,_))) => 2177 CP0 := (CP0_Count_rupd((!CP0),BitsN.bits(31,0) value)) 2178 | (0,(BitsN.B(0xB,_),BitsN.B(0x0,_))) => 2179 CP0 := (CP0_Compare_rupd((!CP0),BitsN.bits(31,0) value)) 2180 | (0,(BitsN.B(0xC,_),BitsN.B(0x0,_))) => 2181 let 2182 val x0 = #Status((!CP0) : CP0) 2183 in 2184 CP0 := 2185 (CP0_Status_rupd 2186 ((!CP0),write'reg'StatusRegister(x0,BitsN.bits(31,0) value))) 2187 end 2188 | (0,(BitsN.B(0xD,_),BitsN.B(0x0,_))) => 2189 let 2190 val x0 = #Cause((!CP0) : CP0) 2191 in 2192 CP0 := 2193 (CP0_Cause_rupd 2194 ((!CP0),write'reg'CauseRegister(x0,BitsN.bits(31,0) value))) 2195 end 2196 | (0,(BitsN.B(0xE,_),BitsN.B(0x0,_))) => 2197 CP0 := (CP0_EPC_rupd((!CP0),value)) 2198 | (0,(BitsN.B(0x10,_),BitsN.B(0x0,_))) => 2199 let 2200 val x0 = #Config((!CP0) : CP0) 2201 in 2202 CP0 := 2203 (CP0_Config_rupd 2204 ((!CP0),write'reg'ConfigRegister(x0,BitsN.bits(31,0) value))) 2205 end 2206 | (0,(BitsN.B(0x17,_),BitsN.B(0x0,_))) => 2207 CP0 := (CP0_Debug_rupd((!CP0),BitsN.bits(31,0) value)) 2208 | (0,(BitsN.B(0x1A,_),BitsN.B(0x0,_))) => 2209 CP0 := (CP0_ErrCtl_rupd((!CP0),BitsN.bits(31,0) value)) 2210 | (0,(BitsN.B(0x1E,_),BitsN.B(0x0,_))) => 2211 CP0 := (CP0_ErrorEPC_rupd((!CP0),value)) 2212 | _ => (); 2213 2214val BYTE = BitsN.B(0x0,3) 2215 2216val HALFWORD = BitsN.B(0x1,3) 2217 2218val WORD = BitsN.B(0x3,3) 2219 2220val DOUBLEWORD = BitsN.B(0x7,3) 2221 2222fun BigEndianMem () = #BE((#Config((!CP0) : CP0)) : ConfigRegister); 2223 2224fun ReverseEndian () = 2225 BitsN.fromBit 2226 ((#RE((#Status((!CP0) : CP0)) : StatusRegister)) andalso (UserMode ())); 2227 2228fun BigEndianCPU () = 2229 BitsN.??(BitsN.fromBit(BigEndianMem ()),ReverseEndian ()); 2230 2231fun AddressTranslation (vAddr,LorS) = (vAddr,BitsN.B(0x2,3)); 2232 2233fun Aligned (vAddr,MemType) = 2234 (BitsN.&&(BitsN.fromNat(BitsN.toNat vAddr,3),MemType)) = 2235 (BitsN.B(0x0,3)); 2236 2237fun AdjustEndian (MemType,pAddr) = 2238 case MemType of 2239 BitsN.B(0x0,_) => 2240 BitsN.?? 2241 (pAddr, 2242 BitsN.fromNat 2243 (BitsN.toNat(BitsN.resize_replicate 3 (ReverseEndian (),3)),64)) 2244 | BitsN.B(0x1,_) => 2245 BitsN.?? 2246 (pAddr, 2247 BitsN.fromNat 2248 (BitsN.toNat 2249 (BitsN.@@ 2250 (BitsN.resize_replicate 2 (ReverseEndian (),2), 2251 BitsN.B(0x0,1))),64)) 2252 | BitsN.B(0x3,_) => 2253 BitsN.?? 2254 (pAddr, 2255 BitsN.fromNat 2256 (BitsN.toNat(BitsN.@@(ReverseEndian (),BitsN.B(0x0,2))),64)) 2257 | BitsN.B(0x7,_) => pAddr 2258 | _ => raise UNPREDICTABLE "bad access length"; 2259 2260fun ReadData a = 2261 let 2262 val a = BitsN.&&(a,BitsN.~(BitsN.B(0x7,64))) 2263 in 2264 if BigEndianMem () 2265 then BitsN.concat 2266 [Map.lookup((!MEM),BitsN.toNat a), 2267 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x1,64)))), 2268 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x2,64)))), 2269 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x3,64)))), 2270 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x4,64)))), 2271 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x5,64)))), 2272 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x6,64)))), 2273 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x7,64))))] 2274 else BitsN.concat 2275 [Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x7,64)))), 2276 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x6,64)))), 2277 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x5,64)))), 2278 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x4,64)))), 2279 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x3,64)))), 2280 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x2,64)))), 2281 Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x1,64)))), 2282 Map.lookup((!MEM),BitsN.toNat a)] 2283 end; 2284 2285fun LoadMemory (MemType,(AccessLength,(needAlign,(vAddr,link)))) = 2286 if needAlign andalso (not(Aligned(vAddr,MemType))) 2287 then ( CP0 := (CP0_BadVAddr_rupd((!CP0),vAddr)) 2288 ; SignalException AdEL 2289 ; BitsN.B(0x0,64) 2290 ) 2291 else let 2292 val (pAddr,_) = AddressTranslation(vAddr,LOAD) 2293 in 2294 if (!exceptionSignalled) 2295 then BitsN.B(0x0,64) 2296 else let 2297 val pAddr = AdjustEndian(MemType,pAddr) 2298 in 2299 ( case link of 2300 Option.SOME true => 2301 ( LLbit := (Option.SOME true) 2302 ; CP0 := (CP0_LLAddr_rupd((!CP0),pAddr)) 2303 ) 2304 | Option.SOME false => LLbit := NONE 2305 | NONE => () 2306 ; ReadData pAddr 2307 ) 2308 end 2309 end; 2310 2311fun loadByte (base,(rt,(offset,unsigned))) = 2312 let 2313 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 2314 val memdoubleword = 2315 LoadMemory(BYTE,(BYTE,(false,(vAddr,Option.SOME false)))) 2316 in 2317 if not (!exceptionSignalled) 2318 then let 2319 val byte = 2320 BitsN.?? 2321 (BitsN.bits(2,0) vAddr, 2322 BitsN.resize_replicate 3 (BigEndianCPU (),3)) 2323 val membyte = 2324 BitsN.bits 2325 (Nat.+(7,Nat.*(8,BitsN.toNat byte)), 2326 Nat.*(8,BitsN.toNat byte)) 2327 memdoubleword 2328 in 2329 write'GPR 2330 (if unsigned 2331 then BitsN.zeroExtend 64 membyte 2332 else BitsN.signExtend 64 membyte,rt) 2333 end 2334 else () 2335 end; 2336 2337fun loadHalf (base,(rt,(offset,unsigned))) = 2338 let 2339 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 2340 val memdoubleword = 2341 LoadMemory(HALFWORD,(HALFWORD,(true,(vAddr,Option.SOME false)))) 2342 in 2343 if not (!exceptionSignalled) 2344 then let 2345 val byte = 2346 BitsN.?? 2347 (BitsN.bits(2,0) vAddr, 2348 BitsN.@@ 2349 (BitsN.resize_replicate 2 (BigEndianCPU (),2), 2350 BitsN.B(0x0,1))) 2351 val memhalf = 2352 BitsN.bits 2353 (Nat.+(15,Nat.*(8,BitsN.toNat byte)), 2354 Nat.*(8,BitsN.toNat byte)) 2355 memdoubleword 2356 in 2357 write'GPR 2358 (if unsigned 2359 then BitsN.zeroExtend 64 memhalf 2360 else BitsN.signExtend 64 memhalf,rt) 2361 end 2362 else () 2363 end; 2364 2365fun loadWord (link,(base,(rt,(offset,unsigned)))) = 2366 let 2367 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 2368 val memdoubleword = 2369 LoadMemory(WORD,(WORD,(true,(vAddr,Option.SOME link)))) 2370 in 2371 if not (!exceptionSignalled) 2372 then let 2373 val byte = 2374 BitsN.?? 2375 (BitsN.bits(2,0) vAddr, 2376 BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) 2377 val memword = 2378 BitsN.bits 2379 (Nat.+(31,Nat.*(8,BitsN.toNat byte)), 2380 Nat.*(8,BitsN.toNat byte)) 2381 memdoubleword 2382 in 2383 write'GPR 2384 (if unsigned 2385 then BitsN.zeroExtend 64 memword 2386 else BitsN.signExtend 64 memword,rt) 2387 end 2388 else () 2389 end; 2390 2391fun loadDoubleword (link,(base,(rt,offset))) = 2392 let 2393 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 2394 val memdoubleword = 2395 LoadMemory(DOUBLEWORD,(DOUBLEWORD,(true,(vAddr,Option.SOME link)))) 2396 in 2397 if not (!exceptionSignalled) then write'GPR(memdoubleword,rt) else () 2398 end; 2399 2400fun Fetch () = 2401 let 2402 val vAddr = (!PC) 2403 val memdoubleword = LoadMemory(WORD,(WORD,(true,(vAddr,NONE)))) 2404 in 2405 if (!exceptionSignalled) 2406 then NONE 2407 else let 2408 val bytesel = 2409 BitsN.?? 2410 (BitsN.bits(2,0) vAddr, 2411 BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) 2412 val memword = 2413 BitsN.bits 2414 (Nat.+(31,Nat.*(8,BitsN.toNat bytesel)), 2415 Nat.*(8,BitsN.toNat bytesel)) 2416 memdoubleword 2417 in 2418 Option.SOME memword 2419 end 2420 end; 2421 2422fun WriteData (a,(MemElem,(l,h))) = 2423 let 2424 val a = BitsN.&&(a,BitsN.~(BitsN.B(0x7,64))) 2425 in 2426 if BigEndianMem () 2427 then ( if (Nat.<=(l,7)) andalso (Nat.<=(7,h)) 2428 then MEM := 2429 (Map.update 2430 ((!MEM),BitsN.toNat a,BitsN.bits(63,56) MemElem)) 2431 else () 2432 ; if (Nat.<=(l,6)) andalso (Nat.<=(6,h)) 2433 then let 2434 val x = BitsN.+(a,BitsN.B(0x1,64)) 2435 in 2436 MEM := 2437 (Map.update 2438 ((!MEM),BitsN.toNat x,BitsN.bits(55,48) MemElem)) 2439 end 2440 else () 2441 ; if (Nat.<=(l,5)) andalso (Nat.<=(5,h)) 2442 then let 2443 val x = BitsN.+(a,BitsN.B(0x2,64)) 2444 in 2445 MEM := 2446 (Map.update 2447 ((!MEM),BitsN.toNat x,BitsN.bits(47,40) MemElem)) 2448 end 2449 else () 2450 ; if (Nat.<=(l,4)) andalso (Nat.<=(4,h)) 2451 then let 2452 val x = BitsN.+(a,BitsN.B(0x3,64)) 2453 in 2454 MEM := 2455 (Map.update 2456 ((!MEM),BitsN.toNat x,BitsN.bits(39,32) MemElem)) 2457 end 2458 else () 2459 ; if (Nat.<=(l,3)) andalso (Nat.<=(3,h)) 2460 then let 2461 val x = BitsN.+(a,BitsN.B(0x4,64)) 2462 in 2463 MEM := 2464 (Map.update 2465 ((!MEM),BitsN.toNat x,BitsN.bits(31,24) MemElem)) 2466 end 2467 else () 2468 ; if (Nat.<=(l,2)) andalso (Nat.<=(2,h)) 2469 then let 2470 val x = BitsN.+(a,BitsN.B(0x5,64)) 2471 in 2472 MEM := 2473 (Map.update 2474 ((!MEM),BitsN.toNat x,BitsN.bits(23,16) MemElem)) 2475 end 2476 else () 2477 ; if (Nat.<=(l,1)) andalso (Nat.<=(1,h)) 2478 then let 2479 val x = BitsN.+(a,BitsN.B(0x6,64)) 2480 in 2481 MEM := 2482 (Map.update 2483 ((!MEM),BitsN.toNat x,BitsN.bits(15,8) MemElem)) 2484 end 2485 else () 2486 ; if l = 0 2487 then let 2488 val x = BitsN.+(a,BitsN.B(0x7,64)) 2489 in 2490 MEM := 2491 (Map.update 2492 ((!MEM),BitsN.toNat x,BitsN.bits(7,0) MemElem)) 2493 end 2494 else () 2495 ) 2496 else ( if (Nat.<=(l,7)) andalso (Nat.<=(7,h)) 2497 then MEM := 2498 (Map.update 2499 ((!MEM),BitsN.toNat a,BitsN.bits(7,0) MemElem)) 2500 else () 2501 ; if (Nat.<=(l,6)) andalso (Nat.<=(6,h)) 2502 then let 2503 val x = BitsN.+(a,BitsN.B(0x1,64)) 2504 in 2505 MEM := 2506 (Map.update 2507 ((!MEM),BitsN.toNat x,BitsN.bits(15,8) MemElem)) 2508 end 2509 else () 2510 ; if (Nat.<=(l,5)) andalso (Nat.<=(5,h)) 2511 then let 2512 val x = BitsN.+(a,BitsN.B(0x2,64)) 2513 in 2514 MEM := 2515 (Map.update 2516 ((!MEM),BitsN.toNat x,BitsN.bits(23,16) MemElem)) 2517 end 2518 else () 2519 ; if (Nat.<=(l,4)) andalso (Nat.<=(4,h)) 2520 then let 2521 val x = BitsN.+(a,BitsN.B(0x3,64)) 2522 in 2523 MEM := 2524 (Map.update 2525 ((!MEM),BitsN.toNat x,BitsN.bits(31,24) MemElem)) 2526 end 2527 else () 2528 ; if (Nat.<=(l,3)) andalso (Nat.<=(3,h)) 2529 then let 2530 val x = BitsN.+(a,BitsN.B(0x4,64)) 2531 in 2532 MEM := 2533 (Map.update 2534 ((!MEM),BitsN.toNat x,BitsN.bits(39,32) MemElem)) 2535 end 2536 else () 2537 ; if (Nat.<=(l,2)) andalso (Nat.<=(2,h)) 2538 then let 2539 val x = BitsN.+(a,BitsN.B(0x5,64)) 2540 in 2541 MEM := 2542 (Map.update 2543 ((!MEM),BitsN.toNat x,BitsN.bits(47,40) MemElem)) 2544 end 2545 else () 2546 ; if (Nat.<=(l,1)) andalso (Nat.<=(1,h)) 2547 then let 2548 val x = BitsN.+(a,BitsN.B(0x6,64)) 2549 in 2550 MEM := 2551 (Map.update 2552 ((!MEM),BitsN.toNat x,BitsN.bits(55,48) MemElem)) 2553 end 2554 else () 2555 ; if l = 0 2556 then let 2557 val x = BitsN.+(a,BitsN.B(0x7,64)) 2558 in 2559 MEM := 2560 (Map.update 2561 ((!MEM),BitsN.toNat x,BitsN.bits(63,56) MemElem)) 2562 end 2563 else () 2564 ) 2565 end; 2566 2567fun StoreMemory 2568 (MemType,(AccessLength,(needAlign,(MemElem,(vAddr,cond))))) = 2569 if needAlign andalso (not(Aligned(vAddr,MemType))) 2570 then ( CP0 := (CP0_BadVAddr_rupd((!CP0),vAddr)) 2571 ; SignalException AdES 2572 ; false 2573 ) 2574 else let 2575 val (pAddr,_) = AddressTranslation(vAddr,STORE) 2576 in 2577 if (!exceptionSignalled) 2578 then true 2579 else let 2580 val pAddr = AdjustEndian(MemType,pAddr) 2581 val sc_success = 2582 (not cond) orelse 2583 (case (!LLbit) of 2584 NONE => 2585 raise UNPREDICTABLE 2586 "conditional store: LLbit not set" 2587 | Option.SOME false => false 2588 | Option.SOME true => 2589 ((#LLAddr((!CP0) : CP0)) = pAddr) orelse 2590 (raise UNPREDICTABLE 2591 "conditional store: address doesn't match previous LL address")) 2592 in 2593 ( if sc_success 2594 then let 2595 val b = Nat.+(BitsN.toNat AccessLength,1) 2596 val l = 2597 Nat.- 2598 (8, 2599 Nat.+ 2600 (b,BitsN.toNat(BitsN.bits(2,0) vAddr))) 2601 val h = Nat.-(Nat.+(l,b),1) 2602 in 2603 WriteData(pAddr,(MemElem,(l,h))) 2604 end 2605 else () 2606 ; LLbit := NONE 2607 ; sc_success 2608 ) 2609 end 2610 end; 2611 2612fun storeWord (base,(rt,(offset,cond))) = 2613 let 2614 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 2615 val bytesel = 2616 BitsN.?? 2617 (BitsN.bits(2,0) vAddr,BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) 2618 val datadoubleword = BitsN.<<(GPR rt,Nat.*(8,BitsN.toNat bytesel)) 2619 in 2620 StoreMemory(WORD,(WORD,(true,(datadoubleword,(vAddr,cond))))) 2621 end; 2622 2623fun storeDoubleword (base,(rt,(offset,cond))) = 2624 let 2625 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 2626 val datadoubleword = GPR rt 2627 in 2628 StoreMemory 2629 (DOUBLEWORD,(DOUBLEWORD,(true,(datadoubleword,(vAddr,cond))))) 2630 end; 2631 2632fun rec'FCSR x = 2633 {ABS2008 = BitsN.bit(x,19), CauseE = BitsN.bit(x,17), 2634 CauseI = BitsN.bit(x,12), CauseO = BitsN.bit(x,14), 2635 CauseU = BitsN.bit(x,13), CauseV = BitsN.bit(x,16), 2636 CauseZ = BitsN.bit(x,15), EnableI = BitsN.bit(x,7), 2637 EnableO = BitsN.bit(x,9), EnableU = BitsN.bit(x,8), 2638 EnableV = BitsN.bit(x,11), EnableZ = BitsN.bit(x,10), 2639 FCC = BitsN.@@(BitsN.bits(31,25) x,BitsN.bits(23,23) x), 2640 FS = BitsN.bit(x,24), FlagI = BitsN.bit(x,2), FlagO = BitsN.bit(x,4), 2641 FlagU = BitsN.bit(x,3), FlagV = BitsN.bit(x,6), FlagZ = BitsN.bit(x,5), 2642 NAN2008 = BitsN.bit(x,18), RM = BitsN.bits(1,0) x, 2643 fcsr'rst = BitsN.bits(22,20) x}; 2644 2645fun reg'FCSR x = 2646 case x of 2647 {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, 2648 CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, 2649 EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, 2650 EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, 2651 FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, 2652 FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst} => 2653 BitsN.concat 2654 [BitsN.bits(7,1) FCC,BitsN.fromBit FS,BitsN.bits(0,0) FCC, 2655 fcsr'rst,BitsN.fromBit ABS2008,BitsN.fromBit NAN2008, 2656 BitsN.fromBit CauseE,BitsN.fromBit CauseV,BitsN.fromBit CauseZ, 2657 BitsN.fromBit CauseO,BitsN.fromBit CauseU,BitsN.fromBit CauseI, 2658 BitsN.fromBit EnableV,BitsN.fromBit EnableZ, 2659 BitsN.fromBit EnableO,BitsN.fromBit EnableU, 2660 BitsN.fromBit EnableI,BitsN.fromBit FlagV,BitsN.fromBit FlagZ, 2661 BitsN.fromBit FlagO,BitsN.fromBit FlagU,BitsN.fromBit FlagI,RM]; 2662 2663fun write'rec'FCSR (_,x) = reg'FCSR x; 2664 2665fun write'reg'FCSR (_,x) = rec'FCSR x; 2666 2667fun rec'FIR x = 2668 {ASE = BitsN.bit(x,19), D = BitsN.bit(x,17), F64 = BitsN.bit(x,22), 2669 L = BitsN.bit(x,21), PS = BitsN.bit(x,18), PrID = BitsN.bits(15,8) x, 2670 Rev = BitsN.bits(7,0) x, S = BitsN.bit(x,16), W = BitsN.bit(x,20), 2671 fir'rst = BitsN.bits(31,23) x}; 2672 2673fun reg'FIR x = 2674 case x of 2675 {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, 2676 S = S, W = W, fir'rst = fir'rst} => 2677 BitsN.concat 2678 [fir'rst,BitsN.fromBit F64,BitsN.fromBit L,BitsN.fromBit W, 2679 BitsN.fromBit ASE,BitsN.fromBit PS,BitsN.fromBit D, 2680 BitsN.fromBit S,PrID,Rev]; 2681 2682fun write'rec'FIR (_,x) = reg'FIR x; 2683 2684fun write'reg'FIR (_,x) = rec'FIR x; 2685 2686fun IntToWordMIPS v = 2687 if IntInf.>(v,2147483647) 2688 then BitsN.B(0x7FFFFFFF,32) 2689 else if IntInf.<(v,IntInf.~ 2147483648) 2690 then BitsN.B(0x7FFFFFFF,32) 2691 else BitsN.fromInt(v,32); 2692 2693fun IntToDWordMIPS v = 2694 if IntInf.>(v,9223372036854775807) 2695 then BitsN.B(0x7FFFFFFFFFFFFFFF,64) 2696 else if IntInf.<(v,IntInf.~ 9223372036854775808) 2697 then BitsN.B(0x7FFFFFFFFFFFFFFF,64) 2698 else BitsN.fromInt(v,64); 2699 2700fun PostOpF32 v = 2701 if (#FS((!fcsr) : FCSR)) andalso (FP32.isSubnormal v) 2702 then BitsN.B(0x0,32) 2703 else v; 2704 2705fun PostOpF64 v = 2706 if (#FS((!fcsr) : FCSR)) andalso (FP64.isSubnormal v) 2707 then BitsN.B(0x0,64) 2708 else v; 2709 2710fun FP32_Abs1985 a = if FP32.isNan a then a else FP32.abs a; 2711 2712fun FP32_Neg1985 a = if FP32.isNan a then a else FP32.neg a; 2713 2714fun FP64_Abs1985 a = if FP64.isNan a then a else FP64.abs a; 2715 2716fun FP64_Neg1985 a = if FP64.isNan a then a else FP64.neg a; 2717 2718fun FP64_Unordered (a,b) = (FP64.isNan a) orelse (FP64.isNan b); 2719 2720fun FP32_Unordered (a,b) = (FP32.isNan a) orelse (FP32.isNan b); 2721 2722fun Rounding_Mode () = 2723 case #RM((!fcsr) : FCSR) of 2724 BitsN.B(0x0,_) => IEEEReal.TO_NEAREST 2725 | BitsN.B(0x1,_) => IEEEReal.TO_ZERO 2726 | BitsN.B(0x2,_) => IEEEReal.TO_POSINF 2727 | BitsN.B(0x3,_) => IEEEReal.TO_NEGINF 2728 | _ => raise General.Bind; 2729 2730fun dfn'ABS_D (fd,fs) = 2731 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2732 then SignalCP1UnusableException () 2733 else if #ABS2008((!fcsr) : FCSR) 2734 then FGR := 2735 (Map.update 2736 ((!FGR),BitsN.toNat fd, 2737 FP64.abs(Map.lookup((!FGR),BitsN.toNat fs)))) 2738 else FGR := 2739 (Map.update 2740 ((!FGR),BitsN.toNat fd, 2741 PostOpF64(FP64_Abs1985(Map.lookup((!FGR),BitsN.toNat fs))))); 2742 2743fun dfn'ABS_S (fd,fs) = 2744 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2745 then SignalCP1UnusableException () 2746 else if #ABS2008((!fcsr) : FCSR) 2747 then FGR := 2748 (Map.update 2749 ((!FGR),BitsN.toNat fd, 2750 BitsN.signExtend 64 2751 (FP32.abs 2752 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)))))) 2753 else FGR := 2754 (Map.update 2755 ((!FGR),BitsN.toNat fd, 2756 BitsN.signExtend 64 2757 (PostOpF32 2758 (FP32_Abs1985 2759 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))))); 2760 2761fun dfn'ADD_D (fd,(fs,ft)) = 2762 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2763 then SignalCP1UnusableException () 2764 else FGR := 2765 (Map.update 2766 ((!FGR),BitsN.toNat fd, 2767 PostOpF64 2768 ((L3.snd o FP64.add) 2769 (Rounding_Mode (), 2770 (Map.lookup((!FGR),BitsN.toNat fs), 2771 Map.lookup((!FGR),BitsN.toNat ft)))))); 2772 2773fun dfn'ADD_S (fd,(fs,ft)) = 2774 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2775 then SignalCP1UnusableException () 2776 else FGR := 2777 (Map.update 2778 ((!FGR),BitsN.toNat fd, 2779 BitsN.signExtend 64 2780 (PostOpF32 2781 ((L3.snd o FP32.add) 2782 (Rounding_Mode (), 2783 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), 2784 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))))))); 2785 2786fun dfn'BC1F (i,cc) = 2787 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2788 then SignalCP1UnusableException () 2789 else ConditionalBranch 2790 (not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)),i); 2791 2792fun dfn'BC1FL (i,cc) = 2793 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2794 then SignalCP1UnusableException () 2795 else ConditionalBranchLikely 2796 (not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)),i); 2797 2798fun dfn'BC1T (i,cc) = 2799 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2800 then SignalCP1UnusableException () 2801 else ConditionalBranch(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc),i); 2802 2803fun dfn'BC1TL (i,cc) = 2804 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2805 then SignalCP1UnusableException () 2806 else ConditionalBranchLikely 2807 (BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc),i); 2808 2809fun dfn'C_cond_D (fs,(ft,(cnd,cc))) = 2810 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2811 then SignalCP1UnusableException () 2812 else let 2813 val i = BitsN.toNat cc 2814 val w = #FCC((!fcsr) : FCSR) 2815 in 2816 fcsr := 2817 (FCSR_FCC_rupd 2818 ((!fcsr), 2819 BitsN.bitFieldInsert(i,i) 2820 (w, 2821 BitsN.fromBit 2822 (case cnd of 2823 BitsN.B(0x0,_) => false 2824 | BitsN.B(0x1,_) => 2825 FP64_Unordered 2826 (Map.lookup((!FGR),BitsN.toNat fs), 2827 Map.lookup((!FGR),BitsN.toNat ft)) 2828 | BitsN.B(0x2,_) => 2829 FP64.equal 2830 (Map.lookup((!FGR),BitsN.toNat fs), 2831 Map.lookup((!FGR),BitsN.toNat ft)) 2832 | BitsN.B(0x3,_) => 2833 (FP64.equal 2834 (Map.lookup((!FGR),BitsN.toNat fs), 2835 Map.lookup((!FGR),BitsN.toNat ft))) orelse 2836 (FP64_Unordered 2837 (Map.lookup((!FGR),BitsN.toNat fs), 2838 Map.lookup((!FGR),BitsN.toNat ft))) 2839 | BitsN.B(0x4,_) => 2840 FP64.lessThan 2841 (Map.lookup((!FGR),BitsN.toNat fs), 2842 Map.lookup((!FGR),BitsN.toNat ft)) 2843 | BitsN.B(0x5,_) => 2844 not(FP64.greaterEqual 2845 (Map.lookup((!FGR),BitsN.toNat fs), 2846 Map.lookup((!FGR),BitsN.toNat ft))) 2847 | BitsN.B(0x6,_) => 2848 FP64.lessEqual 2849 (Map.lookup((!FGR),BitsN.toNat fs), 2850 Map.lookup((!FGR),BitsN.toNat ft)) 2851 | BitsN.B(0x7,_) => 2852 not(FP64.greaterThan 2853 (Map.lookup((!FGR),BitsN.toNat fs), 2854 Map.lookup((!FGR),BitsN.toNat ft))) 2855 | _ => raise General.Bind)))) 2856 end; 2857 2858fun dfn'C_cond_S (fs,(ft,(cnd,cc))) = 2859 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2860 then SignalCP1UnusableException () 2861 else let 2862 val i = BitsN.toNat cc 2863 val w = #FCC((!fcsr) : FCSR) 2864 in 2865 fcsr := 2866 (FCSR_FCC_rupd 2867 ((!fcsr), 2868 BitsN.bitFieldInsert(i,i) 2869 (w, 2870 BitsN.fromBit 2871 (case cnd of 2872 BitsN.B(0x0,_) => false 2873 | BitsN.B(0x1,_) => 2874 FP32_Unordered 2875 (BitsN.bits(31,0) 2876 (Map.lookup((!FGR),BitsN.toNat fs)), 2877 BitsN.bits(31,0) 2878 (Map.lookup((!FGR),BitsN.toNat ft))) 2879 | BitsN.B(0x2,_) => 2880 FP32.equal 2881 (BitsN.bits(31,0) 2882 (Map.lookup((!FGR),BitsN.toNat fs)), 2883 BitsN.bits(31,0) 2884 (Map.lookup((!FGR),BitsN.toNat ft))) 2885 | BitsN.B(0x3,_) => 2886 (FP32.equal 2887 (BitsN.bits(31,0) 2888 (Map.lookup((!FGR),BitsN.toNat fs)), 2889 BitsN.bits(31,0) 2890 (Map.lookup((!FGR),BitsN.toNat ft)))) orelse 2891 (FP32_Unordered 2892 (BitsN.bits(31,0) 2893 (Map.lookup((!FGR),BitsN.toNat fs)), 2894 BitsN.bits(31,0) 2895 (Map.lookup((!FGR),BitsN.toNat ft)))) 2896 | BitsN.B(0x4,_) => 2897 FP32.lessThan 2898 (BitsN.bits(31,0) 2899 (Map.lookup((!FGR),BitsN.toNat fs)), 2900 BitsN.bits(31,0) 2901 (Map.lookup((!FGR),BitsN.toNat ft))) 2902 | BitsN.B(0x5,_) => 2903 not(FP32.greaterEqual 2904 (BitsN.bits(31,0) 2905 (Map.lookup((!FGR),BitsN.toNat fs)), 2906 BitsN.bits(31,0) 2907 (Map.lookup((!FGR),BitsN.toNat ft)))) 2908 | BitsN.B(0x6,_) => 2909 FP32.lessEqual 2910 (BitsN.bits(31,0) 2911 (Map.lookup((!FGR),BitsN.toNat fs)), 2912 BitsN.bits(31,0) 2913 (Map.lookup((!FGR),BitsN.toNat ft))) 2914 | BitsN.B(0x7,_) => 2915 not(FP32.greaterThan 2916 (BitsN.bits(31,0) 2917 (Map.lookup((!FGR),BitsN.toNat fs)), 2918 BitsN.bits(31,0) 2919 (Map.lookup((!FGR),BitsN.toNat ft)))) 2920 | _ => raise General.Bind)))) 2921 end; 2922 2923fun dfn'CEIL_L_D (fd,fs) = 2924 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2925 then SignalCP1UnusableException () 2926 else FGR := 2927 (Map.update 2928 ((!FGR),BitsN.toNat fd, 2929 case FP64.toInt 2930 (IEEEReal.TO_POSINF,Map.lookup((!FGR),BitsN.toNat fs)) of 2931 Option.SOME x => IntToDWordMIPS x 2932 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 2933 2934fun dfn'CEIL_L_S (fd,fs) = 2935 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2936 then SignalCP1UnusableException () 2937 else FGR := 2938 (Map.update 2939 ((!FGR),BitsN.toNat fd, 2940 case FP32.toInt 2941 (IEEEReal.TO_POSINF, 2942 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 2943 Option.SOME x => IntToDWordMIPS x 2944 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 2945 2946fun dfn'CEIL_W_D (fd,fs) = 2947 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2948 then SignalCP1UnusableException () 2949 else FGR := 2950 (Map.update 2951 ((!FGR),BitsN.toNat fd, 2952 case FP64.toInt 2953 (IEEEReal.TO_POSINF,Map.lookup((!FGR),BitsN.toNat fs)) of 2954 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 2955 | NONE => BitsN.B(0x7FFFFFFF,64))); 2956 2957fun dfn'CEIL_W_S (fd,fs) = 2958 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2959 then SignalCP1UnusableException () 2960 else FGR := 2961 (Map.update 2962 ((!FGR),BitsN.toNat fd, 2963 case FP32.toInt 2964 (IEEEReal.TO_POSINF, 2965 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 2966 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 2967 | NONE => BitsN.B(0x7FFFFFFF,64))); 2968 2969fun dfn'CVT_D_L (fd,fs) = 2970 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2971 then SignalCP1UnusableException () 2972 else FGR := 2973 (Map.update 2974 ((!FGR),BitsN.toNat fd, 2975 FP64.fromInt 2976 (Rounding_Mode (), 2977 BitsN.toInt(Map.lookup((!FGR),BitsN.toNat fs))))); 2978 2979fun dfn'CVT_D_S (fd,fs) = 2980 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2981 then SignalCP1UnusableException () 2982 else FGR := 2983 (Map.update 2984 ((!FGR),BitsN.toNat fd, 2985 FPConvert.fp32_to_fp64 2986 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))); 2987 2988fun dfn'CVT_D_W (fd,fs) = 2989 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 2990 then SignalCP1UnusableException () 2991 else ( if NotWordValue(Map.lookup((!FGR),BitsN.toNat fs)) 2992 then raise UNPREDICTABLE "CVT.D.W: NotWordValue" 2993 else () 2994 ; FGR := 2995 (Map.update 2996 ((!FGR),BitsN.toNat fd, 2997 FP64.fromInt 2998 (Rounding_Mode (), 2999 BitsN.toInt 3000 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)))))) 3001 ); 3002 3003fun dfn'CVT_L_D (fd,fs) = 3004 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3005 then SignalCP1UnusableException () 3006 else FGR := 3007 (Map.update 3008 ((!FGR),BitsN.toNat fd, 3009 case FP64.toInt 3010 (Rounding_Mode (),Map.lookup((!FGR),BitsN.toNat fs)) of 3011 Option.SOME x => IntToDWordMIPS x 3012 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 3013 3014fun dfn'CVT_L_S (fd,fs) = 3015 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3016 then SignalCP1UnusableException () 3017 else FGR := 3018 (Map.update 3019 ((!FGR),BitsN.toNat fd, 3020 case FP32.toInt 3021 (Rounding_Mode (), 3022 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 3023 Option.SOME x => IntToDWordMIPS x 3024 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 3025 3026fun dfn'CVT_S_D (fd,fs) = 3027 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3028 then SignalCP1UnusableException () 3029 else FGR := 3030 (Map.update 3031 ((!FGR),BitsN.toNat fd, 3032 BitsN.signExtend 64 3033 (FPConvert.fp64_to_fp32 3034 (Rounding_Mode (),Map.lookup((!FGR),BitsN.toNat fs))))); 3035 3036fun dfn'CVT_S_L (fd,fs) = 3037 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3038 then SignalCP1UnusableException () 3039 else FGR := 3040 (Map.update 3041 ((!FGR),BitsN.toNat fd, 3042 BitsN.signExtend 64 3043 (FP32.fromInt 3044 (Rounding_Mode (), 3045 BitsN.toInt(Map.lookup((!FGR),BitsN.toNat fs)))))); 3046 3047fun dfn'CVT_S_W (fd,fs) = 3048 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3049 then SignalCP1UnusableException () 3050 else ( if NotWordValue(Map.lookup((!FGR),BitsN.toNat fs)) 3051 then raise UNPREDICTABLE "CVT.S.W: NotWordValue" 3052 else () 3053 ; FGR := 3054 (Map.update 3055 ((!FGR),BitsN.toNat fd, 3056 BitsN.signExtend 64 3057 (FP32.fromInt 3058 (Rounding_Mode (), 3059 BitsN.toInt 3060 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))))) 3061 ); 3062 3063fun dfn'CVT_W_D (fd,fs) = 3064 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3065 then SignalCP1UnusableException () 3066 else FGR := 3067 (Map.update 3068 ((!FGR),BitsN.toNat fd, 3069 case FP64.toInt 3070 (Rounding_Mode (),Map.lookup((!FGR),BitsN.toNat fs)) of 3071 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 3072 | NONE => BitsN.B(0x7FFFFFFF,64))); 3073 3074fun dfn'CVT_W_S (fd,fs) = 3075 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3076 then SignalCP1UnusableException () 3077 else FGR := 3078 (Map.update 3079 ((!FGR),BitsN.toNat fd, 3080 case FP32.toInt 3081 (Rounding_Mode (), 3082 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 3083 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 3084 | NONE => BitsN.B(0x7FFFFFFF,64))); 3085 3086fun dfn'DIV_D (fd,(fs,ft)) = 3087 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3088 then SignalCP1UnusableException () 3089 else FGR := 3090 (Map.update 3091 ((!FGR),BitsN.toNat fd, 3092 PostOpF64 3093 ((L3.snd o FP64.div) 3094 (Rounding_Mode (), 3095 (Map.lookup((!FGR),BitsN.toNat fs), 3096 Map.lookup((!FGR),BitsN.toNat ft)))))); 3097 3098fun dfn'DIV_S (fd,(fs,ft)) = 3099 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3100 then SignalCP1UnusableException () 3101 else FGR := 3102 (Map.update 3103 ((!FGR),BitsN.toNat fd, 3104 BitsN.signExtend 64 3105 (PostOpF32 3106 ((L3.snd o FP32.div) 3107 (Rounding_Mode (), 3108 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), 3109 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))))))); 3110 3111fun dfn'FLOOR_L_D (fd,fs) = 3112 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3113 then SignalCP1UnusableException () 3114 else FGR := 3115 (Map.update 3116 ((!FGR),BitsN.toNat fd, 3117 case FP64.toInt 3118 (IEEEReal.TO_NEGINF,Map.lookup((!FGR),BitsN.toNat fs)) of 3119 Option.SOME x => IntToDWordMIPS x 3120 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 3121 3122fun dfn'FLOOR_L_S (fd,fs) = 3123 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3124 then SignalCP1UnusableException () 3125 else FGR := 3126 (Map.update 3127 ((!FGR),BitsN.toNat fd, 3128 case FP32.toInt 3129 (IEEEReal.TO_NEGINF, 3130 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 3131 Option.SOME x => IntToDWordMIPS x 3132 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 3133 3134fun dfn'FLOOR_W_D (fd,fs) = 3135 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3136 then SignalCP1UnusableException () 3137 else FGR := 3138 (Map.update 3139 ((!FGR),BitsN.toNat fd, 3140 case FP64.toInt 3141 (IEEEReal.TO_NEGINF,Map.lookup((!FGR),BitsN.toNat fs)) of 3142 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 3143 | NONE => BitsN.B(0x7FFFFFFF,64))); 3144 3145fun dfn'FLOOR_W_S (fd,fs) = 3146 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3147 then SignalCP1UnusableException () 3148 else FGR := 3149 (Map.update 3150 ((!FGR),BitsN.toNat fd, 3151 case FP32.toInt 3152 (IEEEReal.TO_NEGINF, 3153 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 3154 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 3155 | NONE => BitsN.B(0x7FFFFFFF,64))); 3156 3157fun dfn'LDC1 (ft,(offset,base)) = 3158 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3159 then SignalCP1UnusableException () 3160 else let 3161 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 3162 val memdoubleword = 3163 LoadMemory 3164 (DOUBLEWORD,(DOUBLEWORD,(true,(vAddr,Option.SOME false)))) 3165 in 3166 if not (!exceptionSignalled) 3167 then FGR := (Map.update((!FGR),BitsN.toNat ft,memdoubleword)) 3168 else () 3169 end; 3170 3171fun dfn'LDXC1 (fd,(index,base)) = 3172 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3173 then SignalCP1UnusableException () 3174 else let 3175 val vAddr = BitsN.+(GPR index,GPR base) 3176 val memdoubleword = 3177 LoadMemory 3178 (DOUBLEWORD,(DOUBLEWORD,(true,(vAddr,Option.SOME false)))) 3179 in 3180 if not (!exceptionSignalled) 3181 then FGR := (Map.update((!FGR),BitsN.toNat fd,memdoubleword)) 3182 else () 3183 end; 3184 3185fun dfn'LWC1 (ft,(offset,base)) = 3186 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3187 then SignalCP1UnusableException () 3188 else let 3189 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 3190 val memdoubleword = 3191 LoadMemory(WORD,(WORD,(true,(vAddr,Option.SOME false)))) 3192 in 3193 if not (!exceptionSignalled) 3194 then let 3195 val byte = 3196 BitsN.?? 3197 (BitsN.bits(2,0) vAddr, 3198 BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) 3199 val memword = 3200 BitsN.bits 3201 (Nat.+(31,Nat.*(8,BitsN.toNat byte)), 3202 Nat.*(8,BitsN.toNat byte)) 3203 memdoubleword 3204 in 3205 FGR := 3206 (Map.update 3207 ((!FGR),BitsN.toNat ft,BitsN.signExtend 64 memword)) 3208 end 3209 else () 3210 end; 3211 3212fun dfn'LWXC1 (ft,(index,base)) = 3213 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3214 then SignalCP1UnusableException () 3215 else let 3216 val vAddr = BitsN.+(GPR index,GPR base) 3217 val memdoubleword = 3218 LoadMemory(WORD,(WORD,(true,(vAddr,Option.SOME false)))) 3219 in 3220 if not (!exceptionSignalled) 3221 then let 3222 val byte = 3223 BitsN.?? 3224 (BitsN.bits(2,0) vAddr, 3225 BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) 3226 val memword = 3227 BitsN.bits 3228 (Nat.+(31,Nat.*(8,BitsN.toNat byte)), 3229 Nat.*(8,BitsN.toNat byte)) 3230 memdoubleword 3231 in 3232 FGR := 3233 (Map.update 3234 ((!FGR),BitsN.toNat ft,BitsN.signExtend 64 memword)) 3235 end 3236 else () 3237 end; 3238 3239fun dfn'MADD_D (fd,(fr,(fs,ft))) = 3240 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3241 then SignalCP1UnusableException () 3242 else FGR := 3243 (Map.update 3244 ((!FGR),BitsN.toNat fd, 3245 PostOpF64 3246 ((L3.snd o FP64.add) 3247 (Rounding_Mode (), 3248 (PostOpF64 3249 ((L3.snd o FP64.mul) 3250 (Rounding_Mode (), 3251 (Map.lookup((!FGR),BitsN.toNat fs), 3252 Map.lookup((!FGR),BitsN.toNat ft)))), 3253 Map.lookup((!FGR),BitsN.toNat fr)))))); 3254 3255fun dfn'MADD_S (fd,(fr,(fs,ft))) = 3256 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3257 then SignalCP1UnusableException () 3258 else FGR := 3259 (Map.update 3260 ((!FGR),BitsN.toNat fd, 3261 BitsN.signExtend 64 3262 (PostOpF32 3263 ((L3.snd o FP32.add) 3264 (Rounding_Mode (), 3265 (PostOpF32 3266 ((L3.snd o FP32.mul) 3267 (Rounding_Mode (), 3268 (BitsN.bits(31,0) 3269 (Map.lookup((!FGR),BitsN.toNat fs)), 3270 BitsN.bits(31,0) 3271 (Map.lookup((!FGR),BitsN.toNat ft))))), 3272 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fr)))))))); 3273 3274fun dfn'MOV_D (fd,fs) = 3275 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3276 then SignalCP1UnusableException () 3277 else FGR := 3278 (Map.update 3279 ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))); 3280 3281fun dfn'MOV_S (fd,fs) = 3282 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3283 then SignalCP1UnusableException () 3284 else FGR := 3285 (Map.update 3286 ((!FGR),BitsN.toNat fd, 3287 BitsN.signExtend 64 3288 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))); 3289 3290fun dfn'MOVF (rd,(rs,cc)) = 3291 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3292 then SignalCP1UnusableException () 3293 else if not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)) 3294 then write'GPR(GPR rs,rd) 3295 else (); 3296 3297fun dfn'MOVF_D (fd,(fs,cc)) = 3298 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3299 then SignalCP1UnusableException () 3300 else if not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)) 3301 then FGR := 3302 (Map.update 3303 ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))) 3304 else (); 3305 3306fun dfn'MOVF_S (fd,(fs,cc)) = 3307 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3308 then SignalCP1UnusableException () 3309 else if not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)) 3310 then FGR := 3311 (Map.update 3312 ((!FGR),BitsN.toNat fd, 3313 BitsN.signExtend 64 3314 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))) 3315 else (); 3316 3317fun dfn'MOVN_D (fd,(fs,rt)) = 3318 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3319 then SignalCP1UnusableException () 3320 else if not((GPR rt) = (BitsN.B(0x0,64))) 3321 then FGR := 3322 (Map.update 3323 ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))) 3324 else (); 3325 3326fun dfn'MOVN_S (fd,(fs,rt)) = 3327 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3328 then SignalCP1UnusableException () 3329 else if not((GPR rt) = (BitsN.B(0x0,64))) 3330 then FGR := 3331 (Map.update 3332 ((!FGR),BitsN.toNat fd, 3333 BitsN.signExtend 64 3334 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))) 3335 else (); 3336 3337fun dfn'MOVT (rd,(rs,cc)) = 3338 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3339 then SignalCP1UnusableException () 3340 else if BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc) 3341 then write'GPR(GPR rs,rd) 3342 else (); 3343 3344fun dfn'MOVT_D (fd,(fs,cc)) = 3345 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3346 then SignalCP1UnusableException () 3347 else if BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc) 3348 then FGR := 3349 (Map.update 3350 ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))) 3351 else (); 3352 3353fun dfn'MOVT_S (fd,(fs,cc)) = 3354 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3355 then SignalCP1UnusableException () 3356 else if BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc) 3357 then FGR := 3358 (Map.update 3359 ((!FGR),BitsN.toNat fd, 3360 BitsN.signExtend 64 3361 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))) 3362 else (); 3363 3364fun dfn'MOVZ_D (fd,(fs,rt)) = 3365 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3366 then SignalCP1UnusableException () 3367 else if (GPR rt) = (BitsN.B(0x0,64)) 3368 then FGR := 3369 (Map.update 3370 ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))) 3371 else (); 3372 3373fun dfn'MOVZ_S (fd,(fs,rt)) = 3374 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3375 then SignalCP1UnusableException () 3376 else if (GPR rt) = (BitsN.B(0x0,64)) 3377 then FGR := 3378 (Map.update 3379 ((!FGR),BitsN.toNat fd, 3380 BitsN.signExtend 64 3381 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))) 3382 else (); 3383 3384fun dfn'MSUB_D (fd,(fr,(fs,ft))) = 3385 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3386 then SignalCP1UnusableException () 3387 else FGR := 3388 (Map.update 3389 ((!FGR),BitsN.toNat fd, 3390 PostOpF64 3391 ((L3.snd o FP64.sub) 3392 (Rounding_Mode (), 3393 (PostOpF64 3394 ((L3.snd o FP64.mul) 3395 (Rounding_Mode (), 3396 (Map.lookup((!FGR),BitsN.toNat fs), 3397 Map.lookup((!FGR),BitsN.toNat ft)))), 3398 Map.lookup((!FGR),BitsN.toNat fr)))))); 3399 3400fun dfn'MSUB_S (fd,(fr,(fs,ft))) = 3401 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3402 then SignalCP1UnusableException () 3403 else FGR := 3404 (Map.update 3405 ((!FGR),BitsN.toNat fd, 3406 BitsN.signExtend 64 3407 (PostOpF32 3408 ((L3.snd o FP32.sub) 3409 (Rounding_Mode (), 3410 (PostOpF32 3411 ((L3.snd o FP32.mul) 3412 (Rounding_Mode (), 3413 (BitsN.bits(31,0) 3414 (Map.lookup((!FGR),BitsN.toNat fs)), 3415 BitsN.bits(31,0) 3416 (Map.lookup((!FGR),BitsN.toNat ft))))), 3417 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fr)))))))); 3418 3419fun dfn'MUL_D (fd,(fs,ft)) = 3420 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3421 then SignalCP1UnusableException () 3422 else FGR := 3423 (Map.update 3424 ((!FGR),BitsN.toNat fd, 3425 PostOpF64 3426 ((L3.snd o FP64.mul) 3427 (Rounding_Mode (), 3428 (Map.lookup((!FGR),BitsN.toNat fs), 3429 Map.lookup((!FGR),BitsN.toNat ft)))))); 3430 3431fun dfn'MUL_S (fd,(fs,ft)) = 3432 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3433 then SignalCP1UnusableException () 3434 else FGR := 3435 (Map.update 3436 ((!FGR),BitsN.toNat fd, 3437 BitsN.signExtend 64 3438 (PostOpF32 3439 ((L3.snd o FP32.mul) 3440 (Rounding_Mode (), 3441 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), 3442 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))))))); 3443 3444fun dfn'NEG_D (fd,fs) = 3445 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3446 then SignalCP1UnusableException () 3447 else if #ABS2008((!fcsr) : FCSR) 3448 then FGR := 3449 (Map.update 3450 ((!FGR),BitsN.toNat fd, 3451 FP64.neg(Map.lookup((!FGR),BitsN.toNat fs)))) 3452 else FGR := 3453 (Map.update 3454 ((!FGR),BitsN.toNat fd, 3455 PostOpF64(FP64_Neg1985(Map.lookup((!FGR),BitsN.toNat fs))))); 3456 3457fun dfn'NEG_S (fd,fs) = 3458 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3459 then SignalCP1UnusableException () 3460 else if #ABS2008((!fcsr) : FCSR) 3461 then FGR := 3462 (Map.update 3463 ((!FGR),BitsN.toNat fd, 3464 BitsN.signExtend 64 3465 (FP32.neg 3466 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)))))) 3467 else FGR := 3468 (Map.update 3469 ((!FGR),BitsN.toNat fd, 3470 BitsN.signExtend 64 3471 (PostOpF32 3472 (FP32_Neg1985 3473 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))))); 3474 3475fun dfn'ROUND_L_D (fd,fs) = 3476 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3477 then SignalCP1UnusableException () 3478 else FGR := 3479 (Map.update 3480 ((!FGR),BitsN.toNat fd, 3481 case FP64.toInt 3482 (IEEEReal.TO_NEAREST,Map.lookup((!FGR),BitsN.toNat fs)) of 3483 Option.SOME x => IntToDWordMIPS x 3484 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 3485 3486fun dfn'ROUND_L_S (fd,fs) = 3487 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3488 then SignalCP1UnusableException () 3489 else FGR := 3490 (Map.update 3491 ((!FGR),BitsN.toNat fd, 3492 case FP32.toInt 3493 (IEEEReal.TO_NEAREST, 3494 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 3495 Option.SOME x => IntToDWordMIPS x 3496 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 3497 3498fun dfn'ROUND_W_D (fd,fs) = 3499 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3500 then SignalCP1UnusableException () 3501 else FGR := 3502 (Map.update 3503 ((!FGR),BitsN.toNat fd, 3504 case FP64.toInt 3505 (IEEEReal.TO_NEAREST,Map.lookup((!FGR),BitsN.toNat fs)) of 3506 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 3507 | NONE => BitsN.B(0x7FFFFFFF,64))); 3508 3509fun dfn'ROUND_W_S (fd,fs) = 3510 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3511 then SignalCP1UnusableException () 3512 else FGR := 3513 (Map.update 3514 ((!FGR),BitsN.toNat fd, 3515 case FP32.toInt 3516 (IEEEReal.TO_NEAREST, 3517 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 3518 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 3519 | NONE => BitsN.B(0x7FFFFFFF,64))); 3520 3521fun dfn'SDC1 (ft,(offset,base)) = 3522 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3523 then SignalCP1UnusableException () 3524 else let 3525 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 3526 val datadoubleword = Map.lookup((!FGR),BitsN.toNat ft) 3527 val _ = 3528 StoreMemory 3529 (DOUBLEWORD, 3530 (DOUBLEWORD,(true,(datadoubleword,(vAddr,false))))) 3531 in 3532 () 3533 end; 3534 3535fun dfn'SDXC1 (fs,(index,base)) = 3536 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3537 then SignalCP1UnusableException () 3538 else let 3539 val vAddr = BitsN.+(GPR index,GPR base) 3540 val datadoubleword = Map.lookup((!FGR),BitsN.toNat fs) 3541 val _ = 3542 StoreMemory 3543 (DOUBLEWORD, 3544 (DOUBLEWORD,(true,(datadoubleword,(vAddr,false))))) 3545 in 3546 () 3547 end; 3548 3549fun dfn'SQRT_D (fd,fs) = 3550 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3551 then SignalCP1UnusableException () 3552 else FGR := 3553 (Map.update 3554 ((!FGR),BitsN.toNat fd, 3555 PostOpF64 3556 ((L3.snd o FP64.sqrt) 3557 (Rounding_Mode (),Map.lookup((!FGR),BitsN.toNat fs))))); 3558 3559fun dfn'SQRT_S (fd,fs) = 3560 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3561 then SignalCP1UnusableException () 3562 else FGR := 3563 (Map.update 3564 ((!FGR),BitsN.toNat fd, 3565 BitsN.signExtend 64 3566 (PostOpF32 3567 ((L3.snd o FP32.sqrt) 3568 (Rounding_Mode (), 3569 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))))); 3570 3571fun dfn'SUB_D (fd,(fs,ft)) = 3572 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3573 then SignalCP1UnusableException () 3574 else FGR := 3575 (Map.update 3576 ((!FGR),BitsN.toNat fd, 3577 PostOpF64 3578 ((L3.snd o FP64.sub) 3579 (Rounding_Mode (), 3580 (Map.lookup((!FGR),BitsN.toNat fs), 3581 Map.lookup((!FGR),BitsN.toNat ft)))))); 3582 3583fun dfn'SUB_S (fd,(fs,ft)) = 3584 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3585 then SignalCP1UnusableException () 3586 else FGR := 3587 (Map.update 3588 ((!FGR),BitsN.toNat fd, 3589 BitsN.signExtend 64 3590 (PostOpF32 3591 ((L3.snd o FP32.sub) 3592 (Rounding_Mode (), 3593 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), 3594 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))))))); 3595 3596fun dfn'SWC1 (ft,(offset,base)) = 3597 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3598 then SignalCP1UnusableException () 3599 else let 3600 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 3601 val bytesel = 3602 BitsN.?? 3603 (BitsN.bits(2,0) vAddr, 3604 BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) 3605 val datadoubleword = 3606 BitsN.<< 3607 (Map.lookup((!FGR),BitsN.toNat ft), 3608 Nat.*(8,BitsN.toNat bytesel)) 3609 val _ = 3610 StoreMemory(WORD,(WORD,(true,(datadoubleword,(vAddr,false))))) 3611 in 3612 () 3613 end; 3614 3615fun dfn'SWXC1 (ft,(index,base)) = 3616 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3617 then SignalCP1UnusableException () 3618 else let 3619 val vAddr = BitsN.+(GPR index,GPR base) 3620 val bytesel = 3621 BitsN.?? 3622 (BitsN.bits(2,0) vAddr, 3623 BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) 3624 val datadoubleword = 3625 BitsN.<< 3626 (Map.lookup((!FGR),BitsN.toNat ft), 3627 Nat.*(8,BitsN.toNat bytesel)) 3628 val _ = 3629 StoreMemory(WORD,(WORD,(true,(datadoubleword,(vAddr,false))))) 3630 in 3631 () 3632 end; 3633 3634fun dfn'TRUNC_L_D (fd,fs) = 3635 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3636 then SignalCP1UnusableException () 3637 else FGR := 3638 (Map.update 3639 ((!FGR),BitsN.toNat fd, 3640 case FP64.toInt 3641 (IEEEReal.TO_ZERO,Map.lookup((!FGR),BitsN.toNat fs)) of 3642 Option.SOME x => IntToDWordMIPS x 3643 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 3644 3645fun dfn'TRUNC_L_S (fd,fs) = 3646 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3647 then SignalCP1UnusableException () 3648 else FGR := 3649 (Map.update 3650 ((!FGR),BitsN.toNat fd, 3651 case FP32.toInt 3652 (IEEEReal.TO_ZERO, 3653 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 3654 Option.SOME x => IntToDWordMIPS x 3655 | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); 3656 3657fun dfn'TRUNC_W_D (fd,fs) = 3658 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3659 then SignalCP1UnusableException () 3660 else FGR := 3661 (Map.update 3662 ((!FGR),BitsN.toNat fd, 3663 case FP64.toInt 3664 (IEEEReal.TO_ZERO,Map.lookup((!FGR),BitsN.toNat fs)) of 3665 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 3666 | NONE => BitsN.B(0x7FFFFFFF,64))); 3667 3668fun dfn'TRUNC_W_S (fd,fs) = 3669 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3670 then SignalCP1UnusableException () 3671 else FGR := 3672 (Map.update 3673 ((!FGR),BitsN.toNat fd, 3674 case FP32.toInt 3675 (IEEEReal.TO_ZERO, 3676 BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of 3677 Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) 3678 | NONE => BitsN.B(0x7FFFFFFF,64))); 3679 3680fun dfn'DMFC1 (rt,fs) = 3681 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3682 then SignalCP1UnusableException () 3683 else write'GPR(Map.lookup((!FGR),BitsN.toNat fs),rt); 3684 3685fun dfn'DMTC1 (rt,fs) = 3686 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3687 then SignalCP1UnusableException () 3688 else FGR := (Map.update((!FGR),BitsN.toNat fs,GPR rt)); 3689 3690fun dfn'MFC1 (rt,fs) = 3691 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3692 then SignalCP1UnusableException () 3693 else write'GPR 3694 (BitsN.signExtend 64 3695 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))),rt); 3696 3697fun dfn'MTC1 (rt,fs) = 3698 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3699 then SignalCP1UnusableException () 3700 else FGR := 3701 (Map.update 3702 ((!FGR),BitsN.toNat fs, 3703 BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rt)))); 3704 3705fun dfn'CFC1 (rt,fs) = 3706 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3707 then SignalCP1UnusableException () 3708 else write'GPR 3709 (case fs of 3710 BitsN.B(0x0,_) => BitsN.signExtend 64 (reg'FIR (!fir)) 3711 | BitsN.B(0x19,_) => BitsN.zeroExtend 64 (#FCC((!fcsr) : FCSR)) 3712 | BitsN.B(0x1F,_) => BitsN.signExtend 64 (reg'FCSR (!fcsr)) 3713 | _ => 3714 raise UNPREDICTABLE 3715 "Unsupported floating point control register",rt); 3716 3717fun dfn'CTC1 (rt,fs) = 3718 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3719 then SignalCP1UnusableException () 3720 else case fs of 3721 BitsN.B(0x0,_) => () 3722 | BitsN.B(0x19,_) => 3723 fcsr := (FCSR_FCC_rupd((!fcsr),BitsN.bits(7,0) (GPR rt))) 3724 | BitsN.B(0x1F,_) => 3725 ( fcsr := (write'reg'FCSR((!fcsr),BitsN.bits(31,0) (GPR rt))) 3726 ; fcsr := (FCSR_NAN2008_rupd((!fcsr),true)) 3727 ) 3728 | _ => 3729 raise UNPREDICTABLE 3730 "Unsupported floating point control register"; 3731 3732fun dfn'UnknownFPInstruction () = 3733 if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) 3734 then SignalCP1UnusableException () 3735 else SignalException ResI; 3736 3737fun dfn'ADDI (rs,(rt,immediate)) = 3738 ( if NotWordValue(GPR rs) 3739 then raise UNPREDICTABLE "ADDI: NotWordValue" 3740 else () 3741 ; let 3742 val temp = 3743 BitsN.+(BitsN.bits(32,0) (GPR rs),BitsN.signExtend 33 immediate) 3744 in 3745 if not((BitsN.bit(temp,32)) = (BitsN.bit(temp,31))) 3746 then SignalException Ov 3747 else write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) temp),rt) 3748 end 3749 ); 3750 3751fun dfn'ADDIU (rs,(rt,immediate)) = 3752 ( if NotWordValue(GPR rs) 3753 then raise UNPREDICTABLE "ADDIU: NotWordValue" 3754 else () 3755 ; let 3756 val temp = 3757 BitsN.+(BitsN.bits(31,0) (GPR rs),BitsN.signExtend 32 immediate) 3758 in 3759 write'GPR(BitsN.signExtend 64 temp,rt) 3760 end 3761 ); 3762 3763fun dfn'DADDI (rs,(rt,immediate)) = 3764 let 3765 val temp = 3766 BitsN.+(BitsN.signExtend 65 (GPR rs),BitsN.signExtend 65 immediate) 3767 in 3768 if not((BitsN.bit(temp,64)) = (BitsN.bit(temp,63))) 3769 then SignalException Ov 3770 else write'GPR(BitsN.bits(63,0) temp,rt) 3771 end; 3772 3773fun dfn'DADDIU (rs,(rt,immediate)) = 3774 write'GPR(BitsN.+(GPR rs,BitsN.signExtend 64 immediate),rt); 3775 3776fun dfn'SLTI (rs,(rt,immediate)) = 3777 write'GPR 3778 (BitsN.fromBool 64 (BitsN.<(GPR rs,BitsN.signExtend 64 immediate)),rt); 3779 3780fun dfn'SLTIU (rs,(rt,immediate)) = 3781 write'GPR 3782 (BitsN.fromBool 64 (BitsN.<+(GPR rs,BitsN.signExtend 64 immediate)),rt); 3783 3784fun dfn'ANDI (rs,(rt,immediate)) = 3785 write'GPR(BitsN.&&(GPR rs,BitsN.zeroExtend 64 immediate),rt); 3786 3787fun dfn'ORI (rs,(rt,immediate)) = 3788 write'GPR(BitsN.||(GPR rs,BitsN.zeroExtend 64 immediate),rt); 3789 3790fun dfn'XORI (rs,(rt,immediate)) = 3791 write'GPR(BitsN.??(GPR rs,BitsN.zeroExtend 64 immediate),rt); 3792 3793fun dfn'LUI (rt,immediate) = 3794 write'GPR(BitsN.signExtend 64 (BitsN.@@(immediate,BitsN.B(0x0,16))),rt); 3795 3796fun dfn'ADD (rs,(rt,rd)) = 3797 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3798 then raise UNPREDICTABLE "ADD: NotWordValue" 3799 else () 3800 ; let 3801 val temp = 3802 BitsN.+(BitsN.bits(32,0) (GPR rs),BitsN.bits(32,0) (GPR rt)) 3803 in 3804 if not((BitsN.bit(temp,32)) = (BitsN.bit(temp,31))) 3805 then SignalException Ov 3806 else write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) temp),rd) 3807 end 3808 ); 3809 3810fun dfn'ADDU (rs,(rt,rd)) = 3811 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3812 then raise UNPREDICTABLE "ADDU: NotWordValue" 3813 else () 3814 ; let 3815 val temp = 3816 BitsN.+(BitsN.bits(31,0) (GPR rs),BitsN.bits(31,0) (GPR rt)) 3817 in 3818 write'GPR(BitsN.signExtend 64 temp,rd) 3819 end 3820 ); 3821 3822fun dfn'SUB (rs,(rt,rd)) = 3823 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3824 then raise UNPREDICTABLE "SUB: NotWordValue" 3825 else () 3826 ; let 3827 val temp = 3828 BitsN.-(BitsN.bits(32,0) (GPR rs),BitsN.bits(32,0) (GPR rt)) 3829 in 3830 if not((BitsN.bit(temp,32)) = (BitsN.bit(temp,31))) 3831 then SignalException Ov 3832 else write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) temp),rd) 3833 end 3834 ); 3835 3836fun dfn'SUBU (rs,(rt,rd)) = 3837 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3838 then raise UNPREDICTABLE "SUBU: NotWordValue" 3839 else () 3840 ; let 3841 val temp = 3842 BitsN.-(BitsN.bits(31,0) (GPR rs),BitsN.bits(31,0) (GPR rt)) 3843 in 3844 write'GPR(BitsN.signExtend 64 temp,rd) 3845 end 3846 ); 3847 3848fun dfn'DADD (rs,(rt,rd)) = 3849 let 3850 val temp = 3851 BitsN.+(BitsN.signExtend 65 (GPR rs),BitsN.signExtend 65 (GPR rt)) 3852 in 3853 if not((BitsN.bit(temp,64)) = (BitsN.bit(temp,63))) 3854 then SignalException Ov 3855 else write'GPR(BitsN.bits(63,0) temp,rd) 3856 end; 3857 3858fun dfn'DADDU (rs,(rt,rd)) = write'GPR(BitsN.+(GPR rs,GPR rt),rd); 3859 3860fun dfn'DSUB (rs,(rt,rd)) = 3861 let 3862 val temp = 3863 BitsN.-(BitsN.signExtend 65 (GPR rs),BitsN.signExtend 65 (GPR rt)) 3864 in 3865 if not((BitsN.bit(temp,64)) = (BitsN.bit(temp,63))) 3866 then SignalException Ov 3867 else write'GPR(BitsN.bits(63,0) temp,rd) 3868 end; 3869 3870fun dfn'DSUBU (rs,(rt,rd)) = write'GPR(BitsN.-(GPR rs,GPR rt),rd); 3871 3872fun dfn'SLT (rs,(rt,rd)) = 3873 write'GPR(BitsN.fromBool 64 (BitsN.<(GPR rs,GPR rt)),rd); 3874 3875fun dfn'SLTU (rs,(rt,rd)) = 3876 write'GPR(BitsN.fromBool 64 (BitsN.<+(GPR rs,GPR rt)),rd); 3877 3878fun dfn'AND (rs,(rt,rd)) = write'GPR(BitsN.&&(GPR rs,GPR rt),rd); 3879 3880fun dfn'OR (rs,(rt,rd)) = write'GPR(BitsN.||(GPR rs,GPR rt),rd); 3881 3882fun dfn'XOR (rs,(rt,rd)) = write'GPR(BitsN.??(GPR rs,GPR rt),rd); 3883 3884fun dfn'NOR (rs,(rt,rd)) = write'GPR(BitsN.~(BitsN.||(GPR rs,GPR rt)),rd); 3885 3886fun dfn'MOVN (rs,(rt,rd)) = 3887 if not((GPR rt) = (BitsN.B(0x0,64))) then write'GPR(GPR rs,rd) else (); 3888 3889fun dfn'MOVZ (rs,(rt,rd)) = 3890 if (GPR rt) = (BitsN.B(0x0,64)) then write'GPR(GPR rs,rd) else (); 3891 3892fun dfn'MADD (rs,rt) = 3893 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3894 then raise UNPREDICTABLE "MADD: NotWordValue" 3895 else () 3896 ; let 3897 val temp = 3898 BitsN.+ 3899 (BitsN.@@(BitsN.bits(31,0) (HI ()),BitsN.bits(31,0) (LO ())), 3900 BitsN.* 3901 (BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs)), 3902 BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rt)))) 3903 in 3904 ( write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) temp)) 3905 ; write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) temp)) 3906 ) 3907 end 3908 ); 3909 3910fun dfn'MADDU (rs,rt) = 3911 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3912 then raise UNPREDICTABLE "MADDU: NotWordValue" 3913 else () 3914 ; let 3915 val temp = 3916 BitsN.+ 3917 (BitsN.@@(BitsN.bits(31,0) (HI ()),BitsN.bits(31,0) (LO ())), 3918 BitsN.* 3919 (BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs)), 3920 BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rt)))) 3921 in 3922 ( write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) temp)) 3923 ; write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) temp)) 3924 ) 3925 end 3926 ); 3927 3928fun dfn'MSUB (rs,rt) = 3929 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3930 then raise UNPREDICTABLE "MSUB: NotWordValue" 3931 else () 3932 ; let 3933 val temp = 3934 BitsN.- 3935 (BitsN.@@(BitsN.bits(31,0) (HI ()),BitsN.bits(31,0) (LO ())), 3936 BitsN.* 3937 (BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs)), 3938 BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rt)))) 3939 in 3940 ( write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) temp)) 3941 ; write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) temp)) 3942 ) 3943 end 3944 ); 3945 3946fun dfn'MSUBU (rs,rt) = 3947 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3948 then raise UNPREDICTABLE "MSUBU: NotWordValue" 3949 else () 3950 ; let 3951 val temp = 3952 BitsN.- 3953 (BitsN.@@(BitsN.bits(31,0) (HI ()),BitsN.bits(31,0) (LO ())), 3954 BitsN.* 3955 (BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs)), 3956 BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rt)))) 3957 in 3958 ( write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) temp)) 3959 ; write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) temp)) 3960 ) 3961 end 3962 ); 3963 3964fun dfn'MUL (rs,(rt,rd)) = 3965 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3966 then raise UNPREDICTABLE "MUL: NotWordValue" 3967 else () 3968 ; write'GPR 3969 (BitsN.signExtend 64 3970 (BitsN.*(BitsN.bits(31,0) (GPR rs),BitsN.bits(31,0) (GPR rt))),rd) 3971 ; lo := NONE 3972 ; hi := NONE 3973 ); 3974 3975fun dfn'MULT (rs,rt) = 3976 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3977 then raise UNPREDICTABLE "MULT: NotWordValue" 3978 else () 3979 ; let 3980 val prod = 3981 BitsN.* 3982 (BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs)), 3983 BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rt))) 3984 in 3985 ( write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) prod)) 3986 ; write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) prod)) 3987 ) 3988 end 3989 ); 3990 3991fun dfn'MULTU (rs,rt) = 3992 ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) 3993 then raise UNPREDICTABLE "MULTU: NotWordValue" 3994 else () 3995 ; let 3996 val prod = 3997 BitsN.* 3998 (BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs)), 3999 BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rt))) 4000 in 4001 ( write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) prod)) 4002 ; write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) prod)) 4003 ) 4004 end 4005 ); 4006 4007fun dfn'DMULT (rs,rt) = 4008 let 4009 val prod = 4010 BitsN.*(BitsN.signExtend 128 (GPR rs),BitsN.signExtend 128 (GPR rt)) 4011 in 4012 ( write'LO(BitsN.bits(63,0) prod); write'HI(BitsN.bits(127,64) prod) ) 4013 end; 4014 4015fun dfn'DMULTU (rs,rt) = 4016 let 4017 val prod = 4018 BitsN.*(BitsN.zeroExtend 128 (GPR rs),BitsN.zeroExtend 128 (GPR rt)) 4019 in 4020 ( write'LO(BitsN.bits(63,0) prod); write'HI(BitsN.bits(127,64) prod) ) 4021 end; 4022 4023fun dfn'DIV (rs,rt) = 4024 let 4025 val s = GPR rs 4026 val t = GPR rt 4027 in 4028 ( if (NotWordValue s) orelse (NotWordValue t) 4029 then raise UNPREDICTABLE "DIV: NotWordValue" 4030 else () 4031 ; if t = (BitsN.B(0x0,64)) 4032 then ( lo := NONE; hi := NONE ) 4033 else let 4034 val q = BitsN.quot(BitsN.bits(31,0) s,BitsN.bits(31,0) t) 4035 val r = BitsN.rem(BitsN.bits(31,0) s,BitsN.bits(31,0) t) 4036 in 4037 ( write'LO(BitsN.signExtend 64 q) 4038 ; write'HI(BitsN.signExtend 64 r) 4039 ) 4040 end 4041 ) 4042 end; 4043 4044fun dfn'DIVU (rs,rt) = 4045 let 4046 val s = GPR rs 4047 val t = GPR rt 4048 in 4049 ( if (NotWordValue s) orelse (NotWordValue t) 4050 then raise UNPREDICTABLE "DIVU: NotWordValue" 4051 else () 4052 ; if t = (BitsN.B(0x0,64)) 4053 then ( lo := NONE; hi := NONE ) 4054 else let 4055 val q = BitsN.div(BitsN.bits(31,0) s,BitsN.bits(31,0) t) 4056 val r = BitsN.mod(BitsN.bits(31,0) s,BitsN.bits(31,0) t) 4057 in 4058 ( write'LO(BitsN.signExtend 64 q) 4059 ; write'HI(BitsN.signExtend 64 r) 4060 ) 4061 end 4062 ) 4063 end; 4064 4065fun dfn'DDIV (rs,rt) = 4066 let 4067 val t = GPR rt 4068 in 4069 if t = (BitsN.B(0x0,64)) 4070 then ( lo := NONE; hi := NONE ) 4071 else let 4072 val s = GPR rs 4073 in 4074 ( write'LO(BitsN.quot(s,t)); write'HI(BitsN.rem(s,t)) ) 4075 end 4076 end; 4077 4078fun dfn'DDIVU (rs,rt) = 4079 let 4080 val t = GPR rt 4081 in 4082 if t = (BitsN.B(0x0,64)) 4083 then ( lo := NONE; hi := NONE ) 4084 else let 4085 val s = GPR rs 4086 in 4087 ( write'LO(BitsN.div(s,t)); write'HI(BitsN.mod(s,t)) ) 4088 end 4089 end; 4090 4091fun dfn'MFHI rd = write'GPR(HI (),rd); 4092 4093fun dfn'MFLO rd = write'GPR(LO (),rd); 4094 4095fun dfn'MTHI rs = write'HI(GPR rs); 4096 4097fun dfn'MTLO rs = write'LO(GPR rs); 4098 4099fun dfn'SLL (rt,(rd,sa)) = 4100 write'GPR 4101 (BitsN.signExtend 64 4102 (BitsN.<<(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd); 4103 4104fun dfn'SRL (rt,(rd,sa)) = 4105 ( if NotWordValue(GPR rt) 4106 then raise UNPREDICTABLE "SRL: NotWordValue" 4107 else () 4108 ; write'GPR 4109 (BitsN.signExtend 64 4110 (BitsN.>>+(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) 4111 ); 4112 4113fun dfn'SRA (rt,(rd,sa)) = 4114 ( if NotWordValue(GPR rt) 4115 then raise UNPREDICTABLE "SRA: NotWordValue" 4116 else () 4117 ; write'GPR 4118 (BitsN.signExtend 64 4119 (BitsN.>>(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) 4120 ); 4121 4122fun dfn'SLLV (rs,(rt,rd)) = 4123 let 4124 val sa = BitsN.bits(4,0) (GPR rs) 4125 in 4126 write'GPR 4127 (BitsN.signExtend 64 4128 (BitsN.<<(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) 4129 end; 4130 4131fun dfn'SRLV (rs,(rt,rd)) = 4132 ( if NotWordValue(GPR rt) 4133 then raise UNPREDICTABLE "SRLV: NotWordValue" 4134 else () 4135 ; let 4136 val sa = BitsN.bits(4,0) (GPR rs) 4137 in 4138 write'GPR 4139 (BitsN.signExtend 64 4140 (BitsN.>>+(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) 4141 end 4142 ); 4143 4144fun dfn'SRAV (rs,(rt,rd)) = 4145 ( if NotWordValue(GPR rt) 4146 then raise UNPREDICTABLE "SRAV: NotWordValue" 4147 else () 4148 ; let 4149 val sa = BitsN.bits(4,0) (GPR rs) 4150 in 4151 write'GPR 4152 (BitsN.signExtend 64 4153 (BitsN.>>(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) 4154 end 4155 ); 4156 4157fun dfn'DSLL (rt,(rd,sa)) = write'GPR(BitsN.<<(GPR rt,BitsN.toNat sa),rd); 4158 4159fun dfn'DSRL (rt,(rd,sa)) = 4160 write'GPR(BitsN.>>+(GPR rt,BitsN.toNat sa),rd); 4161 4162fun dfn'DSRA (rt,(rd,sa)) = write'GPR(BitsN.>>(GPR rt,BitsN.toNat sa),rd); 4163 4164fun dfn'DSLLV (rs,(rt,rd)) = 4165 let 4166 val sa = BitsN.bits(5,0) (GPR rs) 4167 in 4168 write'GPR(BitsN.<<(GPR rt,BitsN.toNat sa),rd) 4169 end; 4170 4171fun dfn'DSRLV (rs,(rt,rd)) = 4172 let 4173 val sa = BitsN.bits(5,0) (GPR rs) 4174 in 4175 write'GPR(BitsN.>>+(GPR rt,BitsN.toNat sa),rd) 4176 end; 4177 4178fun dfn'DSRAV (rs,(rt,rd)) = 4179 let 4180 val sa = BitsN.bits(5,0) (GPR rs) 4181 in 4182 write'GPR(BitsN.>>(GPR rt,BitsN.toNat sa),rd) 4183 end; 4184 4185fun dfn'DSLL32 (rt,(rd,sa)) = 4186 write'GPR(BitsN.<<(GPR rt,Nat.+(BitsN.toNat sa,32)),rd); 4187 4188fun dfn'DSRL32 (rt,(rd,sa)) = 4189 write'GPR(BitsN.>>+(GPR rt,Nat.+(BitsN.toNat sa,32)),rd); 4190 4191fun dfn'DSRA32 (rt,(rd,sa)) = 4192 write'GPR(BitsN.>>(GPR rt,Nat.+(BitsN.toNat sa,32)),rd); 4193 4194fun dfn'TGE (rs,rt) = 4195 if BitsN.>=(GPR rs,GPR rt) then SignalException Tr else (); 4196 4197fun dfn'TGEU (rs,rt) = 4198 if BitsN.>=+(GPR rs,GPR rt) then SignalException Tr else (); 4199 4200fun dfn'TLT (rs,rt) = 4201 if BitsN.<(GPR rs,GPR rt) then SignalException Tr else (); 4202 4203fun dfn'TLTU (rs,rt) = 4204 if BitsN.<+(GPR rs,GPR rt) then SignalException Tr else (); 4205 4206fun dfn'TEQ (rs,rt) = 4207 if (GPR rs) = (GPR rt) then SignalException Tr else (); 4208 4209fun dfn'TNE (rs,rt) = 4210 if not((GPR rs) = (GPR rt)) then SignalException Tr else (); 4211 4212fun dfn'TGEI (rs,immediate) = 4213 if BitsN.>=(GPR rs,BitsN.signExtend 64 immediate) 4214 then SignalException Tr 4215 else (); 4216 4217fun dfn'TGEIU (rs,immediate) = 4218 if BitsN.>=+(GPR rs,BitsN.signExtend 64 immediate) 4219 then SignalException Tr 4220 else (); 4221 4222fun dfn'TLTI (rs,immediate) = 4223 if BitsN.<(GPR rs,BitsN.signExtend 64 immediate) 4224 then SignalException Tr 4225 else (); 4226 4227fun dfn'TLTIU (rs,immediate) = 4228 if BitsN.<+(GPR rs,BitsN.signExtend 64 immediate) 4229 then SignalException Tr 4230 else (); 4231 4232fun dfn'TEQI (rs,immediate) = 4233 if (GPR rs) = (BitsN.signExtend 64 immediate) 4234 then SignalException Tr 4235 else (); 4236 4237fun dfn'TNEI (rs,immediate) = 4238 if not((GPR rs) = (BitsN.signExtend 64 immediate)) 4239 then SignalException Tr 4240 else (); 4241 4242fun dfn'LB (base,(rt,offset)) = loadByte(base,(rt,(offset,false))); 4243 4244fun dfn'LBU (base,(rt,offset)) = loadByte(base,(rt,(offset,true))); 4245 4246fun dfn'LH (base,(rt,offset)) = loadHalf(base,(rt,(offset,false))); 4247 4248fun dfn'LHU (base,(rt,offset)) = loadHalf(base,(rt,(offset,true))); 4249 4250fun dfn'LW (base,(rt,offset)) = 4251 loadWord(false,(base,(rt,(offset,false)))); 4252 4253fun dfn'LWU (base,(rt,offset)) = 4254 loadWord(false,(base,(rt,(offset,true)))); 4255 4256fun dfn'LL (base,(rt,offset)) = loadWord(true,(base,(rt,(offset,false)))); 4257 4258fun dfn'LD (base,(rt,offset)) = loadDoubleword(false,(base,(rt,offset))); 4259 4260fun dfn'LLD (base,(rt,offset)) = loadDoubleword(true,(base,(rt,offset))); 4261 4262fun dfn'LWL (base,(rt,offset)) = 4263 let 4264 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4265 val byte = 4266 BitsN.?? 4267 (BitsN.bits(1,0) vAddr, 4268 BitsN.resize_replicate 2 (BigEndianCPU (),2)) 4269 val memdoubleword = 4270 LoadMemory 4271 (WORD, 4272 (BitsN.@@(BitsN.B(0x0,1),byte),(false,(vAddr,Option.SOME false)))) 4273 in 4274 if not (!exceptionSignalled) 4275 then let 4276 val word = BitsN.??(BitsN.bits(2,2) vAddr,BigEndianCPU ()) 4277 val temp = 4278 case (word,byte) of 4279 (BitsN.B(0x0,_),BitsN.B(0x0,_)) => 4280 BitsN.@@ 4281 (BitsN.bits(7,0) memdoubleword, 4282 BitsN.bits(23,0) (GPR rt)) 4283 | (BitsN.B(0x0,_),BitsN.B(0x1,_)) => 4284 BitsN.@@ 4285 (BitsN.bits(15,0) memdoubleword, 4286 BitsN.bits(15,0) (GPR rt)) 4287 | (BitsN.B(0x0,_),BitsN.B(0x2,_)) => 4288 BitsN.@@ 4289 (BitsN.bits(23,0) memdoubleword, 4290 BitsN.bits(7,0) (GPR rt)) 4291 | (BitsN.B(0x0,_),BitsN.B(0x3,_)) => 4292 BitsN.bits(31,0) memdoubleword 4293 | (BitsN.B(0x1,_),BitsN.B(0x0,_)) => 4294 BitsN.@@ 4295 (BitsN.bits(39,32) memdoubleword, 4296 BitsN.bits(23,0) (GPR rt)) 4297 | (BitsN.B(0x1,_),BitsN.B(0x1,_)) => 4298 BitsN.@@ 4299 (BitsN.bits(47,32) memdoubleword, 4300 BitsN.bits(15,0) (GPR rt)) 4301 | (BitsN.B(0x1,_),BitsN.B(0x2,_)) => 4302 BitsN.@@ 4303 (BitsN.bits(55,32) memdoubleword, 4304 BitsN.bits(7,0) (GPR rt)) 4305 | (BitsN.B(0x1,_),BitsN.B(0x3,_)) => 4306 BitsN.bits(63,32) memdoubleword 4307 in 4308 write'GPR(BitsN.signExtend 64 temp,rt) 4309 end 4310 else () 4311 end; 4312 4313fun dfn'LWR (base,(rt,offset)) = 4314 let 4315 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4316 val byte = 4317 BitsN.?? 4318 (BitsN.bits(1,0) vAddr, 4319 BitsN.resize_replicate 2 (BigEndianCPU (),2)) 4320 val memdoubleword = 4321 LoadMemory 4322 (WORD, 4323 (BitsN.-(WORD,BitsN.@@(BitsN.B(0x0,1),byte)), 4324 (false,(vAddr,Option.SOME false)))) 4325 in 4326 if not (!exceptionSignalled) 4327 then let 4328 val word = BitsN.??(BitsN.bits(2,2) vAddr,BigEndianCPU ()) 4329 val temp = 4330 case (word,byte) of 4331 (BitsN.B(0x0,_),BitsN.B(0x0,_)) => 4332 BitsN.bits(31,0) memdoubleword 4333 | (BitsN.B(0x0,_),BitsN.B(0x1,_)) => 4334 BitsN.@@ 4335 (BitsN.bits(31,24) (GPR rt), 4336 BitsN.bits(31,8) memdoubleword) 4337 | (BitsN.B(0x0,_),BitsN.B(0x2,_)) => 4338 BitsN.@@ 4339 (BitsN.bits(31,16) (GPR rt), 4340 BitsN.bits(31,16) memdoubleword) 4341 | (BitsN.B(0x0,_),BitsN.B(0x3,_)) => 4342 BitsN.@@ 4343 (BitsN.bits(31,8) (GPR rt), 4344 BitsN.bits(31,24) memdoubleword) 4345 | (BitsN.B(0x1,_),BitsN.B(0x0,_)) => 4346 BitsN.bits(63,32) memdoubleword 4347 | (BitsN.B(0x1,_),BitsN.B(0x1,_)) => 4348 BitsN.@@ 4349 (BitsN.bits(31,24) (GPR rt), 4350 BitsN.bits(63,40) memdoubleword) 4351 | (BitsN.B(0x1,_),BitsN.B(0x2,_)) => 4352 BitsN.@@ 4353 (BitsN.bits(31,16) (GPR rt), 4354 BitsN.bits(63,48) memdoubleword) 4355 | (BitsN.B(0x1,_),BitsN.B(0x3,_)) => 4356 BitsN.@@ 4357 (BitsN.bits(31,8) (GPR rt), 4358 BitsN.bits(63,56) memdoubleword) 4359 in 4360 write'GPR(BitsN.signExtend 64 temp,rt) 4361 end 4362 else () 4363 end; 4364 4365fun dfn'LDL (base,(rt,offset)) = 4366 let 4367 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4368 val byte = 4369 BitsN.?? 4370 (BitsN.bits(2,0) vAddr, 4371 BitsN.resize_replicate 3 (BigEndianCPU (),3)) 4372 val memdoubleword = 4373 LoadMemory(DOUBLEWORD,(byte,(false,(vAddr,Option.SOME false)))) 4374 in 4375 if not (!exceptionSignalled) 4376 then write'GPR 4377 (case byte of 4378 BitsN.B(0x0,_) => 4379 BitsN.@@ 4380 (BitsN.bits(7,0) memdoubleword, 4381 BitsN.bits(55,0) (GPR rt)) 4382 | BitsN.B(0x1,_) => 4383 BitsN.@@ 4384 (BitsN.bits(15,0) memdoubleword, 4385 BitsN.bits(47,0) (GPR rt)) 4386 | BitsN.B(0x2,_) => 4387 BitsN.@@ 4388 (BitsN.bits(23,0) memdoubleword, 4389 BitsN.bits(39,0) (GPR rt)) 4390 | BitsN.B(0x3,_) => 4391 BitsN.@@ 4392 (BitsN.bits(31,0) memdoubleword, 4393 BitsN.bits(31,0) (GPR rt)) 4394 | BitsN.B(0x4,_) => 4395 BitsN.@@ 4396 (BitsN.bits(39,0) memdoubleword, 4397 BitsN.bits(23,0) (GPR rt)) 4398 | BitsN.B(0x5,_) => 4399 BitsN.@@ 4400 (BitsN.bits(47,0) memdoubleword, 4401 BitsN.bits(15,0) (GPR rt)) 4402 | BitsN.B(0x6,_) => 4403 BitsN.@@ 4404 (BitsN.bits(55,0) memdoubleword, 4405 BitsN.bits(7,0) (GPR rt)) 4406 | BitsN.B(0x7,_) => BitsN.bits(63,0) memdoubleword 4407 | _ => raise General.Bind,rt) 4408 else () 4409 end; 4410 4411fun dfn'LDR (base,(rt,offset)) = 4412 let 4413 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4414 val byte = 4415 BitsN.?? 4416 (BitsN.bits(2,0) vAddr, 4417 BitsN.resize_replicate 3 (BigEndianCPU (),3)) 4418 val memdoubleword = 4419 LoadMemory 4420 (DOUBLEWORD, 4421 (BitsN.-(DOUBLEWORD,byte),(false,(vAddr,Option.SOME false)))) 4422 in 4423 if not (!exceptionSignalled) 4424 then write'GPR 4425 (case byte of 4426 BitsN.B(0x0,_) => BitsN.bits(63,0) memdoubleword 4427 | BitsN.B(0x1,_) => 4428 BitsN.@@ 4429 (BitsN.bits(63,56) (GPR rt), 4430 BitsN.bits(63,8) memdoubleword) 4431 | BitsN.B(0x2,_) => 4432 BitsN.@@ 4433 (BitsN.bits(63,48) (GPR rt), 4434 BitsN.bits(63,16) memdoubleword) 4435 | BitsN.B(0x3,_) => 4436 BitsN.@@ 4437 (BitsN.bits(63,40) (GPR rt), 4438 BitsN.bits(63,24) memdoubleword) 4439 | BitsN.B(0x4,_) => 4440 BitsN.@@ 4441 (BitsN.bits(63,32) (GPR rt), 4442 BitsN.bits(63,32) memdoubleword) 4443 | BitsN.B(0x5,_) => 4444 BitsN.@@ 4445 (BitsN.bits(63,24) (GPR rt), 4446 BitsN.bits(63,40) memdoubleword) 4447 | BitsN.B(0x6,_) => 4448 BitsN.@@ 4449 (BitsN.bits(63,16) (GPR rt), 4450 BitsN.bits(63,48) memdoubleword) 4451 | BitsN.B(0x7,_) => 4452 BitsN.@@ 4453 (BitsN.bits(63,8) (GPR rt), 4454 BitsN.bits(63,56) memdoubleword) 4455 | _ => raise General.Bind,rt) 4456 else () 4457 end; 4458 4459fun dfn'SB (base,(rt,offset)) = 4460 let 4461 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4462 val bytesel = 4463 BitsN.?? 4464 (BitsN.bits(2,0) vAddr, 4465 BitsN.resize_replicate 3 (BigEndianCPU (),3)) 4466 val datadoubleword = BitsN.<<(GPR rt,Nat.*(8,BitsN.toNat bytesel)) 4467 val _ = 4468 StoreMemory(BYTE,(BYTE,(false,(datadoubleword,(vAddr,false))))) 4469 in 4470 () 4471 end; 4472 4473fun dfn'SH (base,(rt,offset)) = 4474 let 4475 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4476 val bytesel = 4477 BitsN.?? 4478 (BitsN.bits(2,0) vAddr, 4479 BitsN.@@ 4480 (BitsN.resize_replicate 2 (BigEndianCPU (),2),BitsN.B(0x0,1))) 4481 val datadoubleword = BitsN.<<(GPR rt,Nat.*(8,BitsN.toNat bytesel)) 4482 val _ = 4483 StoreMemory 4484 (HALFWORD,(HALFWORD,(true,(datadoubleword,(vAddr,false))))) 4485 in 4486 () 4487 end; 4488 4489fun dfn'SW (base,(rt,offset)) = 4490 let val _ = storeWord(base,(rt,(offset,false))) in () end; 4491 4492fun dfn'SD (base,(rt,offset)) = 4493 let val _ = storeDoubleword(base,(rt,(offset,false))) in () end; 4494 4495fun dfn'SC (base,(rt,offset)) = 4496 let 4497 val ret = BitsN.fromBool 64 (storeWord(base,(rt,(offset,true)))) 4498 in 4499 if not (!exceptionSignalled) then write'GPR(ret,rt) else () 4500 end; 4501 4502fun dfn'SCD (base,(rt,offset)) = 4503 let 4504 val ret = BitsN.fromBool 64 (storeDoubleword(base,(rt,(offset,true)))) 4505 in 4506 if not (!exceptionSignalled) then write'GPR(ret,rt) else () 4507 end; 4508 4509fun dfn'SWL (base,(rt,offset)) = 4510 let 4511 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4512 val byte = 4513 BitsN.?? 4514 (BitsN.bits(1,0) vAddr, 4515 BitsN.resize_replicate 2 (BigEndianCPU (),2)) 4516 val word = BitsN.??(BitsN.bits(2,2) vAddr,BigEndianCPU ()) 4517 val datadoubleword = 4518 case byte of 4519 BitsN.B(0x0,_) => 4520 BitsN.fromNat(BitsN.toNat(BitsN.bits(31,24) (GPR rt)),64) 4521 | BitsN.B(0x1,_) => 4522 BitsN.fromNat(BitsN.toNat(BitsN.bits(31,16) (GPR rt)),64) 4523 | BitsN.B(0x2,_) => 4524 BitsN.fromNat(BitsN.toNat(BitsN.bits(31,8) (GPR rt)),64) 4525 | BitsN.B(0x3,_) => 4526 BitsN.fromNat(BitsN.toNat(BitsN.bits(31,0) (GPR rt)),64) 4527 | _ => raise General.Bind 4528 val datadoubleword = 4529 if word = (BitsN.B(0x1,1)) 4530 then BitsN.<<(datadoubleword,32) 4531 else datadoubleword 4532 val _ = 4533 StoreMemory 4534 (WORD, 4535 (BitsN.fromNat(BitsN.toNat byte,3), 4536 (false,(datadoubleword,(vAddr,false))))) 4537 in 4538 () 4539 end; 4540 4541fun dfn'SWR (base,(rt,offset)) = 4542 let 4543 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4544 val byte = 4545 BitsN.?? 4546 (BitsN.bits(1,0) vAddr, 4547 BitsN.resize_replicate 2 (BigEndianCPU (),2)) 4548 val word = BitsN.??(BitsN.bits(2,2) vAddr,BigEndianCPU ()) 4549 val datadoubleword = 4550 case (word,byte) of 4551 (BitsN.B(0x0,_),BitsN.B(0x0,_)) => 4552 BitsN.fromNat(BitsN.toNat(BitsN.bits(31,0) (GPR rt)),64) 4553 | (BitsN.B(0x0,_),BitsN.B(0x1,_)) => 4554 BitsN.<< 4555 (BitsN.fromNat(BitsN.toNat(BitsN.bits(23,0) (GPR rt)),64),8) 4556 | (BitsN.B(0x0,_),BitsN.B(0x2,_)) => 4557 BitsN.<< 4558 (BitsN.fromNat(BitsN.toNat(BitsN.bits(15,0) (GPR rt)),64),16) 4559 | (BitsN.B(0x0,_),BitsN.B(0x3,_)) => 4560 BitsN.<< 4561 (BitsN.fromNat(BitsN.toNat(BitsN.bits(7,0) (GPR rt)),64),24) 4562 | (BitsN.B(0x1,_),BitsN.B(0x0,_)) => 4563 BitsN.<< 4564 (BitsN.fromNat(BitsN.toNat(BitsN.bits(31,0) (GPR rt)),64),32) 4565 | (BitsN.B(0x1,_),BitsN.B(0x1,_)) => 4566 BitsN.<< 4567 (BitsN.fromNat(BitsN.toNat(BitsN.bits(23,0) (GPR rt)),64),40) 4568 | (BitsN.B(0x1,_),BitsN.B(0x2,_)) => 4569 BitsN.<< 4570 (BitsN.fromNat(BitsN.toNat(BitsN.bits(15,0) (GPR rt)),64),48) 4571 | (BitsN.B(0x1,_),BitsN.B(0x3,_)) => 4572 BitsN.<< 4573 (BitsN.fromNat(BitsN.toNat(BitsN.bits(7,0) (GPR rt)),64),56) 4574 val _ = 4575 StoreMemory 4576 (WORD, 4577 (BitsN.-(WORD,BitsN.fromNat(BitsN.toNat byte,3)), 4578 (false,(datadoubleword,(vAddr,false))))) 4579 in 4580 () 4581 end; 4582 4583fun dfn'SDL (base,(rt,offset)) = 4584 let 4585 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4586 val byte = 4587 BitsN.?? 4588 (BitsN.bits(2,0) vAddr, 4589 BitsN.resize_replicate 3 (BigEndianCPU (),3)) 4590 val datadoubleword = 4591 case byte of 4592 BitsN.B(0x0,_) => 4593 BitsN.fromNat(BitsN.toNat(BitsN.bits(63,56) (GPR rt)),64) 4594 | BitsN.B(0x1,_) => 4595 BitsN.fromNat(BitsN.toNat(BitsN.bits(63,48) (GPR rt)),64) 4596 | BitsN.B(0x2,_) => 4597 BitsN.fromNat(BitsN.toNat(BitsN.bits(63,40) (GPR rt)),64) 4598 | BitsN.B(0x3,_) => 4599 BitsN.fromNat(BitsN.toNat(BitsN.bits(63,32) (GPR rt)),64) 4600 | BitsN.B(0x4,_) => 4601 BitsN.fromNat(BitsN.toNat(BitsN.bits(63,24) (GPR rt)),64) 4602 | BitsN.B(0x5,_) => 4603 BitsN.fromNat(BitsN.toNat(BitsN.bits(63,16) (GPR rt)),64) 4604 | BitsN.B(0x6,_) => 4605 BitsN.fromNat(BitsN.toNat(BitsN.bits(63,8) (GPR rt)),64) 4606 | BitsN.B(0x7,_) => GPR rt 4607 | _ => raise General.Bind 4608 val _ = 4609 StoreMemory 4610 (DOUBLEWORD,(byte,(false,(datadoubleword,(vAddr,false))))) 4611 in 4612 () 4613 end; 4614 4615fun dfn'SDR (base,(rt,offset)) = 4616 let 4617 val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) 4618 val byte = 4619 BitsN.?? 4620 (BitsN.bits(2,0) vAddr, 4621 BitsN.resize_replicate 3 (BigEndianCPU (),3)) 4622 val datadoubleword = 4623 case byte of 4624 BitsN.B(0x0,_) => GPR rt 4625 | BitsN.B(0x1,_) => 4626 BitsN.<< 4627 (BitsN.fromNat(BitsN.toNat(BitsN.bits(55,0) (GPR rt)),64),8) 4628 | BitsN.B(0x2,_) => 4629 BitsN.<< 4630 (BitsN.fromNat(BitsN.toNat(BitsN.bits(47,0) (GPR rt)),64),16) 4631 | BitsN.B(0x3,_) => 4632 BitsN.<< 4633 (BitsN.fromNat(BitsN.toNat(BitsN.bits(39,0) (GPR rt)),64),24) 4634 | BitsN.B(0x4,_) => 4635 BitsN.<< 4636 (BitsN.fromNat(BitsN.toNat(BitsN.bits(31,0) (GPR rt)),64),32) 4637 | BitsN.B(0x5,_) => 4638 BitsN.<< 4639 (BitsN.fromNat(BitsN.toNat(BitsN.bits(23,0) (GPR rt)),64),40) 4640 | BitsN.B(0x6,_) => 4641 BitsN.<< 4642 (BitsN.fromNat(BitsN.toNat(BitsN.bits(15,0) (GPR rt)),64),48) 4643 | BitsN.B(0x7,_) => 4644 BitsN.<< 4645 (BitsN.fromNat(BitsN.toNat(BitsN.bits(7,0) (GPR rt)),64),56) 4646 | _ => raise General.Bind 4647 val _ = 4648 StoreMemory 4649 (DOUBLEWORD, 4650 (BitsN.-(DOUBLEWORD,byte),(false,(datadoubleword,(vAddr,false))))) 4651 in 4652 () 4653 end; 4654 4655fun dfn'SYNC stype = (); 4656 4657fun dfn'BREAK () = SignalException Bp; 4658 4659fun dfn'SYSCALL () = SignalException Sys; 4660 4661fun dfn'ERET () = 4662 if Option.isSome (!BranchDelay) 4663 then raise UNPREDICTABLE "ERET follows branch" 4664 else if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse 4665 (KernelMode ()) 4666 then ( if #ERL((#Status((!CP0) : CP0)) : StatusRegister) 4667 then ( PC := 4668 (BitsN.-(#ErrorEPC((!CP0) : CP0),BitsN.B(0x4,64))) 4669 ; let 4670 val x0 = #Status((!CP0) : CP0) 4671 in 4672 CP0 := 4673 (CP0_Status_rupd 4674 ((!CP0),StatusRegister_ERL_rupd(x0,false))) 4675 end 4676 ) 4677 else ( PC := (BitsN.-(#EPC((!CP0) : CP0),BitsN.B(0x4,64))) 4678 ; let 4679 val x0 = #Status((!CP0) : CP0) 4680 in 4681 CP0 := 4682 (CP0_Status_rupd 4683 ((!CP0),StatusRegister_EXL_rupd(x0,false))) 4684 end 4685 ) 4686 ; LLbit := (Option.SOME false) 4687 ) 4688 else SignalException CpU; 4689 4690fun dfn'MTC0 (rt,(rd,sel)) = 4691 if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse 4692 (KernelMode ()) 4693 then let val x = (0,(rd,sel)) in write'CPR(GPR rt,x) end 4694 else SignalException CpU; 4695 4696fun dfn'DMTC0 (rt,(rd,sel)) = 4697 if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse 4698 (KernelMode ()) 4699 then let val x = (0,(rd,sel)) in write'CPR(GPR rt,x) end 4700 else SignalException CpU; 4701 4702fun dfn'MFC0 (rt,(rd,sel)) = 4703 if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse 4704 (KernelMode ()) 4705 then write'GPR 4706 (BitsN.signExtend 64 (BitsN.bits(31,0) (CPR(0,(rd,sel)))),rt) 4707 else SignalException CpU; 4708 4709fun dfn'DMFC0 (rt,(rd,sel)) = 4710 if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse 4711 (KernelMode ()) 4712 then write'GPR(CPR(0,(rd,sel)),rt) 4713 else SignalException CpU; 4714 4715fun dfn'J instr_index = 4716 BranchTo := 4717 (Option.SOME 4718 (false, 4719 BitsN.concat[BitsN.bits(63,28) (!PC),instr_index,BitsN.B(0x0,2)])); 4720 4721fun dfn'JAL instr_index = 4722 ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) 4723 ; BranchTo := 4724 (Option.SOME 4725 (false, 4726 BitsN.concat[BitsN.bits(63,28) (!PC),instr_index,BitsN.B(0x0,2)])) 4727 ); 4728 4729fun dfn'JR rs = BranchTo := (Option.SOME(false,GPR rs)); 4730 4731fun dfn'JALR (rs,rd) = 4732 let 4733 val temp = GPR rs 4734 in 4735 ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),rd) 4736 ; BranchTo := (Option.SOME(false,temp)) 4737 ) 4738 end; 4739 4740fun dfn'BEQ (rs,(rt,offset)) = 4741 ConditionalBranch((GPR rs) = (GPR rt),offset); 4742 4743fun dfn'BNE (rs,(rt,offset)) = 4744 ConditionalBranch(not((GPR rs) = (GPR rt)),offset); 4745 4746fun dfn'BLEZ (rs,offset) = 4747 ConditionalBranch(BitsN.<=(GPR rs,BitsN.B(0x0,64)),offset); 4748 4749fun dfn'BGTZ (rs,offset) = 4750 ConditionalBranch(BitsN.>(GPR rs,BitsN.B(0x0,64)),offset); 4751 4752fun dfn'BLTZ (rs,offset) = 4753 ConditionalBranch(BitsN.<(GPR rs,BitsN.B(0x0,64)),offset); 4754 4755fun dfn'BGEZ (rs,offset) = 4756 ConditionalBranch(BitsN.>=(GPR rs,BitsN.B(0x0,64)),offset); 4757 4758fun dfn'BLTZAL (rs,offset) = 4759 let 4760 val temp = GPR rs 4761 in 4762 ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) 4763 ; ConditionalBranch(BitsN.<(temp,BitsN.B(0x0,64)),offset) 4764 ) 4765 end; 4766 4767fun dfn'BGEZAL (rs,offset) = 4768 let 4769 val temp = GPR rs 4770 in 4771 ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) 4772 ; ConditionalBranch(BitsN.>=(temp,BitsN.B(0x0,64)),offset) 4773 ) 4774 end; 4775 4776fun dfn'BEQL (rs,(rt,offset)) = 4777 ConditionalBranchLikely((GPR rs) = (GPR rt),offset); 4778 4779fun dfn'BNEL (rs,(rt,offset)) = 4780 ConditionalBranchLikely(not((GPR rs) = (GPR rt)),offset); 4781 4782fun dfn'BLEZL (rs,offset) = 4783 ConditionalBranchLikely(BitsN.<=(GPR rs,BitsN.B(0x0,64)),offset); 4784 4785fun dfn'BGTZL (rs,offset) = 4786 ConditionalBranchLikely(BitsN.>(GPR rs,BitsN.B(0x0,64)),offset); 4787 4788fun dfn'BLTZL (rs,offset) = 4789 ConditionalBranchLikely(BitsN.<(GPR rs,BitsN.B(0x0,64)),offset); 4790 4791fun dfn'BGEZL (rs,offset) = 4792 ConditionalBranchLikely(BitsN.>=(GPR rs,BitsN.B(0x0,64)),offset); 4793 4794fun dfn'BLTZALL (rs,offset) = 4795 let 4796 val temp = GPR rs 4797 in 4798 ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) 4799 ; ConditionalBranchLikely(BitsN.<(temp,BitsN.B(0x0,64)),offset) 4800 ) 4801 end; 4802 4803fun dfn'BGEZALL (rs,offset) = 4804 let 4805 val temp = GPR rs 4806 in 4807 ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) 4808 ; ConditionalBranchLikely(BitsN.>=(temp,BitsN.B(0x0,64)),offset) 4809 ) 4810 end; 4811 4812val dfn'WAIT = () 4813 4814fun dfn'TLBP () = SignalException ResI; 4815 4816fun dfn'TLBR () = SignalException ResI; 4817 4818fun dfn'TLBWI () = SignalException ResI; 4819 4820fun dfn'TLBWR () = SignalException ResI; 4821 4822fun dfn'CACHE (base,(opn,offset)) = SignalException ResI; 4823 4824fun dfn'RDHWR (rt,rd) = SignalException ResI; 4825 4826fun dfn'ReservedInstruction () = SignalException ResI; 4827 4828fun dfn'Unpredictable () = 4829 raise UNPREDICTABLE "Unpredictable instruction"; 4830 4831fun Run v0 = 4832 case v0 of 4833 BREAK => dfn'BREAK () 4834 | ERET => dfn'ERET () 4835 | ReservedInstruction => dfn'ReservedInstruction () 4836 | SYSCALL => dfn'SYSCALL () 4837 | TLBP => dfn'TLBP () 4838 | TLBR => dfn'TLBR () 4839 | TLBWI => dfn'TLBWI () 4840 | TLBWR => dfn'TLBWR () 4841 | Unpredictable => dfn'Unpredictable () 4842 | WAIT => dfn'WAIT 4843 | CACHE v204 => dfn'CACHE v204 4844 | RDHWR v205 => dfn'RDHWR v205 4845 | SYNC v206 => dfn'SYNC v206 4846 | ArithI v1 => 4847 (case v1 of 4848 ADDI v2 => dfn'ADDI v2 4849 | ADDIU v3 => dfn'ADDIU v3 4850 | ANDI v4 => dfn'ANDI v4 4851 | DADDI v5 => dfn'DADDI v5 4852 | DADDIU v6 => dfn'DADDIU v6 4853 | LUI v7 => dfn'LUI v7 4854 | ORI v8 => dfn'ORI v8 4855 | SLTI v9 => dfn'SLTI v9 4856 | SLTIU v10 => dfn'SLTIU v10 4857 | XORI v11 => dfn'XORI v11) 4858 | ArithR v12 => 4859 (case v12 of 4860 ADD v13 => dfn'ADD v13 4861 | ADDU v14 => dfn'ADDU v14 4862 | AND v15 => dfn'AND v15 4863 | DADD v16 => dfn'DADD v16 4864 | DADDU v17 => dfn'DADDU v17 4865 | DSUB v18 => dfn'DSUB v18 4866 | DSUBU v19 => dfn'DSUBU v19 4867 | MOVN v20 => dfn'MOVN v20 4868 | MOVZ v21 => dfn'MOVZ v21 4869 | NOR v22 => dfn'NOR v22 4870 | OR v23 => dfn'OR v23 4871 | SLT v24 => dfn'SLT v24 4872 | SLTU v25 => dfn'SLTU v25 4873 | SUB v26 => dfn'SUB v26 4874 | SUBU v27 => dfn'SUBU v27 4875 | XOR v28 => dfn'XOR v28) 4876 | Branch v29 => 4877 (case v29 of 4878 BEQ v30 => dfn'BEQ v30 4879 | BEQL v31 => dfn'BEQL v31 4880 | BGEZ v32 => dfn'BGEZ v32 4881 | BGEZAL v33 => dfn'BGEZAL v33 4882 | BGEZALL v34 => dfn'BGEZALL v34 4883 | BGEZL v35 => dfn'BGEZL v35 4884 | BGTZ v36 => dfn'BGTZ v36 4885 | BGTZL v37 => dfn'BGTZL v37 4886 | BLEZ v38 => dfn'BLEZ v38 4887 | BLEZL v39 => dfn'BLEZL v39 4888 | BLTZ v40 => dfn'BLTZ v40 4889 | BLTZAL v41 => dfn'BLTZAL v41 4890 | BLTZALL v42 => dfn'BLTZALL v42 4891 | BLTZL v43 => dfn'BLTZL v43 4892 | BNE v44 => dfn'BNE v44 4893 | BNEL v45 => dfn'BNEL v45 4894 | J v46 => dfn'J v46 4895 | JAL v47 => dfn'JAL v47 4896 | JALR v48 => dfn'JALR v48 4897 | JR v49 => dfn'JR v49) 4898 | COP1 v50 => 4899 (case v50 of 4900 UnknownFPInstruction => dfn'UnknownFPInstruction () 4901 | ABS_D v51 => dfn'ABS_D v51 4902 | ABS_S v52 => dfn'ABS_S v52 4903 | ADD_D v53 => dfn'ADD_D v53 4904 | ADD_S v54 => dfn'ADD_S v54 4905 | BC1F v55 => dfn'BC1F v55 4906 | BC1FL v56 => dfn'BC1FL v56 4907 | BC1T v57 => dfn'BC1T v57 4908 | BC1TL v58 => dfn'BC1TL v58 4909 | CEIL_L_D v59 => dfn'CEIL_L_D v59 4910 | CEIL_L_S v60 => dfn'CEIL_L_S v60 4911 | CEIL_W_D v61 => dfn'CEIL_W_D v61 4912 | CEIL_W_S v62 => dfn'CEIL_W_S v62 4913 | CFC1 v63 => dfn'CFC1 v63 4914 | CTC1 v64 => dfn'CTC1 v64 4915 | CVT_D_L v65 => dfn'CVT_D_L v65 4916 | CVT_D_S v66 => dfn'CVT_D_S v66 4917 | CVT_D_W v67 => dfn'CVT_D_W v67 4918 | CVT_L_D v68 => dfn'CVT_L_D v68 4919 | CVT_L_S v69 => dfn'CVT_L_S v69 4920 | CVT_S_D v70 => dfn'CVT_S_D v70 4921 | CVT_S_L v71 => dfn'CVT_S_L v71 4922 | CVT_S_W v72 => dfn'CVT_S_W v72 4923 | CVT_W_D v73 => dfn'CVT_W_D v73 4924 | CVT_W_S v74 => dfn'CVT_W_S v74 4925 | C_cond_D v75 => dfn'C_cond_D v75 4926 | C_cond_S v76 => dfn'C_cond_S v76 4927 | DIV_D v77 => dfn'DIV_D v77 4928 | DIV_S v78 => dfn'DIV_S v78 4929 | DMFC1 v79 => dfn'DMFC1 v79 4930 | DMTC1 v80 => dfn'DMTC1 v80 4931 | FLOOR_L_D v81 => dfn'FLOOR_L_D v81 4932 | FLOOR_L_S v82 => dfn'FLOOR_L_S v82 4933 | FLOOR_W_D v83 => dfn'FLOOR_W_D v83 4934 | FLOOR_W_S v84 => dfn'FLOOR_W_S v84 4935 | LDC1 v85 => dfn'LDC1 v85 4936 | LDXC1 v86 => dfn'LDXC1 v86 4937 | LWC1 v87 => dfn'LWC1 v87 4938 | LWXC1 v88 => dfn'LWXC1 v88 4939 | MADD_D v89 => dfn'MADD_D v89 4940 | MADD_S v90 => dfn'MADD_S v90 4941 | MFC1 v91 => dfn'MFC1 v91 4942 | MOVF v92 => dfn'MOVF v92 4943 | MOVF_D v93 => dfn'MOVF_D v93 4944 | MOVF_S v94 => dfn'MOVF_S v94 4945 | MOVN_D v95 => dfn'MOVN_D v95 4946 | MOVN_S v96 => dfn'MOVN_S v96 4947 | MOVT v97 => dfn'MOVT v97 4948 | MOVT_D v98 => dfn'MOVT_D v98 4949 | MOVT_S v99 => dfn'MOVT_S v99 4950 | MOVZ_D v100 => dfn'MOVZ_D v100 4951 | MOVZ_S v101 => dfn'MOVZ_S v101 4952 | MOV_D v102 => dfn'MOV_D v102 4953 | MOV_S v103 => dfn'MOV_S v103 4954 | MSUB_D v104 => dfn'MSUB_D v104 4955 | MSUB_S v105 => dfn'MSUB_S v105 4956 | MTC1 v106 => dfn'MTC1 v106 4957 | MUL_D v107 => dfn'MUL_D v107 4958 | MUL_S v108 => dfn'MUL_S v108 4959 | NEG_D v109 => dfn'NEG_D v109 4960 | NEG_S v110 => dfn'NEG_S v110 4961 | ROUND_L_D v111 => dfn'ROUND_L_D v111 4962 | ROUND_L_S v112 => dfn'ROUND_L_S v112 4963 | ROUND_W_D v113 => dfn'ROUND_W_D v113 4964 | ROUND_W_S v114 => dfn'ROUND_W_S v114 4965 | SDC1 v115 => dfn'SDC1 v115 4966 | SDXC1 v116 => dfn'SDXC1 v116 4967 | SQRT_D v117 => dfn'SQRT_D v117 4968 | SQRT_S v118 => dfn'SQRT_S v118 4969 | SUB_D v119 => dfn'SUB_D v119 4970 | SUB_S v120 => dfn'SUB_S v120 4971 | SWC1 v121 => dfn'SWC1 v121 4972 | SWXC1 v122 => dfn'SWXC1 v122 4973 | TRUNC_L_D v123 => dfn'TRUNC_L_D v123 4974 | TRUNC_L_S v124 => dfn'TRUNC_L_S v124 4975 | TRUNC_W_D v125 => dfn'TRUNC_W_D v125 4976 | TRUNC_W_S v126 => dfn'TRUNC_W_S v126) 4977 | CP v127 => 4978 (case v127 of 4979 DMFC0 v128 => dfn'DMFC0 v128 4980 | DMTC0 v129 => dfn'DMTC0 v129 4981 | MFC0 v130 => dfn'MFC0 v130 4982 | MTC0 v131 => dfn'MTC0 v131) 4983 | Load v132 => 4984 (case v132 of 4985 LB v133 => dfn'LB v133 4986 | LBU v134 => dfn'LBU v134 4987 | LD v135 => dfn'LD v135 4988 | LDL v136 => dfn'LDL v136 4989 | LDR v137 => dfn'LDR v137 4990 | LH v138 => dfn'LH v138 4991 | LHU v139 => dfn'LHU v139 4992 | LL v140 => dfn'LL v140 4993 | LLD v141 => dfn'LLD v141 4994 | LW v142 => dfn'LW v142 4995 | LWL v143 => dfn'LWL v143 4996 | LWR v144 => dfn'LWR v144 4997 | LWU v145 => dfn'LWU v145) 4998 | MultDiv v146 => 4999 (case v146 of 5000 DDIV v147 => dfn'DDIV v147 5001 | DDIVU v148 => dfn'DDIVU v148 5002 | DIV v149 => dfn'DIV v149 5003 | DIVU v150 => dfn'DIVU v150 5004 | DMULT v151 => dfn'DMULT v151 5005 | DMULTU v152 => dfn'DMULTU v152 5006 | MADD v153 => dfn'MADD v153 5007 | MADDU v154 => dfn'MADDU v154 5008 | MFHI v155 => dfn'MFHI v155 5009 | MFLO v156 => dfn'MFLO v156 5010 | MSUB v157 => dfn'MSUB v157 5011 | MSUBU v158 => dfn'MSUBU v158 5012 | MTHI v159 => dfn'MTHI v159 5013 | MTLO v160 => dfn'MTLO v160 5014 | MUL v161 => dfn'MUL v161 5015 | MULT v162 => dfn'MULT v162 5016 | MULTU v163 => dfn'MULTU v163) 5017 | Shift v164 => 5018 (case v164 of 5019 DSLL v165 => dfn'DSLL v165 5020 | DSLL32 v166 => dfn'DSLL32 v166 5021 | DSLLV v167 => dfn'DSLLV v167 5022 | DSRA v168 => dfn'DSRA v168 5023 | DSRA32 v169 => dfn'DSRA32 v169 5024 | DSRAV v170 => dfn'DSRAV v170 5025 | DSRL v171 => dfn'DSRL v171 5026 | DSRL32 v172 => dfn'DSRL32 v172 5027 | DSRLV v173 => dfn'DSRLV v173 5028 | SLL v174 => dfn'SLL v174 5029 | SLLV v175 => dfn'SLLV v175 5030 | SRA v176 => dfn'SRA v176 5031 | SRAV v177 => dfn'SRAV v177 5032 | SRL v178 => dfn'SRL v178 5033 | SRLV v179 => dfn'SRLV v179) 5034 | Store v180 => 5035 (case v180 of 5036 SB v181 => dfn'SB v181 5037 | SC v182 => dfn'SC v182 5038 | SCD v183 => dfn'SCD v183 5039 | SD v184 => dfn'SD v184 5040 | SDL v185 => dfn'SDL v185 5041 | SDR v186 => dfn'SDR v186 5042 | SH v187 => dfn'SH v187 5043 | SW v188 => dfn'SW v188 5044 | SWL v189 => dfn'SWL v189 5045 | SWR v190 => dfn'SWR v190) 5046 | Trap v191 => 5047 (case v191 of 5048 TEQ v192 => dfn'TEQ v192 5049 | TEQI v193 => dfn'TEQI v193 5050 | TGE v194 => dfn'TGE v194 5051 | TGEI v195 => dfn'TGEI v195 5052 | TGEIU v196 => dfn'TGEIU v196 5053 | TGEU v197 => dfn'TGEU v197 5054 | TLT v198 => dfn'TLT v198 5055 | TLTI v199 => dfn'TLTI v199 5056 | TLTIU v200 => dfn'TLTIU v200 5057 | TLTU v201 => dfn'TLTU v201 5058 | TNE v202 => dfn'TNE v202 5059 | TNEI v203 => dfn'TNEI v203); 5060 5061fun COP1Decode v = 5062 COP1 5063 (case boolify'26 v of 5064 (false, 5065 (false, 5066 (false, 5067 (false, 5068 (false, 5069 (rt'4, 5070 (rt'3, 5071 (rt'2, 5072 (rt'1, 5073 (rt'0, 5074 (fs'4, 5075 (fs'3, 5076 (fs'2, 5077 (fs'1, 5078 (fs'0, 5079 (false, 5080 (false, 5081 (false, 5082 (false, 5083 (false, 5084 (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => 5085 MFC1 5086 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 5087 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5088 | (false, 5089 (false, 5090 (false, 5091 (false, 5092 (true, 5093 (rt'4, 5094 (rt'3, 5095 (rt'2, 5096 (rt'1, 5097 (rt'0, 5098 (fs'4, 5099 (fs'3, 5100 (fs'2, 5101 (fs'1, 5102 (fs'0, 5103 (false, 5104 (false, 5105 (false, 5106 (false, 5107 (false, 5108 (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => 5109 DMFC1 5110 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 5111 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5112 | (false, 5113 (false, 5114 (false, 5115 (true, 5116 (false, 5117 (rt'4, 5118 (rt'3, 5119 (rt'2, 5120 (rt'1, 5121 (rt'0, 5122 (fs'4, 5123 (fs'3, 5124 (fs'2, 5125 (fs'1, 5126 (fs'0, 5127 (false, 5128 (false, 5129 (false, 5130 (false, 5131 (false, 5132 (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => 5133 CFC1 5134 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 5135 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5136 | (false, 5137 (false, 5138 (true, 5139 (false, 5140 (false, 5141 (rt'4, 5142 (rt'3, 5143 (rt'2, 5144 (rt'1, 5145 (rt'0, 5146 (fs'4, 5147 (fs'3, 5148 (fs'2, 5149 (fs'1, 5150 (fs'0, 5151 (false, 5152 (false, 5153 (false, 5154 (false, 5155 (false, 5156 (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => 5157 MTC1 5158 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 5159 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5160 | (false, 5161 (false, 5162 (true, 5163 (false, 5164 (true, 5165 (rt'4, 5166 (rt'3, 5167 (rt'2, 5168 (rt'1, 5169 (rt'0, 5170 (fs'4, 5171 (fs'3, 5172 (fs'2, 5173 (fs'1, 5174 (fs'0, 5175 (false, 5176 (false, 5177 (false, 5178 (false, 5179 (false, 5180 (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => 5181 DMTC1 5182 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 5183 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5184 | (false, 5185 (false, 5186 (true, 5187 (true, 5188 (false, 5189 (rt'4, 5190 (rt'3, 5191 (rt'2, 5192 (rt'1, 5193 (rt'0, 5194 (fs'4, 5195 (fs'3, 5196 (fs'2, 5197 (fs'1, 5198 (fs'0, 5199 (false, 5200 (false, 5201 (false, 5202 (false, 5203 (false, 5204 (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => 5205 CTC1 5206 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 5207 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5208 | (false, 5209 (true, 5210 (false, 5211 (false, 5212 (false, 5213 (cc'2, 5214 (cc'1, 5215 (cc'0, 5216 (false, 5217 (false, 5218 (i'15, 5219 (i'14, 5220 (i'13, 5221 (i'12, 5222 (i'11, 5223 (i'10, 5224 (i'9, 5225 (i'8,(i'7,(i'6,(i'5,(i'4,(i'3,(i'2,(i'1,i'0))))))))))))))))))))))))) => 5226 BC1F 5227 (BitsN.fromBitstring 5228 ([i'15,i'14,i'13,i'12,i'11,i'10,i'9,i'8,i'7,i'6,i'5,i'4,i'3, 5229 i'2,i'1,i'0],16),BitsN.fromBitstring([cc'2,cc'1,cc'0],3)) 5230 | (false, 5231 (true, 5232 (false, 5233 (false, 5234 (false, 5235 (cc'2, 5236 (cc'1, 5237 (cc'0, 5238 (false, 5239 (true, 5240 (i'15, 5241 (i'14, 5242 (i'13, 5243 (i'12, 5244 (i'11, 5245 (i'10, 5246 (i'9, 5247 (i'8,(i'7,(i'6,(i'5,(i'4,(i'3,(i'2,(i'1,i'0))))))))))))))))))))))))) => 5248 BC1T 5249 (BitsN.fromBitstring 5250 ([i'15,i'14,i'13,i'12,i'11,i'10,i'9,i'8,i'7,i'6,i'5,i'4,i'3, 5251 i'2,i'1,i'0],16),BitsN.fromBitstring([cc'2,cc'1,cc'0],3)) 5252 | (false, 5253 (true, 5254 (false, 5255 (false, 5256 (false, 5257 (cc'2, 5258 (cc'1, 5259 (cc'0, 5260 (true, 5261 (false, 5262 (i'15, 5263 (i'14, 5264 (i'13, 5265 (i'12, 5266 (i'11, 5267 (i'10, 5268 (i'9, 5269 (i'8,(i'7,(i'6,(i'5,(i'4,(i'3,(i'2,(i'1,i'0))))))))))))))))))))))))) => 5270 BC1FL 5271 (BitsN.fromBitstring 5272 ([i'15,i'14,i'13,i'12,i'11,i'10,i'9,i'8,i'7,i'6,i'5,i'4,i'3, 5273 i'2,i'1,i'0],16),BitsN.fromBitstring([cc'2,cc'1,cc'0],3)) 5274 | (false, 5275 (true, 5276 (false, 5277 (false, 5278 (false, 5279 (cc'2, 5280 (cc'1, 5281 (cc'0, 5282 (true, 5283 (true, 5284 (i'15, 5285 (i'14, 5286 (i'13, 5287 (i'12, 5288 (i'11, 5289 (i'10, 5290 (i'9, 5291 (i'8,(i'7,(i'6,(i'5,(i'4,(i'3,(i'2,(i'1,i'0))))))))))))))))))))))))) => 5292 BC1TL 5293 (BitsN.fromBitstring 5294 ([i'15,i'14,i'13,i'12,i'11,i'10,i'9,i'8,i'7,i'6,i'5,i'4,i'3, 5295 i'2,i'1,i'0],16),BitsN.fromBitstring([cc'2,cc'1,cc'0],3)) 5296 | (true, 5297 (false, 5298 (false, 5299 (false, 5300 (false, 5301 (ft'4, 5302 (ft'3, 5303 (ft'2, 5304 (ft'1, 5305 (ft'0, 5306 (fs'4, 5307 (fs'3, 5308 (fs'2, 5309 (fs'1, 5310 (fs'0, 5311 (fd'4, 5312 (fd'3, 5313 (fd'2, 5314 (fd'1, 5315 (fd'0, 5316 (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => 5317 ADD_S 5318 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5319 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5320 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) 5321 | (true, 5322 (false, 5323 (false, 5324 (false, 5325 (false, 5326 (ft'4, 5327 (ft'3, 5328 (ft'2, 5329 (ft'1, 5330 (ft'0, 5331 (fs'4, 5332 (fs'3, 5333 (fs'2, 5334 (fs'1, 5335 (fs'0, 5336 (fd'4, 5337 (fd'3, 5338 (fd'2, 5339 (fd'1, 5340 (fd'0, 5341 (false,(false,(false,(false,(false,true))))))))))))))))))))))))) => 5342 SUB_S 5343 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5344 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5345 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) 5346 | (true, 5347 (false, 5348 (false, 5349 (false, 5350 (false, 5351 (ft'4, 5352 (ft'3, 5353 (ft'2, 5354 (ft'1, 5355 (ft'0, 5356 (fs'4, 5357 (fs'3, 5358 (fs'2, 5359 (fs'1, 5360 (fs'0, 5361 (fd'4, 5362 (fd'3, 5363 (fd'2, 5364 (fd'1, 5365 (fd'0, 5366 (false,(false,(false,(false,(true,false))))))))))))))))))))))))) => 5367 MUL_S 5368 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5369 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5370 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) 5371 | (true, 5372 (false, 5373 (false, 5374 (false, 5375 (false, 5376 (ft'4, 5377 (ft'3, 5378 (ft'2, 5379 (ft'1, 5380 (ft'0, 5381 (fs'4, 5382 (fs'3, 5383 (fs'2, 5384 (fs'1, 5385 (fs'0, 5386 (fd'4, 5387 (fd'3, 5388 (fd'2, 5389 (fd'1, 5390 (fd'0,(false,(false,(false,(false,(true,true))))))))))))))))))))))))) => 5391 DIV_S 5392 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5393 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5394 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) 5395 | (true, 5396 (false, 5397 (false, 5398 (false, 5399 (false, 5400 (false, 5401 (false, 5402 (false, 5403 (false, 5404 (false, 5405 (fs'4, 5406 (fs'3, 5407 (fs'2, 5408 (fs'1, 5409 (fs'0, 5410 (fd'4, 5411 (fd'3, 5412 (fd'2, 5413 (fd'1, 5414 (fd'0, 5415 (false,(false,(false,(true,(false,false))))))))))))))))))))))))) => 5416 SQRT_S 5417 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5418 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5419 | (true, 5420 (false, 5421 (false, 5422 (false, 5423 (false, 5424 (false, 5425 (false, 5426 (false, 5427 (false, 5428 (false, 5429 (fs'4, 5430 (fs'3, 5431 (fs'2, 5432 (fs'1, 5433 (fs'0, 5434 (fd'4, 5435 (fd'3, 5436 (fd'2, 5437 (fd'1, 5438 (fd'0,(false,(false,(false,(true,(false,true))))))))))))))))))))))))) => 5439 ABS_S 5440 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5441 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5442 | (true, 5443 (false, 5444 (false, 5445 (false, 5446 (false, 5447 (false, 5448 (false, 5449 (false, 5450 (false, 5451 (false, 5452 (fs'4, 5453 (fs'3, 5454 (fs'2, 5455 (fs'1, 5456 (fs'0, 5457 (fd'4, 5458 (fd'3, 5459 (fd'2, 5460 (fd'1, 5461 (fd'0,(false,(false,(false,(true,(true,false))))))))))))))))))))))))) => 5462 MOV_S 5463 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5464 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5465 | (true, 5466 (false, 5467 (false, 5468 (false, 5469 (false, 5470 (false, 5471 (false, 5472 (false, 5473 (false, 5474 (false, 5475 (fs'4, 5476 (fs'3, 5477 (fs'2, 5478 (fs'1, 5479 (fs'0, 5480 (fd'4, 5481 (fd'3, 5482 (fd'2, 5483 (fd'1, 5484 (fd'0,(false,(false,(false,(true,(true,true))))))))))))))))))))))))) => 5485 NEG_S 5486 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5487 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5488 | (true, 5489 (false, 5490 (false, 5491 (false, 5492 (false, 5493 (false, 5494 (false, 5495 (false, 5496 (false, 5497 (false, 5498 (fs'4, 5499 (fs'3, 5500 (fs'2, 5501 (fs'1, 5502 (fs'0, 5503 (fd'4, 5504 (fd'3, 5505 (fd'2, 5506 (fd'1, 5507 (fd'0, 5508 (false,(false,(true,(false,(false,false))))))))))))))))))))))))) => 5509 ROUND_L_S 5510 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5511 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5512 | (true, 5513 (false, 5514 (false, 5515 (false, 5516 (false, 5517 (false, 5518 (false, 5519 (false, 5520 (false, 5521 (false, 5522 (fs'4, 5523 (fs'3, 5524 (fs'2, 5525 (fs'1, 5526 (fs'0, 5527 (fd'4, 5528 (fd'3, 5529 (fd'2, 5530 (fd'1, 5531 (fd'0,(false,(false,(true,(false,(false,true))))))))))))))))))))))))) => 5532 TRUNC_L_S 5533 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5534 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5535 | (true, 5536 (false, 5537 (false, 5538 (false, 5539 (false, 5540 (false, 5541 (false, 5542 (false, 5543 (false, 5544 (false, 5545 (fs'4, 5546 (fs'3, 5547 (fs'2, 5548 (fs'1, 5549 (fs'0, 5550 (fd'4, 5551 (fd'3, 5552 (fd'2, 5553 (fd'1, 5554 (fd'0,(false,(false,(true,(false,(true,false))))))))))))))))))))))))) => 5555 CEIL_L_S 5556 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5557 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5558 | (true, 5559 (false, 5560 (false, 5561 (false, 5562 (false, 5563 (false, 5564 (false, 5565 (false, 5566 (false, 5567 (false, 5568 (fs'4, 5569 (fs'3, 5570 (fs'2, 5571 (fs'1, 5572 (fs'0, 5573 (fd'4, 5574 (fd'3, 5575 (fd'2, 5576 (fd'1, 5577 (fd'0,(false,(false,(true,(false,(true,true))))))))))))))))))))))))) => 5578 FLOOR_L_S 5579 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5580 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5581 | (true, 5582 (false, 5583 (false, 5584 (false, 5585 (false, 5586 (false, 5587 (false, 5588 (false, 5589 (false, 5590 (false, 5591 (fs'4, 5592 (fs'3, 5593 (fs'2, 5594 (fs'1, 5595 (fs'0, 5596 (fd'4, 5597 (fd'3, 5598 (fd'2, 5599 (fd'1, 5600 (fd'0,(false,(false,(true,(true,(false,false))))))))))))))))))))))))) => 5601 ROUND_W_S 5602 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5603 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5604 | (true, 5605 (false, 5606 (false, 5607 (false, 5608 (false, 5609 (false, 5610 (false, 5611 (false, 5612 (false, 5613 (false, 5614 (fs'4, 5615 (fs'3, 5616 (fs'2, 5617 (fs'1, 5618 (fs'0, 5619 (fd'4, 5620 (fd'3, 5621 (fd'2, 5622 (fd'1, 5623 (fd'0,(false,(false,(true,(true,(false,true))))))))))))))))))))))))) => 5624 TRUNC_W_S 5625 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5626 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5627 | (true, 5628 (false, 5629 (false, 5630 (false, 5631 (false, 5632 (false, 5633 (false, 5634 (false, 5635 (false, 5636 (false, 5637 (fs'4, 5638 (fs'3, 5639 (fs'2, 5640 (fs'1, 5641 (fs'0, 5642 (fd'4, 5643 (fd'3, 5644 (fd'2, 5645 (fd'1, 5646 (fd'0,(false,(false,(true,(true,(true,false))))))))))))))))))))))))) => 5647 CEIL_W_S 5648 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5649 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5650 | (true, 5651 (false, 5652 (false, 5653 (false, 5654 (false, 5655 (false, 5656 (false, 5657 (false, 5658 (false, 5659 (false, 5660 (fs'4, 5661 (fs'3, 5662 (fs'2, 5663 (fs'1, 5664 (fs'0, 5665 (fd'4, 5666 (fd'3, 5667 (fd'2, 5668 (fd'1, 5669 (fd'0,(false,(false,(true,(true,(true,true))))))))))))))))))))))))) => 5670 FLOOR_W_S 5671 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5672 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5673 | (true, 5674 (false, 5675 (false, 5676 (false, 5677 (false, 5678 (cc'2, 5679 (cc'1, 5680 (cc'0, 5681 (false, 5682 (false, 5683 (fs'4, 5684 (fs'3, 5685 (fs'2, 5686 (fs'1, 5687 (fs'0, 5688 (fd'4, 5689 (fd'3, 5690 (fd'2, 5691 (fd'1, 5692 (fd'0,(false,(true,(false,(false,(false,true))))))))))))))))))))))))) => 5693 MOVF_S 5694 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5695 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5696 BitsN.fromBitstring([cc'2,cc'1,cc'0],3))) 5697 | (true, 5698 (false, 5699 (false, 5700 (false, 5701 (false, 5702 (cc'2, 5703 (cc'1, 5704 (cc'0, 5705 (false, 5706 (true, 5707 (fs'4, 5708 (fs'3, 5709 (fs'2, 5710 (fs'1, 5711 (fs'0, 5712 (fd'4, 5713 (fd'3, 5714 (fd'2, 5715 (fd'1, 5716 (fd'0,(false,(true,(false,(false,(false,true))))))))))))))))))))))))) => 5717 MOVT_S 5718 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5719 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5720 BitsN.fromBitstring([cc'2,cc'1,cc'0],3))) 5721 | (true, 5722 (false, 5723 (false, 5724 (false, 5725 (false, 5726 (rt'4, 5727 (rt'3, 5728 (rt'2, 5729 (rt'1, 5730 (rt'0, 5731 (fs'4, 5732 (fs'3, 5733 (fs'2, 5734 (fs'1, 5735 (fs'0, 5736 (fd'4, 5737 (fd'3, 5738 (fd'2, 5739 (fd'1, 5740 (fd'0,(false,(true,(false,(false,(true,false))))))))))))))))))))))))) => 5741 MOVZ_S 5742 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5743 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5744 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 5745 | (true, 5746 (false, 5747 (false, 5748 (false, 5749 (false, 5750 (rt'4, 5751 (rt'3, 5752 (rt'2, 5753 (rt'1, 5754 (rt'0, 5755 (fs'4, 5756 (fs'3, 5757 (fs'2, 5758 (fs'1, 5759 (fs'0, 5760 (fd'4, 5761 (fd'3, 5762 (fd'2, 5763 (fd'1, 5764 (fd'0,(false,(true,(false,(false,(true,true))))))))))))))))))))))))) => 5765 MOVN_S 5766 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5767 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5768 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 5769 | (true, 5770 (false, 5771 (false, 5772 (false, 5773 (false, 5774 (ft'4, 5775 (ft'3, 5776 (ft'2, 5777 (ft'1, 5778 (ft'0, 5779 (fs'4, 5780 (fs'3, 5781 (fs'2, 5782 (fs'1, 5783 (fs'0, 5784 (cc'2, 5785 (cc'1, 5786 (cc'0, 5787 (false, 5788 (false, 5789 (true,(true,(false,(cnd'2,(cnd'1,cnd'0))))))))))))))))))))))))) => 5790 C_cond_S 5791 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5792 (BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5), 5793 (BitsN.fromBitstring([cnd'2,cnd'1,cnd'0],3), 5794 BitsN.fromBitstring([cc'2,cc'1,cc'0],3)))) 5795 | (true, 5796 (false, 5797 (false, 5798 (false, 5799 (true, 5800 (ft'4, 5801 (ft'3, 5802 (ft'2, 5803 (ft'1, 5804 (ft'0, 5805 (fs'4, 5806 (fs'3, 5807 (fs'2, 5808 (fs'1, 5809 (fs'0, 5810 (fd'4, 5811 (fd'3, 5812 (fd'2, 5813 (fd'1, 5814 (fd'0, 5815 (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => 5816 ADD_D 5817 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5818 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5819 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) 5820 | (true, 5821 (false, 5822 (false, 5823 (false, 5824 (true, 5825 (ft'4, 5826 (ft'3, 5827 (ft'2, 5828 (ft'1, 5829 (ft'0, 5830 (fs'4, 5831 (fs'3, 5832 (fs'2, 5833 (fs'1, 5834 (fs'0, 5835 (fd'4, 5836 (fd'3, 5837 (fd'2, 5838 (fd'1, 5839 (fd'0, 5840 (false,(false,(false,(false,(false,true))))))))))))))))))))))))) => 5841 SUB_D 5842 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5843 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5844 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) 5845 | (true, 5846 (false, 5847 (false, 5848 (false, 5849 (true, 5850 (ft'4, 5851 (ft'3, 5852 (ft'2, 5853 (ft'1, 5854 (ft'0, 5855 (fs'4, 5856 (fs'3, 5857 (fs'2, 5858 (fs'1, 5859 (fs'0, 5860 (fd'4, 5861 (fd'3, 5862 (fd'2, 5863 (fd'1, 5864 (fd'0, 5865 (false,(false,(false,(false,(true,false))))))))))))))))))))))))) => 5866 MUL_D 5867 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5868 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5869 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) 5870 | (true, 5871 (false, 5872 (false, 5873 (false, 5874 (true, 5875 (ft'4, 5876 (ft'3, 5877 (ft'2, 5878 (ft'1, 5879 (ft'0, 5880 (fs'4, 5881 (fs'3, 5882 (fs'2, 5883 (fs'1, 5884 (fs'0, 5885 (fd'4, 5886 (fd'3, 5887 (fd'2, 5888 (fd'1, 5889 (fd'0,(false,(false,(false,(false,(true,true))))))))))))))))))))))))) => 5890 DIV_D 5891 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5892 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 5893 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) 5894 | (true, 5895 (false, 5896 (false, 5897 (false, 5898 (true, 5899 (false, 5900 (false, 5901 (false, 5902 (false, 5903 (false, 5904 (fs'4, 5905 (fs'3, 5906 (fs'2, 5907 (fs'1, 5908 (fs'0, 5909 (fd'4, 5910 (fd'3, 5911 (fd'2, 5912 (fd'1, 5913 (fd'0, 5914 (false,(false,(false,(true,(false,false))))))))))))))))))))))))) => 5915 SQRT_D 5916 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5917 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5918 | (true, 5919 (false, 5920 (false, 5921 (false, 5922 (true, 5923 (false, 5924 (false, 5925 (false, 5926 (false, 5927 (false, 5928 (fs'4, 5929 (fs'3, 5930 (fs'2, 5931 (fs'1, 5932 (fs'0, 5933 (fd'4, 5934 (fd'3, 5935 (fd'2, 5936 (fd'1, 5937 (fd'0,(false,(false,(false,(true,(false,true))))))))))))))))))))))))) => 5938 ABS_D 5939 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5940 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5941 | (true, 5942 (false, 5943 (false, 5944 (false, 5945 (true, 5946 (false, 5947 (false, 5948 (false, 5949 (false, 5950 (false, 5951 (fs'4, 5952 (fs'3, 5953 (fs'2, 5954 (fs'1, 5955 (fs'0, 5956 (fd'4, 5957 (fd'3, 5958 (fd'2, 5959 (fd'1, 5960 (fd'0,(false,(false,(false,(true,(true,false))))))))))))))))))))))))) => 5961 MOV_D 5962 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5963 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5964 | (true, 5965 (false, 5966 (false, 5967 (false, 5968 (true, 5969 (false, 5970 (false, 5971 (false, 5972 (false, 5973 (false, 5974 (fs'4, 5975 (fs'3, 5976 (fs'2, 5977 (fs'1, 5978 (fs'0, 5979 (fd'4, 5980 (fd'3, 5981 (fd'2, 5982 (fd'1, 5983 (fd'0,(false,(false,(false,(true,(true,true))))))))))))))))))))))))) => 5984 NEG_D 5985 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 5986 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 5987 | (true, 5988 (false, 5989 (false, 5990 (false, 5991 (true, 5992 (false, 5993 (false, 5994 (false, 5995 (false, 5996 (false, 5997 (fs'4, 5998 (fs'3, 5999 (fs'2, 6000 (fs'1, 6001 (fs'0, 6002 (fd'4, 6003 (fd'3, 6004 (fd'2, 6005 (fd'1, 6006 (fd'0, 6007 (false,(false,(true,(false,(false,false))))))))))))))))))))))))) => 6008 ROUND_L_D 6009 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6010 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6011 | (true, 6012 (false, 6013 (false, 6014 (false, 6015 (true, 6016 (false, 6017 (false, 6018 (false, 6019 (false, 6020 (false, 6021 (fs'4, 6022 (fs'3, 6023 (fs'2, 6024 (fs'1, 6025 (fs'0, 6026 (fd'4, 6027 (fd'3, 6028 (fd'2, 6029 (fd'1, 6030 (fd'0,(false,(false,(true,(false,(false,true))))))))))))))))))))))))) => 6031 TRUNC_L_D 6032 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6033 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6034 | (true, 6035 (false, 6036 (false, 6037 (false, 6038 (true, 6039 (false, 6040 (false, 6041 (false, 6042 (false, 6043 (false, 6044 (fs'4, 6045 (fs'3, 6046 (fs'2, 6047 (fs'1, 6048 (fs'0, 6049 (fd'4, 6050 (fd'3, 6051 (fd'2, 6052 (fd'1, 6053 (fd'0,(false,(false,(true,(false,(true,false))))))))))))))))))))))))) => 6054 CEIL_L_D 6055 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6056 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6057 | (true, 6058 (false, 6059 (false, 6060 (false, 6061 (true, 6062 (false, 6063 (false, 6064 (false, 6065 (false, 6066 (false, 6067 (fs'4, 6068 (fs'3, 6069 (fs'2, 6070 (fs'1, 6071 (fs'0, 6072 (fd'4, 6073 (fd'3, 6074 (fd'2, 6075 (fd'1, 6076 (fd'0,(false,(false,(true,(false,(true,true))))))))))))))))))))))))) => 6077 FLOOR_L_D 6078 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6079 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6080 | (true, 6081 (false, 6082 (false, 6083 (false, 6084 (true, 6085 (false, 6086 (false, 6087 (false, 6088 (false, 6089 (false, 6090 (fs'4, 6091 (fs'3, 6092 (fs'2, 6093 (fs'1, 6094 (fs'0, 6095 (fd'4, 6096 (fd'3, 6097 (fd'2, 6098 (fd'1, 6099 (fd'0,(false,(false,(true,(true,(false,false))))))))))))))))))))))))) => 6100 ROUND_W_D 6101 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6102 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6103 | (true, 6104 (false, 6105 (false, 6106 (false, 6107 (true, 6108 (false, 6109 (false, 6110 (false, 6111 (false, 6112 (false, 6113 (fs'4, 6114 (fs'3, 6115 (fs'2, 6116 (fs'1, 6117 (fs'0, 6118 (fd'4, 6119 (fd'3, 6120 (fd'2, 6121 (fd'1, 6122 (fd'0,(false,(false,(true,(true,(false,true))))))))))))))))))))))))) => 6123 TRUNC_W_D 6124 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6125 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6126 | (true, 6127 (false, 6128 (false, 6129 (false, 6130 (true, 6131 (false, 6132 (false, 6133 (false, 6134 (false, 6135 (false, 6136 (fs'4, 6137 (fs'3, 6138 (fs'2, 6139 (fs'1, 6140 (fs'0, 6141 (fd'4, 6142 (fd'3, 6143 (fd'2, 6144 (fd'1, 6145 (fd'0,(false,(false,(true,(true,(true,false))))))))))))))))))))))))) => 6146 CEIL_W_D 6147 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6148 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6149 | (true, 6150 (false, 6151 (false, 6152 (false, 6153 (true, 6154 (false, 6155 (false, 6156 (false, 6157 (false, 6158 (false, 6159 (fs'4, 6160 (fs'3, 6161 (fs'2, 6162 (fs'1, 6163 (fs'0, 6164 (fd'4, 6165 (fd'3, 6166 (fd'2, 6167 (fd'1, 6168 (fd'0,(false,(false,(true,(true,(true,true))))))))))))))))))))))))) => 6169 FLOOR_W_D 6170 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6171 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6172 | (true, 6173 (false, 6174 (false, 6175 (false, 6176 (true, 6177 (cc'2, 6178 (cc'1, 6179 (cc'0, 6180 (false, 6181 (false, 6182 (fs'4, 6183 (fs'3, 6184 (fs'2, 6185 (fs'1, 6186 (fs'0, 6187 (fd'4, 6188 (fd'3, 6189 (fd'2, 6190 (fd'1, 6191 (fd'0,(false,(true,(false,(false,(false,true))))))))))))))))))))))))) => 6192 MOVF_D 6193 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6194 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6195 BitsN.fromBitstring([cc'2,cc'1,cc'0],3))) 6196 | (true, 6197 (false, 6198 (false, 6199 (false, 6200 (true, 6201 (cc'2, 6202 (cc'1, 6203 (cc'0, 6204 (false, 6205 (true, 6206 (fs'4, 6207 (fs'3, 6208 (fs'2, 6209 (fs'1, 6210 (fs'0, 6211 (fd'4, 6212 (fd'3, 6213 (fd'2, 6214 (fd'1, 6215 (fd'0,(false,(true,(false,(false,(false,true))))))))))))))))))))))))) => 6216 MOVT_D 6217 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6218 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6219 BitsN.fromBitstring([cc'2,cc'1,cc'0],3))) 6220 | (true, 6221 (false, 6222 (false, 6223 (false, 6224 (true, 6225 (rt'4, 6226 (rt'3, 6227 (rt'2, 6228 (rt'1, 6229 (rt'0, 6230 (fs'4, 6231 (fs'3, 6232 (fs'2, 6233 (fs'1, 6234 (fs'0, 6235 (fd'4, 6236 (fd'3, 6237 (fd'2, 6238 (fd'1, 6239 (fd'0,(false,(true,(false,(false,(true,false))))))))))))))))))))))))) => 6240 MOVZ_D 6241 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6242 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6243 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 6244 | (true, 6245 (false, 6246 (false, 6247 (false, 6248 (true, 6249 (rt'4, 6250 (rt'3, 6251 (rt'2, 6252 (rt'1, 6253 (rt'0, 6254 (fs'4, 6255 (fs'3, 6256 (fs'2, 6257 (fs'1, 6258 (fs'0, 6259 (fd'4, 6260 (fd'3, 6261 (fd'2, 6262 (fd'1, 6263 (fd'0,(false,(true,(false,(false,(true,true))))))))))))))))))))))))) => 6264 MOVN_D 6265 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6266 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6267 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 6268 | (true, 6269 (false, 6270 (false, 6271 (false, 6272 (true, 6273 (ft'4, 6274 (ft'3, 6275 (ft'2, 6276 (ft'1, 6277 (ft'0, 6278 (fs'4, 6279 (fs'3, 6280 (fs'2, 6281 (fs'1, 6282 (fs'0, 6283 (cc'2, 6284 (cc'1, 6285 (cc'0, 6286 (false, 6287 (false, 6288 (true,(true,(false,(cnd'2,(cnd'1,cnd'0))))))))))))))))))))))))) => 6289 C_cond_D 6290 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6291 (BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5), 6292 (BitsN.fromBitstring([cnd'2,cnd'1,cnd'0],3), 6293 BitsN.fromBitstring([cc'2,cc'1,cc'0],3)))) 6294 | (true, 6295 (false, 6296 (false, 6297 (false, 6298 (true, 6299 (false, 6300 (false, 6301 (false, 6302 (false, 6303 (false, 6304 (fs'4, 6305 (fs'3, 6306 (fs'2, 6307 (fs'1, 6308 (fs'0, 6309 (fd'4, 6310 (fd'3, 6311 (fd'2, 6312 (fd'1, 6313 (fd'0, 6314 (true,(false,(false,(false,(false,false))))))))))))))))))))))))) => 6315 CVT_S_D 6316 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6317 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6318 | (true, 6319 (false, 6320 (true, 6321 (false, 6322 (false, 6323 (false, 6324 (false, 6325 (false, 6326 (false, 6327 (false, 6328 (fs'4, 6329 (fs'3, 6330 (fs'2, 6331 (fs'1, 6332 (fs'0, 6333 (fd'4, 6334 (fd'3, 6335 (fd'2, 6336 (fd'1, 6337 (fd'0, 6338 (true,(false,(false,(false,(false,false))))))))))))))))))))))))) => 6339 CVT_S_W 6340 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6341 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6342 | (true, 6343 (false, 6344 (true, 6345 (false, 6346 (true, 6347 (false, 6348 (false, 6349 (false, 6350 (false, 6351 (false, 6352 (fs'4, 6353 (fs'3, 6354 (fs'2, 6355 (fs'1, 6356 (fs'0, 6357 (fd'4, 6358 (fd'3, 6359 (fd'2, 6360 (fd'1, 6361 (fd'0, 6362 (true,(false,(false,(false,(false,false))))))))))))))))))))))))) => 6363 CVT_S_L 6364 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6365 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6366 | (true, 6367 (false, 6368 (false, 6369 (false, 6370 (false, 6371 (false, 6372 (false, 6373 (false, 6374 (false, 6375 (false, 6376 (fs'4, 6377 (fs'3, 6378 (fs'2, 6379 (fs'1, 6380 (fs'0, 6381 (fd'4, 6382 (fd'3, 6383 (fd'2, 6384 (fd'1, 6385 (fd'0,(true,(false,(false,(false,(false,true))))))))))))))))))))))))) => 6386 CVT_D_S 6387 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6388 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6389 | (true, 6390 (false, 6391 (true, 6392 (false, 6393 (false, 6394 (false, 6395 (false, 6396 (false, 6397 (false, 6398 (false, 6399 (fs'4, 6400 (fs'3, 6401 (fs'2, 6402 (fs'1, 6403 (fs'0, 6404 (fd'4, 6405 (fd'3, 6406 (fd'2, 6407 (fd'1, 6408 (fd'0,(true,(false,(false,(false,(false,true))))))))))))))))))))))))) => 6409 CVT_D_W 6410 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6411 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6412 | (true, 6413 (false, 6414 (true, 6415 (false, 6416 (true, 6417 (false, 6418 (false, 6419 (false, 6420 (false, 6421 (false, 6422 (fs'4, 6423 (fs'3, 6424 (fs'2, 6425 (fs'1, 6426 (fs'0, 6427 (fd'4, 6428 (fd'3, 6429 (fd'2, 6430 (fd'1, 6431 (fd'0,(true,(false,(false,(false,(false,true))))))))))))))))))))))))) => 6432 CVT_D_L 6433 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6434 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6435 | (true, 6436 (false, 6437 (false, 6438 (false, 6439 (false, 6440 (false, 6441 (false, 6442 (false, 6443 (false, 6444 (false, 6445 (fs'4, 6446 (fs'3, 6447 (fs'2, 6448 (fs'1, 6449 (fs'0, 6450 (fd'4, 6451 (fd'3, 6452 (fd'2, 6453 (fd'1, 6454 (fd'0,(true,(false,(false,(true,(false,false))))))))))))))))))))))))) => 6455 CVT_W_S 6456 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6457 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6458 | (true, 6459 (false, 6460 (false, 6461 (false, 6462 (true, 6463 (false, 6464 (false, 6465 (false, 6466 (false, 6467 (false, 6468 (fs'4, 6469 (fs'3, 6470 (fs'2, 6471 (fs'1, 6472 (fs'0, 6473 (fd'4, 6474 (fd'3, 6475 (fd'2, 6476 (fd'1, 6477 (fd'0,(true,(false,(false,(true,(false,false))))))))))))))))))))))))) => 6478 CVT_W_D 6479 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6480 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6481 | (true, 6482 (false, 6483 (false, 6484 (false, 6485 (false, 6486 (false, 6487 (false, 6488 (false, 6489 (false, 6490 (false, 6491 (fs'4, 6492 (fs'3, 6493 (fs'2, 6494 (fs'1, 6495 (fs'0, 6496 (fd'4, 6497 (fd'3, 6498 (fd'2, 6499 (fd'1, 6500 (fd'0,(true,(false,(false,(true,(false,true))))))))))))))))))))))))) => 6501 CVT_L_S 6502 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6503 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6504 | (true, 6505 (false, 6506 (false, 6507 (false, 6508 (true, 6509 (false, 6510 (false, 6511 (false, 6512 (false, 6513 (false, 6514 (fs'4, 6515 (fs'3, 6516 (fs'2, 6517 (fs'1, 6518 (fs'0, 6519 (fd'4, 6520 (fd'3, 6521 (fd'2, 6522 (fd'1, 6523 (fd'0,(true,(false,(false,(true,(false,true))))))))))))))))))))))))) => 6524 CVT_L_D 6525 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6526 BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) 6527 | _ => UnknownFPInstruction); 6528 6529fun LDC1Decode (base,(offset,ft)) = COP1(LDC1(base,(offset,ft))); 6530 6531fun LWC1Decode (base,(offset,ft)) = COP1(LWC1(base,(offset,ft))); 6532 6533fun SDC1Decode (base,(offset,ft)) = COP1(SDC1(base,(offset,ft))); 6534 6535fun SWC1Decode (base,(offset,ft)) = COP1(SWC1(base,(offset,ft))); 6536 6537fun MOVCIDecode (rs,(rt,rd)) = 6538 case boolify'5 rt of 6539 (cc'2,(cc'1,(cc'0,(false,false)))) => 6540 COP1(MOVF(rd,(rs,BitsN.fromBitstring([cc'2,cc'1,cc'0],3)))) 6541 | (cc'2,(cc'1,(cc'0,(false,true)))) => 6542 COP1(MOVT(rd,(rs,BitsN.fromBitstring([cc'2,cc'1,cc'0],3)))) 6543 | _ => ReservedInstruction; 6544 6545fun COP3Decode v = 6546 COP1 6547 (case boolify'26 v of 6548 (base'4, 6549 (base'3, 6550 (base'2, 6551 (base'1, 6552 (base'0, 6553 (index'4, 6554 (index'3, 6555 (index'2, 6556 (index'1, 6557 (index'0, 6558 (false, 6559 (false, 6560 (false, 6561 (false, 6562 (false, 6563 (fd'4, 6564 (fd'3, 6565 (fd'2, 6566 (fd'1, 6567 (fd'0, 6568 (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => 6569 LWXC1 6570 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6571 (BitsN.fromBitstring 6572 ([index'4,index'3,index'2,index'1,index'0],5), 6573 BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5))) 6574 | (base'4, 6575 (base'3, 6576 (base'2, 6577 (base'1, 6578 (base'0, 6579 (index'4, 6580 (index'3, 6581 (index'2, 6582 (index'1, 6583 (index'0, 6584 (false, 6585 (false, 6586 (false, 6587 (false, 6588 (false, 6589 (fd'4, 6590 (fd'3, 6591 (fd'2, 6592 (fd'1, 6593 (fd'0, 6594 (false,(false,(false,(false,(false,true))))))))))))))))))))))))) => 6595 LDXC1 6596 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6597 (BitsN.fromBitstring 6598 ([index'4,index'3,index'2,index'1,index'0],5), 6599 BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5))) 6600 | (base'4, 6601 (base'3, 6602 (base'2, 6603 (base'1, 6604 (base'0, 6605 (index'4, 6606 (index'3, 6607 (index'2, 6608 (index'1, 6609 (index'0, 6610 (fs'4, 6611 (fs'3, 6612 (fs'2, 6613 (fs'1, 6614 (fs'0, 6615 (false, 6616 (false, 6617 (false, 6618 (false, 6619 (false, 6620 (false,(false,(true,(false,(false,false))))))))))))))))))))))))) => 6621 SWXC1 6622 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6623 (BitsN.fromBitstring 6624 ([index'4,index'3,index'2,index'1,index'0],5), 6625 BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5))) 6626 | (base'4, 6627 (base'3, 6628 (base'2, 6629 (base'1, 6630 (base'0, 6631 (index'4, 6632 (index'3, 6633 (index'2, 6634 (index'1, 6635 (index'0, 6636 (fs'4, 6637 (fs'3, 6638 (fs'2, 6639 (fs'1, 6640 (fs'0, 6641 (false, 6642 (false, 6643 (false, 6644 (false, 6645 (false, 6646 (false,(false,(true,(false,(false,true))))))))))))))))))))))))) => 6647 SDXC1 6648 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6649 (BitsN.fromBitstring 6650 ([index'4,index'3,index'2,index'1,index'0],5), 6651 BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5))) 6652 | (fr'4, 6653 (fr'3, 6654 (fr'2, 6655 (fr'1, 6656 (fr'0, 6657 (ft'4, 6658 (ft'3, 6659 (ft'2, 6660 (ft'1, 6661 (ft'0, 6662 (fs'4, 6663 (fs'3, 6664 (fs'2, 6665 (fs'1, 6666 (fs'0, 6667 (fd'4, 6668 (fd'3, 6669 (fd'2, 6670 (fd'1, 6671 (fd'0, 6672 (true,(false,(false,(false,(false,false))))))))))))))))))))))))) => 6673 MADD_S 6674 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6675 (BitsN.fromBitstring([fr'4,fr'3,fr'2,fr'1,fr'0],5), 6676 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6677 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5)))) 6678 | (fr'4, 6679 (fr'3, 6680 (fr'2, 6681 (fr'1, 6682 (fr'0, 6683 (ft'4, 6684 (ft'3, 6685 (ft'2, 6686 (ft'1, 6687 (ft'0, 6688 (fs'4, 6689 (fs'3, 6690 (fs'2, 6691 (fs'1, 6692 (fs'0, 6693 (fd'4, 6694 (fd'3, 6695 (fd'2, 6696 (fd'1, 6697 (fd'0,(true,(false,(false,(false,(false,true))))))))))))))))))))))))) => 6698 MADD_D 6699 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6700 (BitsN.fromBitstring([fr'4,fr'3,fr'2,fr'1,fr'0],5), 6701 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6702 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5)))) 6703 | (fr'4, 6704 (fr'3, 6705 (fr'2, 6706 (fr'1, 6707 (fr'0, 6708 (ft'4, 6709 (ft'3, 6710 (ft'2, 6711 (ft'1, 6712 (ft'0, 6713 (fs'4, 6714 (fs'3, 6715 (fs'2, 6716 (fs'1, 6717 (fs'0, 6718 (fd'4, 6719 (fd'3, 6720 (fd'2, 6721 (fd'1, 6722 (fd'0,(true,(false,(true,(false,(false,false))))))))))))))))))))))))) => 6723 MSUB_S 6724 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6725 (BitsN.fromBitstring([fr'4,fr'3,fr'2,fr'1,fr'0],5), 6726 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6727 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5)))) 6728 | (fr'4, 6729 (fr'3, 6730 (fr'2, 6731 (fr'1, 6732 (fr'0, 6733 (ft'4, 6734 (ft'3, 6735 (ft'2, 6736 (ft'1, 6737 (ft'0, 6738 (fs'4, 6739 (fs'3, 6740 (fs'2, 6741 (fs'1, 6742 (fs'0, 6743 (fd'4, 6744 (fd'3, 6745 (fd'2, 6746 (fd'1, 6747 (fd'0,(true,(false,(true,(false,(false,true))))))))))))))))))))))))) => 6748 MSUB_D 6749 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), 6750 (BitsN.fromBitstring([fr'4,fr'3,fr'2,fr'1,fr'0],5), 6751 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), 6752 BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5)))) 6753 | _ => UnknownFPInstruction); 6754 6755fun Decode w = 6756 case boolify'32 w of 6757 (false, 6758 (false, 6759 (false, 6760 (false, 6761 (false, 6762 (false, 6763 (rs'4, 6764 (rs'3, 6765 (rs'2, 6766 (rs'1, 6767 (rs'0, 6768 (rt'4, 6769 (rt'3, 6770 (rt'2, 6771 (rt'1, 6772 (rt'0, 6773 (rd'4, 6774 (rd'3, 6775 (rd'2, 6776 (rd'1, 6777 (rd'0, 6778 (false, 6779 (false, 6780 (false, 6781 (false, 6782 (false, 6783 (false,(false,(false,(false,(false,true))))))))))))))))))))))))))))))) => 6784 MOVCIDecode 6785 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 6786 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 6787 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5))) 6788 | (false, 6789 (false, 6790 (false, 6791 (false, 6792 (false, 6793 (false, 6794 (false, 6795 (false, 6796 (false, 6797 (false, 6798 (false, 6799 (rt'4, 6800 (rt'3, 6801 (rt'2, 6802 (rt'1, 6803 (rt'0, 6804 (rd'4, 6805 (rd'3, 6806 (rd'2, 6807 (rd'1, 6808 (rd'0, 6809 (imm5'4, 6810 (imm5'3, 6811 (imm5'2, 6812 (imm5'1, 6813 (imm5'0, 6814 (false,(false,(false,(false,(false,false))))))))))))))))))))))))))))))) => 6815 Shift 6816 (SLL(BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 6817 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 6818 BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) 6819 | (false, 6820 (false, 6821 (false, 6822 (false, 6823 (false, 6824 (false, 6825 (false, 6826 (false, 6827 (false, 6828 (false, 6829 (false, 6830 (rt'4, 6831 (rt'3, 6832 (rt'2, 6833 (rt'1, 6834 (rt'0, 6835 (rd'4, 6836 (rd'3, 6837 (rd'2, 6838 (rd'1, 6839 (rd'0, 6840 (imm5'4, 6841 (imm5'3, 6842 (imm5'2, 6843 (imm5'1, 6844 (imm5'0, 6845 (false,(false,(false,(false,(true,false))))))))))))))))))))))))))))))) => 6846 Shift 6847 (SRL(BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 6848 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 6849 BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) 6850 | (false, 6851 (false, 6852 (false, 6853 (false, 6854 (false, 6855 (false, 6856 (false, 6857 (false, 6858 (false, 6859 (false, 6860 (false, 6861 (rt'4, 6862 (rt'3, 6863 (rt'2, 6864 (rt'1, 6865 (rt'0, 6866 (rd'4, 6867 (rd'3, 6868 (rd'2, 6869 (rd'1, 6870 (rd'0, 6871 (imm5'4, 6872 (imm5'3, 6873 (imm5'2, 6874 (imm5'1, 6875 (imm5'0, 6876 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 6877 Shift 6878 (SRA(BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 6879 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 6880 BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) 6881 | (false, 6882 (false, 6883 (false, 6884 (false, 6885 (false, 6886 (false, 6887 (rs'4, 6888 (rs'3, 6889 (rs'2, 6890 (rs'1, 6891 (rs'0, 6892 (rt'4, 6893 (rt'3, 6894 (rt'2, 6895 (rt'1, 6896 (rt'0, 6897 (rd'4, 6898 (rd'3, 6899 (rd'2, 6900 (rd'1, 6901 (rd'0, 6902 (false, 6903 (false, 6904 (false, 6905 (false, 6906 (false, 6907 (false,(false,(false,(true,(false,false))))))))))))))))))))))))))))))) => 6908 Shift 6909 (SLLV 6910 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 6911 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 6912 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 6913 | (false, 6914 (false, 6915 (false, 6916 (false, 6917 (false, 6918 (false, 6919 (rs'4, 6920 (rs'3, 6921 (rs'2, 6922 (rs'1, 6923 (rs'0, 6924 (rt'4, 6925 (rt'3, 6926 (rt'2, 6927 (rt'1, 6928 (rt'0, 6929 (rd'4, 6930 (rd'3, 6931 (rd'2, 6932 (rd'1, 6933 (rd'0, 6934 (false, 6935 (false, 6936 (false, 6937 (false, 6938 (false, 6939 (false,(false,(false,(true,(true,false))))))))))))))))))))))))))))))) => 6940 Shift 6941 (SRLV 6942 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 6943 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 6944 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 6945 | (false, 6946 (false, 6947 (false, 6948 (false, 6949 (false, 6950 (false, 6951 (rs'4, 6952 (rs'3, 6953 (rs'2, 6954 (rs'1, 6955 (rs'0, 6956 (rt'4, 6957 (rt'3, 6958 (rt'2, 6959 (rt'1, 6960 (rt'0, 6961 (rd'4, 6962 (rd'3, 6963 (rd'2, 6964 (rd'1, 6965 (rd'0, 6966 (false, 6967 (false, 6968 (false, 6969 (false, 6970 (false, 6971 (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => 6972 Shift 6973 (SRAV 6974 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 6975 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 6976 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 6977 | (false, 6978 (false, 6979 (false, 6980 (false, 6981 (false, 6982 (false, 6983 (rs'4, 6984 (rs'3, 6985 (rs'2, 6986 (rs'1, 6987 (rs'0, 6988 (false, 6989 (false, 6990 (false, 6991 (false, 6992 (false, 6993 (false, 6994 (false, 6995 (false, 6996 (false, 6997 (false, 6998 (hint'4, 6999 (hint'3, 7000 (hint'2, 7001 (hint'1, 7002 (hint'0, 7003 (false,(false,(true,(false,(false,false))))))))))))))))))))))))))))))) => 7004 Branch(JR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) 7005 | (false, 7006 (false, 7007 (false, 7008 (false, 7009 (false, 7010 (false, 7011 (rs'4, 7012 (rs'3, 7013 (rs'2, 7014 (rs'1, 7015 (rs'0, 7016 (false, 7017 (false, 7018 (false, 7019 (false, 7020 (false, 7021 (rd'4, 7022 (rd'3, 7023 (rd'2, 7024 (rd'1, 7025 (rd'0, 7026 (hint'4, 7027 (hint'3, 7028 (hint'2, 7029 (hint'1, 7030 (hint'0, 7031 (false,(false,(true,(false,(false,true))))))))))))))))))))))))))))))) => 7032 Branch 7033 (JALR 7034 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7035 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5))) 7036 | (false, 7037 (false, 7038 (false, 7039 (false, 7040 (false, 7041 (false, 7042 (rs'4, 7043 (rs'3, 7044 (rs'2, 7045 (rs'1, 7046 (rs'0, 7047 (rt'4, 7048 (rt'3, 7049 (rt'2, 7050 (rt'1, 7051 (rt'0, 7052 (rd'4, 7053 (rd'3, 7054 (rd'2, 7055 (rd'1, 7056 (rd'0, 7057 (false, 7058 (false, 7059 (false, 7060 (false, 7061 (false, 7062 (false,(false,(true,(false,(true,false))))))))))))))))))))))))))))))) => 7063 ArithR 7064 (MOVZ 7065 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7066 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7067 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7068 | (false, 7069 (false, 7070 (false, 7071 (false, 7072 (false, 7073 (false, 7074 (rs'4, 7075 (rs'3, 7076 (rs'2, 7077 (rs'1, 7078 (rs'0, 7079 (rt'4, 7080 (rt'3, 7081 (rt'2, 7082 (rt'1, 7083 (rt'0, 7084 (rd'4, 7085 (rd'3, 7086 (rd'2, 7087 (rd'1, 7088 (rd'0, 7089 (false, 7090 (false, 7091 (false, 7092 (false, 7093 (false, 7094 (false,(false,(true,(false,(true,true))))))))))))))))))))))))))))))) => 7095 ArithR 7096 (MOVN 7097 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7098 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7099 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7100 | (false, 7101 (false, 7102 (false, 7103 (false, 7104 (false, 7105 (false, 7106 (false, 7107 (false, 7108 (false, 7109 (false, 7110 (false, 7111 (code'14, 7112 (code'13, 7113 (code'12, 7114 (code'11, 7115 (code'10, 7116 (code'9, 7117 (code'8, 7118 (code'7, 7119 (code'6, 7120 (code'5, 7121 (code'4, 7122 (code'3, 7123 (code'2, 7124 (code'1, 7125 (code'0, 7126 (false,(false,(true,(true,(false,false))))))))))))))))))))))))))))))) => 7127 SYSCALL 7128 | (false, 7129 (false, 7130 (false, 7131 (false, 7132 (false, 7133 (false, 7134 (false, 7135 (false, 7136 (false, 7137 (false, 7138 (false, 7139 (code'14, 7140 (code'13, 7141 (code'12, 7142 (code'11, 7143 (code'10, 7144 (code'9, 7145 (code'8, 7146 (code'7, 7147 (code'6, 7148 (code'5, 7149 (code'4, 7150 (code'3, 7151 (code'2, 7152 (code'1, 7153 (code'0, 7154 (false,(false,(true,(true,(false,true))))))))))))))))))))))))))))))) => 7155 BREAK 7156 | (false, 7157 (false, 7158 (false, 7159 (false, 7160 (false, 7161 (false, 7162 (false, 7163 (false, 7164 (false, 7165 (false, 7166 (false, 7167 (false, 7168 (false, 7169 (false, 7170 (false, 7171 (false, 7172 (false, 7173 (false, 7174 (false, 7175 (false, 7176 (false, 7177 (imm5'4, 7178 (imm5'3, 7179 (imm5'2, 7180 (imm5'1, 7181 (imm5'0, 7182 (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 7183 SYNC(BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)) 7184 | (false, 7185 (false, 7186 (false, 7187 (false, 7188 (false, 7189 (false, 7190 (false, 7191 (false, 7192 (false, 7193 (false, 7194 (false, 7195 (false, 7196 (false, 7197 (false, 7198 (false, 7199 (false, 7200 (rd'4, 7201 (rd'3, 7202 (rd'2, 7203 (rd'1, 7204 (rd'0, 7205 (false, 7206 (false, 7207 (false, 7208 (false, 7209 (false, 7210 (false,(true,(false,(false,(false,false))))))))))))))))))))))))))))))) => 7211 MultDiv(MFHI(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5))) 7212 | (false, 7213 (false, 7214 (false, 7215 (false, 7216 (false, 7217 (false, 7218 (rs'4, 7219 (rs'3, 7220 (rs'2, 7221 (rs'1, 7222 (rs'0, 7223 (false, 7224 (false, 7225 (false, 7226 (false, 7227 (false, 7228 (false, 7229 (false, 7230 (false, 7231 (false, 7232 (false, 7233 (false, 7234 (false, 7235 (false, 7236 (false, 7237 (false, 7238 (false,(true,(false,(false,(false,true))))))))))))))))))))))))))))))) => 7239 MultDiv(MTHI(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) 7240 | (false, 7241 (false, 7242 (false, 7243 (false, 7244 (false, 7245 (false, 7246 (false, 7247 (false, 7248 (false, 7249 (false, 7250 (false, 7251 (false, 7252 (false, 7253 (false, 7254 (false, 7255 (false, 7256 (rd'4, 7257 (rd'3, 7258 (rd'2, 7259 (rd'1, 7260 (rd'0, 7261 (false, 7262 (false, 7263 (false, 7264 (false, 7265 (false, 7266 (false,(true,(false,(false,(true,false))))))))))))))))))))))))))))))) => 7267 MultDiv(MFLO(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5))) 7268 | (false, 7269 (false, 7270 (false, 7271 (false, 7272 (false, 7273 (false, 7274 (rs'4, 7275 (rs'3, 7276 (rs'2, 7277 (rs'1, 7278 (rs'0, 7279 (false, 7280 (false, 7281 (false, 7282 (false, 7283 (false, 7284 (false, 7285 (false, 7286 (false, 7287 (false, 7288 (false, 7289 (false, 7290 (false, 7291 (false, 7292 (false, 7293 (false, 7294 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 7295 MultDiv(MTLO(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) 7296 | (false, 7297 (false, 7298 (false, 7299 (false, 7300 (false, 7301 (false, 7302 (rs'4, 7303 (rs'3, 7304 (rs'2, 7305 (rs'1, 7306 (rs'0, 7307 (rt'4, 7308 (rt'3, 7309 (rt'2, 7310 (rt'1, 7311 (rt'0, 7312 (rd'4, 7313 (rd'3, 7314 (rd'2, 7315 (rd'1, 7316 (rd'0, 7317 (false, 7318 (false, 7319 (false, 7320 (false, 7321 (false, 7322 (false,(true,(false,(true,(false,false))))))))))))))))))))))))))))))) => 7323 Shift 7324 (DSLLV 7325 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7326 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7327 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7328 | (false, 7329 (false, 7330 (false, 7331 (false, 7332 (false, 7333 (false, 7334 (rs'4, 7335 (rs'3, 7336 (rs'2, 7337 (rs'1, 7338 (rs'0, 7339 (rt'4, 7340 (rt'3, 7341 (rt'2, 7342 (rt'1, 7343 (rt'0, 7344 (rd'4, 7345 (rd'3, 7346 (rd'2, 7347 (rd'1, 7348 (rd'0, 7349 (false, 7350 (false, 7351 (false, 7352 (false, 7353 (false, 7354 (false,(true,(false,(true,(true,false))))))))))))))))))))))))))))))) => 7355 Shift 7356 (DSRLV 7357 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7358 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7359 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7360 | (false, 7361 (false, 7362 (false, 7363 (false, 7364 (false, 7365 (false, 7366 (rs'4, 7367 (rs'3, 7368 (rs'2, 7369 (rs'1, 7370 (rs'0, 7371 (rt'4, 7372 (rt'3, 7373 (rt'2, 7374 (rt'1, 7375 (rt'0, 7376 (rd'4, 7377 (rd'3, 7378 (rd'2, 7379 (rd'1, 7380 (rd'0, 7381 (false, 7382 (false, 7383 (false, 7384 (false, 7385 (false, 7386 (false,(true,(false,(true,(true,true))))))))))))))))))))))))))))))) => 7387 Shift 7388 (DSRAV 7389 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7390 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7391 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7392 | (false, 7393 (false, 7394 (false, 7395 (false, 7396 (false, 7397 (false, 7398 (rs'4, 7399 (rs'3, 7400 (rs'2, 7401 (rs'1, 7402 (rs'0, 7403 (rt'4, 7404 (rt'3, 7405 (rt'2, 7406 (rt'1, 7407 (rt'0, 7408 (false, 7409 (false, 7410 (false, 7411 (false, 7412 (false, 7413 (false, 7414 (false, 7415 (false, 7416 (false, 7417 (false, 7418 (false,(true,(true,(false,(false,false))))))))))))))))))))))))))))))) => 7419 MultDiv 7420 (MULT 7421 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7422 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 7423 | (false, 7424 (false, 7425 (false, 7426 (false, 7427 (false, 7428 (false, 7429 (rs'4, 7430 (rs'3, 7431 (rs'2, 7432 (rs'1, 7433 (rs'0, 7434 (rt'4, 7435 (rt'3, 7436 (rt'2, 7437 (rt'1, 7438 (rt'0, 7439 (false, 7440 (false, 7441 (false, 7442 (false, 7443 (false, 7444 (false, 7445 (false, 7446 (false, 7447 (false, 7448 (false, 7449 (false,(true,(true,(false,(false,true))))))))))))))))))))))))))))))) => 7450 MultDiv 7451 (MULTU 7452 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7453 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 7454 | (false, 7455 (false, 7456 (false, 7457 (false, 7458 (false, 7459 (false, 7460 (rs'4, 7461 (rs'3, 7462 (rs'2, 7463 (rs'1, 7464 (rs'0, 7465 (rt'4, 7466 (rt'3, 7467 (rt'2, 7468 (rt'1, 7469 (rt'0, 7470 (false, 7471 (false, 7472 (false, 7473 (false, 7474 (false, 7475 (false, 7476 (false, 7477 (false, 7478 (false, 7479 (false, 7480 (false,(true,(true,(false,(true,false))))))))))))))))))))))))))))))) => 7481 MultDiv 7482 (DIV(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7483 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 7484 | (false, 7485 (false, 7486 (false, 7487 (false, 7488 (false, 7489 (false, 7490 (rs'4, 7491 (rs'3, 7492 (rs'2, 7493 (rs'1, 7494 (rs'0, 7495 (rt'4, 7496 (rt'3, 7497 (rt'2, 7498 (rt'1, 7499 (rt'0, 7500 (false, 7501 (false, 7502 (false, 7503 (false, 7504 (false, 7505 (false, 7506 (false, 7507 (false, 7508 (false, 7509 (false, 7510 (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 7511 MultDiv 7512 (DIVU 7513 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7514 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 7515 | (false, 7516 (false, 7517 (false, 7518 (false, 7519 (false, 7520 (false, 7521 (rs'4, 7522 (rs'3, 7523 (rs'2, 7524 (rs'1, 7525 (rs'0, 7526 (rt'4, 7527 (rt'3, 7528 (rt'2, 7529 (rt'1, 7530 (rt'0, 7531 (false, 7532 (false, 7533 (false, 7534 (false, 7535 (false, 7536 (false, 7537 (false, 7538 (false, 7539 (false, 7540 (false, 7541 (false,(true,(true,(true,(false,false))))))))))))))))))))))))))))))) => 7542 MultDiv 7543 (DMULT 7544 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7545 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 7546 | (false, 7547 (false, 7548 (false, 7549 (false, 7550 (false, 7551 (false, 7552 (rs'4, 7553 (rs'3, 7554 (rs'2, 7555 (rs'1, 7556 (rs'0, 7557 (rt'4, 7558 (rt'3, 7559 (rt'2, 7560 (rt'1, 7561 (rt'0, 7562 (false, 7563 (false, 7564 (false, 7565 (false, 7566 (false, 7567 (false, 7568 (false, 7569 (false, 7570 (false, 7571 (false, 7572 (false,(true,(true,(true,(false,true))))))))))))))))))))))))))))))) => 7573 MultDiv 7574 (DMULTU 7575 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7576 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 7577 | (false, 7578 (false, 7579 (false, 7580 (false, 7581 (false, 7582 (false, 7583 (rs'4, 7584 (rs'3, 7585 (rs'2, 7586 (rs'1, 7587 (rs'0, 7588 (rt'4, 7589 (rt'3, 7590 (rt'2, 7591 (rt'1, 7592 (rt'0, 7593 (false, 7594 (false, 7595 (false, 7596 (false, 7597 (false, 7598 (false, 7599 (false, 7600 (false, 7601 (false, 7602 (false, 7603 (false,(true,(true,(true,(true,false))))))))))))))))))))))))))))))) => 7604 MultDiv 7605 (DDIV 7606 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7607 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 7608 | (false, 7609 (false, 7610 (false, 7611 (false, 7612 (false, 7613 (false, 7614 (rs'4, 7615 (rs'3, 7616 (rs'2, 7617 (rs'1, 7618 (rs'0, 7619 (rt'4, 7620 (rt'3, 7621 (rt'2, 7622 (rt'1, 7623 (rt'0, 7624 (false, 7625 (false, 7626 (false, 7627 (false, 7628 (false, 7629 (false, 7630 (false, 7631 (false, 7632 (false, 7633 (false, 7634 (false,(true,(true,(true,(true,true))))))))))))))))))))))))))))))) => 7635 MultDiv 7636 (DDIVU 7637 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7638 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 7639 | (false, 7640 (false, 7641 (false, 7642 (false, 7643 (false, 7644 (false, 7645 (rs'4, 7646 (rs'3, 7647 (rs'2, 7648 (rs'1, 7649 (rs'0, 7650 (rt'4, 7651 (rt'3, 7652 (rt'2, 7653 (rt'1, 7654 (rt'0, 7655 (rd'4, 7656 (rd'3, 7657 (rd'2, 7658 (rd'1, 7659 (rd'0, 7660 (false, 7661 (false, 7662 (false, 7663 (false, 7664 (false, 7665 (true,(false,(false,(false,(false,false))))))))))))))))))))))))))))))) => 7666 ArithR 7667 (ADD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7668 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7669 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7670 | (false, 7671 (false, 7672 (false, 7673 (false, 7674 (false, 7675 (false, 7676 (rs'4, 7677 (rs'3, 7678 (rs'2, 7679 (rs'1, 7680 (rs'0, 7681 (rt'4, 7682 (rt'3, 7683 (rt'2, 7684 (rt'1, 7685 (rt'0, 7686 (rd'4, 7687 (rd'3, 7688 (rd'2, 7689 (rd'1, 7690 (rd'0, 7691 (false, 7692 (false, 7693 (false, 7694 (false, 7695 (false, 7696 (true,(false,(false,(false,(false,true))))))))))))))))))))))))))))))) => 7697 ArithR 7698 (ADDU 7699 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7700 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7701 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7702 | (false, 7703 (false, 7704 (false, 7705 (false, 7706 (false, 7707 (false, 7708 (rs'4, 7709 (rs'3, 7710 (rs'2, 7711 (rs'1, 7712 (rs'0, 7713 (rt'4, 7714 (rt'3, 7715 (rt'2, 7716 (rt'1, 7717 (rt'0, 7718 (rd'4, 7719 (rd'3, 7720 (rd'2, 7721 (rd'1, 7722 (rd'0, 7723 (false, 7724 (false, 7725 (false, 7726 (false, 7727 (false, 7728 (true,(false,(false,(false,(true,false))))))))))))))))))))))))))))))) => 7729 ArithR 7730 (SUB(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7731 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7732 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7733 | (false, 7734 (false, 7735 (false, 7736 (false, 7737 (false, 7738 (false, 7739 (rs'4, 7740 (rs'3, 7741 (rs'2, 7742 (rs'1, 7743 (rs'0, 7744 (rt'4, 7745 (rt'3, 7746 (rt'2, 7747 (rt'1, 7748 (rt'0, 7749 (rd'4, 7750 (rd'3, 7751 (rd'2, 7752 (rd'1, 7753 (rd'0, 7754 (false, 7755 (false, 7756 (false, 7757 (false, 7758 (false, 7759 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 7760 ArithR 7761 (SUBU 7762 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7763 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7764 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7765 | (false, 7766 (false, 7767 (false, 7768 (false, 7769 (false, 7770 (false, 7771 (rs'4, 7772 (rs'3, 7773 (rs'2, 7774 (rs'1, 7775 (rs'0, 7776 (rt'4, 7777 (rt'3, 7778 (rt'2, 7779 (rt'1, 7780 (rt'0, 7781 (rd'4, 7782 (rd'3, 7783 (rd'2, 7784 (rd'1, 7785 (rd'0, 7786 (false, 7787 (false, 7788 (false, 7789 (false, 7790 (false, 7791 (true,(false,(false,(true,(false,false))))))))))))))))))))))))))))))) => 7792 ArithR 7793 (AND(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7794 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7795 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7796 | (false, 7797 (false, 7798 (false, 7799 (false, 7800 (false, 7801 (false, 7802 (rs'4, 7803 (rs'3, 7804 (rs'2, 7805 (rs'1, 7806 (rs'0, 7807 (rt'4, 7808 (rt'3, 7809 (rt'2, 7810 (rt'1, 7811 (rt'0, 7812 (rd'4, 7813 (rd'3, 7814 (rd'2, 7815 (rd'1, 7816 (rd'0, 7817 (false, 7818 (false, 7819 (false, 7820 (false, 7821 (false, 7822 (true,(false,(false,(true,(false,true))))))))))))))))))))))))))))))) => 7823 ArithR 7824 (OR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7825 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7826 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7827 | (false, 7828 (false, 7829 (false, 7830 (false, 7831 (false, 7832 (false, 7833 (rs'4, 7834 (rs'3, 7835 (rs'2, 7836 (rs'1, 7837 (rs'0, 7838 (rt'4, 7839 (rt'3, 7840 (rt'2, 7841 (rt'1, 7842 (rt'0, 7843 (rd'4, 7844 (rd'3, 7845 (rd'2, 7846 (rd'1, 7847 (rd'0, 7848 (false, 7849 (false, 7850 (false, 7851 (false, 7852 (false, 7853 (true,(false,(false,(true,(true,false))))))))))))))))))))))))))))))) => 7854 ArithR 7855 (XOR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7856 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7857 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7858 | (false, 7859 (false, 7860 (false, 7861 (false, 7862 (false, 7863 (false, 7864 (rs'4, 7865 (rs'3, 7866 (rs'2, 7867 (rs'1, 7868 (rs'0, 7869 (rt'4, 7870 (rt'3, 7871 (rt'2, 7872 (rt'1, 7873 (rt'0, 7874 (rd'4, 7875 (rd'3, 7876 (rd'2, 7877 (rd'1, 7878 (rd'0, 7879 (false, 7880 (false, 7881 (false, 7882 (false, 7883 (false, 7884 (true,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => 7885 ArithR 7886 (NOR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7887 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7888 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7889 | (false, 7890 (false, 7891 (false, 7892 (false, 7893 (false, 7894 (false, 7895 (rs'4, 7896 (rs'3, 7897 (rs'2, 7898 (rs'1, 7899 (rs'0, 7900 (rt'4, 7901 (rt'3, 7902 (rt'2, 7903 (rt'1, 7904 (rt'0, 7905 (rd'4, 7906 (rd'3, 7907 (rd'2, 7908 (rd'1, 7909 (rd'0, 7910 (false, 7911 (false, 7912 (false, 7913 (false, 7914 (false, 7915 (true,(false,(true,(false,(true,false))))))))))))))))))))))))))))))) => 7916 ArithR 7917 (SLT(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7918 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7919 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7920 | (false, 7921 (false, 7922 (false, 7923 (false, 7924 (false, 7925 (false, 7926 (rs'4, 7927 (rs'3, 7928 (rs'2, 7929 (rs'1, 7930 (rs'0, 7931 (rt'4, 7932 (rt'3, 7933 (rt'2, 7934 (rt'1, 7935 (rt'0, 7936 (rd'4, 7937 (rd'3, 7938 (rd'2, 7939 (rd'1, 7940 (rd'0, 7941 (false, 7942 (false, 7943 (false, 7944 (false, 7945 (false, 7946 (true,(false,(true,(false,(true,true))))))))))))))))))))))))))))))) => 7947 ArithR 7948 (SLTU 7949 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7950 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7951 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7952 | (false, 7953 (false, 7954 (false, 7955 (false, 7956 (false, 7957 (false, 7958 (rs'4, 7959 (rs'3, 7960 (rs'2, 7961 (rs'1, 7962 (rs'0, 7963 (rt'4, 7964 (rt'3, 7965 (rt'2, 7966 (rt'1, 7967 (rt'0, 7968 (rd'4, 7969 (rd'3, 7970 (rd'2, 7971 (rd'1, 7972 (rd'0, 7973 (false, 7974 (false, 7975 (false, 7976 (false, 7977 (false, 7978 (true,(false,(true,(true,(false,false))))))))))))))))))))))))))))))) => 7979 ArithR 7980 (DADD 7981 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 7982 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 7983 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 7984 | (false, 7985 (false, 7986 (false, 7987 (false, 7988 (false, 7989 (false, 7990 (rs'4, 7991 (rs'3, 7992 (rs'2, 7993 (rs'1, 7994 (rs'0, 7995 (rt'4, 7996 (rt'3, 7997 (rt'2, 7998 (rt'1, 7999 (rt'0, 8000 (rd'4, 8001 (rd'3, 8002 (rd'2, 8003 (rd'1, 8004 (rd'0, 8005 (false, 8006 (false, 8007 (false, 8008 (false, 8009 (false, 8010 (true,(false,(true,(true,(false,true))))))))))))))))))))))))))))))) => 8011 ArithR 8012 (DADDU 8013 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8014 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 8015 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 8016 | (false, 8017 (false, 8018 (false, 8019 (false, 8020 (false, 8021 (false, 8022 (rs'4, 8023 (rs'3, 8024 (rs'2, 8025 (rs'1, 8026 (rs'0, 8027 (rt'4, 8028 (rt'3, 8029 (rt'2, 8030 (rt'1, 8031 (rt'0, 8032 (rd'4, 8033 (rd'3, 8034 (rd'2, 8035 (rd'1, 8036 (rd'0, 8037 (false, 8038 (false, 8039 (false, 8040 (false, 8041 (false, 8042 (true,(false,(true,(true,(true,false))))))))))))))))))))))))))))))) => 8043 ArithR 8044 (DSUB 8045 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8046 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 8047 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 8048 | (false, 8049 (false, 8050 (false, 8051 (false, 8052 (false, 8053 (false, 8054 (rs'4, 8055 (rs'3, 8056 (rs'2, 8057 (rs'1, 8058 (rs'0, 8059 (rt'4, 8060 (rt'3, 8061 (rt'2, 8062 (rt'1, 8063 (rt'0, 8064 (rd'4, 8065 (rd'3, 8066 (rd'2, 8067 (rd'1, 8068 (rd'0, 8069 (false, 8070 (false, 8071 (false, 8072 (false, 8073 (false, 8074 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 8075 ArithR 8076 (DSUBU 8077 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8078 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 8079 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 8080 | (false, 8081 (false, 8082 (false, 8083 (false, 8084 (false, 8085 (false, 8086 (rs'4, 8087 (rs'3, 8088 (rs'2, 8089 (rs'1, 8090 (rs'0, 8091 (rt'4, 8092 (rt'3, 8093 (rt'2, 8094 (rt'1, 8095 (rt'0, 8096 (code'9, 8097 (code'8, 8098 (code'7, 8099 (code'6, 8100 (code'5, 8101 (code'4, 8102 (code'3, 8103 (code'2, 8104 (code'1, 8105 (code'0, 8106 (true,(true,(false,(false,(false,false))))))))))))))))))))))))))))))) => 8107 Trap 8108 (TGE(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8109 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 8110 | (false, 8111 (false, 8112 (false, 8113 (false, 8114 (false, 8115 (false, 8116 (rs'4, 8117 (rs'3, 8118 (rs'2, 8119 (rs'1, 8120 (rs'0, 8121 (rt'4, 8122 (rt'3, 8123 (rt'2, 8124 (rt'1, 8125 (rt'0, 8126 (code'9, 8127 (code'8, 8128 (code'7, 8129 (code'6, 8130 (code'5, 8131 (code'4, 8132 (code'3, 8133 (code'2, 8134 (code'1, 8135 (code'0, 8136 (true,(true,(false,(false,(false,true))))))))))))))))))))))))))))))) => 8137 Trap 8138 (TGEU 8139 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8140 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 8141 | (false, 8142 (false, 8143 (false, 8144 (false, 8145 (false, 8146 (false, 8147 (rs'4, 8148 (rs'3, 8149 (rs'2, 8150 (rs'1, 8151 (rs'0, 8152 (rt'4, 8153 (rt'3, 8154 (rt'2, 8155 (rt'1, 8156 (rt'0, 8157 (code'9, 8158 (code'8, 8159 (code'7, 8160 (code'6, 8161 (code'5, 8162 (code'4, 8163 (code'3, 8164 (code'2, 8165 (code'1, 8166 (code'0, 8167 (true,(true,(false,(false,(true,false))))))))))))))))))))))))))))))) => 8168 Trap 8169 (TLT(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8170 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 8171 | (false, 8172 (false, 8173 (false, 8174 (false, 8175 (false, 8176 (false, 8177 (rs'4, 8178 (rs'3, 8179 (rs'2, 8180 (rs'1, 8181 (rs'0, 8182 (rt'4, 8183 (rt'3, 8184 (rt'2, 8185 (rt'1, 8186 (rt'0, 8187 (code'9, 8188 (code'8, 8189 (code'7, 8190 (code'6, 8191 (code'5, 8192 (code'4, 8193 (code'3, 8194 (code'2, 8195 (code'1, 8196 (code'0, 8197 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8198 Trap 8199 (TLTU 8200 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8201 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 8202 | (false, 8203 (false, 8204 (false, 8205 (false, 8206 (false, 8207 (false, 8208 (rs'4, 8209 (rs'3, 8210 (rs'2, 8211 (rs'1, 8212 (rs'0, 8213 (rt'4, 8214 (rt'3, 8215 (rt'2, 8216 (rt'1, 8217 (rt'0, 8218 (code'9, 8219 (code'8, 8220 (code'7, 8221 (code'6, 8222 (code'5, 8223 (code'4, 8224 (code'3, 8225 (code'2, 8226 (code'1, 8227 (code'0, 8228 (true,(true,(false,(true,(false,false))))))))))))))))))))))))))))))) => 8229 Trap 8230 (TEQ(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8231 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 8232 | (false, 8233 (false, 8234 (false, 8235 (false, 8236 (false, 8237 (false, 8238 (rs'4, 8239 (rs'3, 8240 (rs'2, 8241 (rs'1, 8242 (rs'0, 8243 (rt'4, 8244 (rt'3, 8245 (rt'2, 8246 (rt'1, 8247 (rt'0, 8248 (code'9, 8249 (code'8, 8250 (code'7, 8251 (code'6, 8252 (code'5, 8253 (code'4, 8254 (code'3, 8255 (code'2, 8256 (code'1, 8257 (code'0, 8258 (true,(true,(false,(true,(true,false))))))))))))))))))))))))))))))) => 8259 Trap 8260 (TNE(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8261 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 8262 | (false, 8263 (false, 8264 (false, 8265 (false, 8266 (false, 8267 (false, 8268 (false, 8269 (false, 8270 (false, 8271 (false, 8272 (false, 8273 (rt'4, 8274 (rt'3, 8275 (rt'2, 8276 (rt'1, 8277 (rt'0, 8278 (rd'4, 8279 (rd'3, 8280 (rd'2, 8281 (rd'1, 8282 (rd'0, 8283 (imm5'4, 8284 (imm5'3, 8285 (imm5'2, 8286 (imm5'1, 8287 (imm5'0, 8288 (true,(true,(true,(false,(false,false))))))))))))))))))))))))))))))) => 8289 Shift 8290 (DSLL 8291 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 8292 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8293 BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) 8294 | (false, 8295 (false, 8296 (false, 8297 (false, 8298 (false, 8299 (false, 8300 (false, 8301 (false, 8302 (false, 8303 (false, 8304 (false, 8305 (rt'4, 8306 (rt'3, 8307 (rt'2, 8308 (rt'1, 8309 (rt'0, 8310 (rd'4, 8311 (rd'3, 8312 (rd'2, 8313 (rd'1, 8314 (rd'0, 8315 (imm5'4, 8316 (imm5'3, 8317 (imm5'2, 8318 (imm5'1, 8319 (imm5'0, 8320 (true,(true,(true,(false,(true,false))))))))))))))))))))))))))))))) => 8321 Shift 8322 (DSRL 8323 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 8324 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8325 BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) 8326 | (false, 8327 (false, 8328 (false, 8329 (false, 8330 (false, 8331 (false, 8332 (false, 8333 (false, 8334 (false, 8335 (false, 8336 (false, 8337 (rt'4, 8338 (rt'3, 8339 (rt'2, 8340 (rt'1, 8341 (rt'0, 8342 (rd'4, 8343 (rd'3, 8344 (rd'2, 8345 (rd'1, 8346 (rd'0, 8347 (imm5'4, 8348 (imm5'3, 8349 (imm5'2, 8350 (imm5'1, 8351 (imm5'0, 8352 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 8353 Shift 8354 (DSRA 8355 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 8356 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8357 BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) 8358 | (false, 8359 (false, 8360 (false, 8361 (false, 8362 (false, 8363 (false, 8364 (false, 8365 (false, 8366 (false, 8367 (false, 8368 (false, 8369 (rt'4, 8370 (rt'3, 8371 (rt'2, 8372 (rt'1, 8373 (rt'0, 8374 (rd'4, 8375 (rd'3, 8376 (rd'2, 8377 (rd'1, 8378 (rd'0, 8379 (imm5'4, 8380 (imm5'3, 8381 (imm5'2, 8382 (imm5'1, 8383 (imm5'0, 8384 (true,(true,(true,(true,(false,false))))))))))))))))))))))))))))))) => 8385 Shift 8386 (DSLL32 8387 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 8388 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8389 BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) 8390 | (false, 8391 (false, 8392 (false, 8393 (false, 8394 (false, 8395 (false, 8396 (false, 8397 (false, 8398 (false, 8399 (false, 8400 (false, 8401 (rt'4, 8402 (rt'3, 8403 (rt'2, 8404 (rt'1, 8405 (rt'0, 8406 (rd'4, 8407 (rd'3, 8408 (rd'2, 8409 (rd'1, 8410 (rd'0, 8411 (imm5'4, 8412 (imm5'3, 8413 (imm5'2, 8414 (imm5'1, 8415 (imm5'0, 8416 (true,(true,(true,(true,(true,false))))))))))))))))))))))))))))))) => 8417 Shift 8418 (DSRL32 8419 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 8420 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8421 BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) 8422 | (false, 8423 (false, 8424 (false, 8425 (false, 8426 (false, 8427 (false, 8428 (false, 8429 (false, 8430 (false, 8431 (false, 8432 (false, 8433 (rt'4, 8434 (rt'3, 8435 (rt'2, 8436 (rt'1, 8437 (rt'0, 8438 (rd'4, 8439 (rd'3, 8440 (rd'2, 8441 (rd'1, 8442 (rd'0, 8443 (imm5'4, 8444 (imm5'3, 8445 (imm5'2, 8446 (imm5'1, 8447 (imm5'0, 8448 (true,(true,(true,(true,(true,true))))))))))))))))))))))))))))))) => 8449 Shift 8450 (DSRA32 8451 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 8452 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8453 BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) 8454 | (false, 8455 (false, 8456 (false, 8457 (false, 8458 (false, 8459 (true, 8460 (rs'4, 8461 (rs'3, 8462 (rs'2, 8463 (rs'1, 8464 (rs'0, 8465 (false, 8466 (false, 8467 (false, 8468 (false, 8469 (false, 8470 (immediate'15, 8471 (immediate'14, 8472 (immediate'13, 8473 (immediate'12, 8474 (immediate'11, 8475 (immediate'10, 8476 (immediate'9, 8477 (immediate'8, 8478 (immediate'7, 8479 (immediate'6, 8480 (immediate'5, 8481 (immediate'4, 8482 (immediate'3, 8483 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8484 Branch 8485 (BLTZ 8486 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8487 BitsN.fromBitstring 8488 ([immediate'15,immediate'14,immediate'13,immediate'12, 8489 immediate'11,immediate'10,immediate'9,immediate'8, 8490 immediate'7,immediate'6,immediate'5,immediate'4, 8491 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8492 | (false, 8493 (false, 8494 (false, 8495 (false, 8496 (false, 8497 (true, 8498 (rs'4, 8499 (rs'3, 8500 (rs'2, 8501 (rs'1, 8502 (rs'0, 8503 (false, 8504 (false, 8505 (false, 8506 (false, 8507 (true, 8508 (immediate'15, 8509 (immediate'14, 8510 (immediate'13, 8511 (immediate'12, 8512 (immediate'11, 8513 (immediate'10, 8514 (immediate'9, 8515 (immediate'8, 8516 (immediate'7, 8517 (immediate'6, 8518 (immediate'5, 8519 (immediate'4, 8520 (immediate'3, 8521 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8522 Branch 8523 (BGEZ 8524 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8525 BitsN.fromBitstring 8526 ([immediate'15,immediate'14,immediate'13,immediate'12, 8527 immediate'11,immediate'10,immediate'9,immediate'8, 8528 immediate'7,immediate'6,immediate'5,immediate'4, 8529 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8530 | (false, 8531 (false, 8532 (false, 8533 (false, 8534 (false, 8535 (true, 8536 (rs'4, 8537 (rs'3, 8538 (rs'2, 8539 (rs'1, 8540 (rs'0, 8541 (false, 8542 (false, 8543 (false, 8544 (true, 8545 (false, 8546 (immediate'15, 8547 (immediate'14, 8548 (immediate'13, 8549 (immediate'12, 8550 (immediate'11, 8551 (immediate'10, 8552 (immediate'9, 8553 (immediate'8, 8554 (immediate'7, 8555 (immediate'6, 8556 (immediate'5, 8557 (immediate'4, 8558 (immediate'3, 8559 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8560 Branch 8561 (BLTZL 8562 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8563 BitsN.fromBitstring 8564 ([immediate'15,immediate'14,immediate'13,immediate'12, 8565 immediate'11,immediate'10,immediate'9,immediate'8, 8566 immediate'7,immediate'6,immediate'5,immediate'4, 8567 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8568 | (false, 8569 (false, 8570 (false, 8571 (false, 8572 (false, 8573 (true, 8574 (rs'4, 8575 (rs'3, 8576 (rs'2, 8577 (rs'1, 8578 (rs'0, 8579 (false, 8580 (false, 8581 (false, 8582 (true, 8583 (true, 8584 (immediate'15, 8585 (immediate'14, 8586 (immediate'13, 8587 (immediate'12, 8588 (immediate'11, 8589 (immediate'10, 8590 (immediate'9, 8591 (immediate'8, 8592 (immediate'7, 8593 (immediate'6, 8594 (immediate'5, 8595 (immediate'4, 8596 (immediate'3, 8597 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8598 Branch 8599 (BGEZL 8600 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8601 BitsN.fromBitstring 8602 ([immediate'15,immediate'14,immediate'13,immediate'12, 8603 immediate'11,immediate'10,immediate'9,immediate'8, 8604 immediate'7,immediate'6,immediate'5,immediate'4, 8605 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8606 | (false, 8607 (false, 8608 (false, 8609 (false, 8610 (false, 8611 (true, 8612 (rs'4, 8613 (rs'3, 8614 (rs'2, 8615 (rs'1, 8616 (rs'0, 8617 (false, 8618 (true, 8619 (false, 8620 (false, 8621 (false, 8622 (immediate'15, 8623 (immediate'14, 8624 (immediate'13, 8625 (immediate'12, 8626 (immediate'11, 8627 (immediate'10, 8628 (immediate'9, 8629 (immediate'8, 8630 (immediate'7, 8631 (immediate'6, 8632 (immediate'5, 8633 (immediate'4, 8634 (immediate'3, 8635 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8636 Trap 8637 (TGEI 8638 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8639 BitsN.fromBitstring 8640 ([immediate'15,immediate'14,immediate'13,immediate'12, 8641 immediate'11,immediate'10,immediate'9,immediate'8, 8642 immediate'7,immediate'6,immediate'5,immediate'4, 8643 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8644 | (false, 8645 (false, 8646 (false, 8647 (false, 8648 (false, 8649 (true, 8650 (rs'4, 8651 (rs'3, 8652 (rs'2, 8653 (rs'1, 8654 (rs'0, 8655 (false, 8656 (true, 8657 (false, 8658 (false, 8659 (true, 8660 (immediate'15, 8661 (immediate'14, 8662 (immediate'13, 8663 (immediate'12, 8664 (immediate'11, 8665 (immediate'10, 8666 (immediate'9, 8667 (immediate'8, 8668 (immediate'7, 8669 (immediate'6, 8670 (immediate'5, 8671 (immediate'4, 8672 (immediate'3, 8673 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8674 Trap 8675 (TGEIU 8676 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8677 BitsN.fromBitstring 8678 ([immediate'15,immediate'14,immediate'13,immediate'12, 8679 immediate'11,immediate'10,immediate'9,immediate'8, 8680 immediate'7,immediate'6,immediate'5,immediate'4, 8681 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8682 | (false, 8683 (false, 8684 (false, 8685 (false, 8686 (false, 8687 (true, 8688 (rs'4, 8689 (rs'3, 8690 (rs'2, 8691 (rs'1, 8692 (rs'0, 8693 (false, 8694 (true, 8695 (false, 8696 (true, 8697 (false, 8698 (immediate'15, 8699 (immediate'14, 8700 (immediate'13, 8701 (immediate'12, 8702 (immediate'11, 8703 (immediate'10, 8704 (immediate'9, 8705 (immediate'8, 8706 (immediate'7, 8707 (immediate'6, 8708 (immediate'5, 8709 (immediate'4, 8710 (immediate'3, 8711 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8712 Trap 8713 (TLTI 8714 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8715 BitsN.fromBitstring 8716 ([immediate'15,immediate'14,immediate'13,immediate'12, 8717 immediate'11,immediate'10,immediate'9,immediate'8, 8718 immediate'7,immediate'6,immediate'5,immediate'4, 8719 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8720 | (false, 8721 (false, 8722 (false, 8723 (false, 8724 (false, 8725 (true, 8726 (rs'4, 8727 (rs'3, 8728 (rs'2, 8729 (rs'1, 8730 (rs'0, 8731 (false, 8732 (true, 8733 (false, 8734 (true, 8735 (true, 8736 (immediate'15, 8737 (immediate'14, 8738 (immediate'13, 8739 (immediate'12, 8740 (immediate'11, 8741 (immediate'10, 8742 (immediate'9, 8743 (immediate'8, 8744 (immediate'7, 8745 (immediate'6, 8746 (immediate'5, 8747 (immediate'4, 8748 (immediate'3, 8749 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8750 Trap 8751 (TLTIU 8752 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8753 BitsN.fromBitstring 8754 ([immediate'15,immediate'14,immediate'13,immediate'12, 8755 immediate'11,immediate'10,immediate'9,immediate'8, 8756 immediate'7,immediate'6,immediate'5,immediate'4, 8757 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8758 | (false, 8759 (false, 8760 (false, 8761 (false, 8762 (false, 8763 (true, 8764 (rs'4, 8765 (rs'3, 8766 (rs'2, 8767 (rs'1, 8768 (rs'0, 8769 (false, 8770 (true, 8771 (true, 8772 (false, 8773 (false, 8774 (immediate'15, 8775 (immediate'14, 8776 (immediate'13, 8777 (immediate'12, 8778 (immediate'11, 8779 (immediate'10, 8780 (immediate'9, 8781 (immediate'8, 8782 (immediate'7, 8783 (immediate'6, 8784 (immediate'5, 8785 (immediate'4, 8786 (immediate'3, 8787 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8788 Trap 8789 (TEQI 8790 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8791 BitsN.fromBitstring 8792 ([immediate'15,immediate'14,immediate'13,immediate'12, 8793 immediate'11,immediate'10,immediate'9,immediate'8, 8794 immediate'7,immediate'6,immediate'5,immediate'4, 8795 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8796 | (false, 8797 (false, 8798 (false, 8799 (false, 8800 (false, 8801 (true, 8802 (rs'4, 8803 (rs'3, 8804 (rs'2, 8805 (rs'1, 8806 (rs'0, 8807 (false, 8808 (true, 8809 (true, 8810 (true, 8811 (false, 8812 (immediate'15, 8813 (immediate'14, 8814 (immediate'13, 8815 (immediate'12, 8816 (immediate'11, 8817 (immediate'10, 8818 (immediate'9, 8819 (immediate'8, 8820 (immediate'7, 8821 (immediate'6, 8822 (immediate'5, 8823 (immediate'4, 8824 (immediate'3, 8825 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8826 Trap 8827 (TNEI 8828 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8829 BitsN.fromBitstring 8830 ([immediate'15,immediate'14,immediate'13,immediate'12, 8831 immediate'11,immediate'10,immediate'9,immediate'8, 8832 immediate'7,immediate'6,immediate'5,immediate'4, 8833 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8834 | (false, 8835 (false, 8836 (false, 8837 (false, 8838 (false, 8839 (true, 8840 (true, 8841 (true, 8842 (true, 8843 (true, 8844 (true, 8845 (true, 8846 (false, 8847 (false, 8848 (_, 8849 (_, 8850 (immediate'15, 8851 (immediate'14, 8852 (immediate'13, 8853 (immediate'12, 8854 (immediate'11, 8855 (immediate'10, 8856 (immediate'9, 8857 (immediate'8, 8858 (immediate'7, 8859 (immediate'6, 8860 (immediate'5, 8861 (immediate'4, 8862 (immediate'3, 8863 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8864 Unpredictable 8865 | (false, 8866 (false, 8867 (false, 8868 (false, 8869 (false, 8870 (true, 8871 (rs'4, 8872 (rs'3, 8873 (rs'2, 8874 (rs'1, 8875 (rs'0, 8876 (true, 8877 (false, 8878 (false, 8879 (false, 8880 (false, 8881 (immediate'15, 8882 (immediate'14, 8883 (immediate'13, 8884 (immediate'12, 8885 (immediate'11, 8886 (immediate'10, 8887 (immediate'9, 8888 (immediate'8, 8889 (immediate'7, 8890 (immediate'6, 8891 (immediate'5, 8892 (immediate'4, 8893 (immediate'3, 8894 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8895 Branch 8896 (BLTZAL 8897 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8898 BitsN.fromBitstring 8899 ([immediate'15,immediate'14,immediate'13,immediate'12, 8900 immediate'11,immediate'10,immediate'9,immediate'8, 8901 immediate'7,immediate'6,immediate'5,immediate'4, 8902 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8903 | (false, 8904 (false, 8905 (false, 8906 (false, 8907 (false, 8908 (true, 8909 (rs'4, 8910 (rs'3, 8911 (rs'2, 8912 (rs'1, 8913 (rs'0, 8914 (true, 8915 (false, 8916 (false, 8917 (false, 8918 (true, 8919 (immediate'15, 8920 (immediate'14, 8921 (immediate'13, 8922 (immediate'12, 8923 (immediate'11, 8924 (immediate'10, 8925 (immediate'9, 8926 (immediate'8, 8927 (immediate'7, 8928 (immediate'6, 8929 (immediate'5, 8930 (immediate'4, 8931 (immediate'3, 8932 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8933 Branch 8934 (BGEZAL 8935 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8936 BitsN.fromBitstring 8937 ([immediate'15,immediate'14,immediate'13,immediate'12, 8938 immediate'11,immediate'10,immediate'9,immediate'8, 8939 immediate'7,immediate'6,immediate'5,immediate'4, 8940 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8941 | (false, 8942 (false, 8943 (false, 8944 (false, 8945 (false, 8946 (true, 8947 (rs'4, 8948 (rs'3, 8949 (rs'2, 8950 (rs'1, 8951 (rs'0, 8952 (true, 8953 (false, 8954 (false, 8955 (true, 8956 (false, 8957 (immediate'15, 8958 (immediate'14, 8959 (immediate'13, 8960 (immediate'12, 8961 (immediate'11, 8962 (immediate'10, 8963 (immediate'9, 8964 (immediate'8, 8965 (immediate'7, 8966 (immediate'6, 8967 (immediate'5, 8968 (immediate'4, 8969 (immediate'3, 8970 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 8971 Branch 8972 (BLTZALL 8973 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 8974 BitsN.fromBitstring 8975 ([immediate'15,immediate'14,immediate'13,immediate'12, 8976 immediate'11,immediate'10,immediate'9,immediate'8, 8977 immediate'7,immediate'6,immediate'5,immediate'4, 8978 immediate'3,immediate'2,immediate'1,immediate'0],16))) 8979 | (false, 8980 (false, 8981 (false, 8982 (false, 8983 (false, 8984 (true, 8985 (rs'4, 8986 (rs'3, 8987 (rs'2, 8988 (rs'1, 8989 (rs'0, 8990 (true, 8991 (false, 8992 (false, 8993 (true, 8994 (true, 8995 (immediate'15, 8996 (immediate'14, 8997 (immediate'13, 8998 (immediate'12, 8999 (immediate'11, 9000 (immediate'10, 9001 (immediate'9, 9002 (immediate'8, 9003 (immediate'7, 9004 (immediate'6, 9005 (immediate'5, 9006 (immediate'4, 9007 (immediate'3, 9008 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9009 Branch 9010 (BGEZALL 9011 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9012 BitsN.fromBitstring 9013 ([immediate'15,immediate'14,immediate'13,immediate'12, 9014 immediate'11,immediate'10,immediate'9,immediate'8, 9015 immediate'7,immediate'6,immediate'5,immediate'4, 9016 immediate'3,immediate'2,immediate'1,immediate'0],16))) 9017 | (false, 9018 (false, 9019 (false, 9020 (false, 9021 (true, 9022 (false, 9023 (immediate'25, 9024 (immediate'24, 9025 (immediate'23, 9026 (immediate'22, 9027 (immediate'21, 9028 (immediate'20, 9029 (immediate'19, 9030 (immediate'18, 9031 (immediate'17, 9032 (immediate'16, 9033 (immediate'15, 9034 (immediate'14, 9035 (immediate'13, 9036 (immediate'12, 9037 (immediate'11, 9038 (immediate'10, 9039 (immediate'9, 9040 (immediate'8, 9041 (immediate'7, 9042 (immediate'6, 9043 (immediate'5, 9044 (immediate'4, 9045 (immediate'3, 9046 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9047 Branch 9048 (J(BitsN.fromBitstring 9049 ([immediate'25,immediate'24,immediate'23,immediate'22, 9050 immediate'21,immediate'20,immediate'19,immediate'18, 9051 immediate'17,immediate'16,immediate'15,immediate'14, 9052 immediate'13,immediate'12,immediate'11,immediate'10, 9053 immediate'9,immediate'8,immediate'7,immediate'6,immediate'5, 9054 immediate'4,immediate'3,immediate'2,immediate'1,immediate'0], 9055 26))) 9056 | (false, 9057 (false, 9058 (false, 9059 (false, 9060 (true, 9061 (true, 9062 (immediate'25, 9063 (immediate'24, 9064 (immediate'23, 9065 (immediate'22, 9066 (immediate'21, 9067 (immediate'20, 9068 (immediate'19, 9069 (immediate'18, 9070 (immediate'17, 9071 (immediate'16, 9072 (immediate'15, 9073 (immediate'14, 9074 (immediate'13, 9075 (immediate'12, 9076 (immediate'11, 9077 (immediate'10, 9078 (immediate'9, 9079 (immediate'8, 9080 (immediate'7, 9081 (immediate'6, 9082 (immediate'5, 9083 (immediate'4, 9084 (immediate'3, 9085 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9086 Branch 9087 (JAL(BitsN.fromBitstring 9088 ([immediate'25,immediate'24,immediate'23,immediate'22, 9089 immediate'21,immediate'20,immediate'19,immediate'18, 9090 immediate'17,immediate'16,immediate'15,immediate'14, 9091 immediate'13,immediate'12,immediate'11,immediate'10, 9092 immediate'9,immediate'8,immediate'7,immediate'6, 9093 immediate'5,immediate'4,immediate'3,immediate'2, 9094 immediate'1,immediate'0],26))) 9095 | (false, 9096 (true, 9097 (false, 9098 (false, 9099 (false, 9100 (false, 9101 (true, 9102 (false, 9103 (false, 9104 (false, 9105 (false, 9106 (false, 9107 (false, 9108 (false, 9109 (false, 9110 (false, 9111 (false, 9112 (false, 9113 (false, 9114 (false, 9115 (false, 9116 (false, 9117 (false, 9118 (false, 9119 (false, 9120 (false, 9121 (false,(false,(false,(false,(false,true))))))))))))))))))))))))))))))) => 9122 TLBR 9123 | (false, 9124 (true, 9125 (false, 9126 (false, 9127 (false, 9128 (false, 9129 (true, 9130 (false, 9131 (false, 9132 (false, 9133 (false, 9134 (false, 9135 (false, 9136 (false, 9137 (false, 9138 (false, 9139 (false, 9140 (false, 9141 (false, 9142 (false, 9143 (false, 9144 (false, 9145 (false, 9146 (false, 9147 (false, 9148 (false, 9149 (false,(false,(false,(false,(true,false))))))))))))))))))))))))))))))) => 9150 TLBWI 9151 | (false, 9152 (true, 9153 (false, 9154 (false, 9155 (false, 9156 (false, 9157 (true, 9158 (false, 9159 (false, 9160 (false, 9161 (false, 9162 (false, 9163 (false, 9164 (false, 9165 (false, 9166 (false, 9167 (false, 9168 (false, 9169 (false, 9170 (false, 9171 (false, 9172 (false, 9173 (false, 9174 (false, 9175 (false, 9176 (false, 9177 (false,(false,(false,(true,(true,false))))))))))))))))))))))))))))))) => 9178 TLBWR 9179 | (false, 9180 (true, 9181 (false, 9182 (false, 9183 (false, 9184 (false, 9185 (true, 9186 (false, 9187 (false, 9188 (false, 9189 (false, 9190 (false, 9191 (false, 9192 (false, 9193 (false, 9194 (false, 9195 (false, 9196 (false, 9197 (false, 9198 (false, 9199 (false, 9200 (false, 9201 (false, 9202 (false, 9203 (false, 9204 (false, 9205 (false,(false,(true,(false,(false,false))))))))))))))))))))))))))))))) => 9206 TLBP 9207 | (false, 9208 (true, 9209 (false, 9210 (false, 9211 (false, 9212 (false, 9213 (true, 9214 (false, 9215 (false, 9216 (false, 9217 (false, 9218 (false, 9219 (false, 9220 (false, 9221 (false, 9222 (false, 9223 (false, 9224 (false, 9225 (false, 9226 (false, 9227 (false, 9228 (false, 9229 (false, 9230 (false, 9231 (false, 9232 (false, 9233 (false,(true,(true,(false,(false,false))))))))))))))))))))))))))))))) => 9234 ERET 9235 | (false, 9236 (true, 9237 (false, 9238 (false, 9239 (false, 9240 (false, 9241 (false, 9242 (false, 9243 (false, 9244 (false, 9245 (false, 9246 (rt'4, 9247 (rt'3, 9248 (rt'2, 9249 (rt'1, 9250 (rt'0, 9251 (rd'4, 9252 (rd'3, 9253 (rd'2, 9254 (rd'1, 9255 (rd'0, 9256 (false, 9257 (false, 9258 (false, 9259 (false, 9260 (false, 9261 (false,(false,(false,(sel'2,(sel'1,sel'0))))))))))))))))))))))))))))))) => 9262 CP(MFC0 9263 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9264 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9265 BitsN.fromBitstring([sel'2,sel'1,sel'0],3)))) 9266 | (false, 9267 (true, 9268 (false, 9269 (false, 9270 (false, 9271 (false, 9272 (false, 9273 (false, 9274 (false, 9275 (false, 9276 (true, 9277 (rt'4, 9278 (rt'3, 9279 (rt'2, 9280 (rt'1, 9281 (rt'0, 9282 (rd'4, 9283 (rd'3, 9284 (rd'2, 9285 (rd'1, 9286 (rd'0, 9287 (false, 9288 (false, 9289 (false, 9290 (false, 9291 (false, 9292 (false,(false,(false,(sel'2,(sel'1,sel'0))))))))))))))))))))))))))))))) => 9293 CP(DMFC0 9294 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9295 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9296 BitsN.fromBitstring([sel'2,sel'1,sel'0],3)))) 9297 | (false, 9298 (true, 9299 (false, 9300 (false, 9301 (false, 9302 (false, 9303 (false, 9304 (false, 9305 (true, 9306 (false, 9307 (false, 9308 (rt'4, 9309 (rt'3, 9310 (rt'2, 9311 (rt'1, 9312 (rt'0, 9313 (rd'4, 9314 (rd'3, 9315 (rd'2, 9316 (rd'1, 9317 (rd'0, 9318 (false, 9319 (false, 9320 (false, 9321 (false, 9322 (false, 9323 (false,(false,(false,(sel'2,(sel'1,sel'0))))))))))))))))))))))))))))))) => 9324 CP(MTC0 9325 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9326 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9327 BitsN.fromBitstring([sel'2,sel'1,sel'0],3)))) 9328 | (false, 9329 (true, 9330 (false, 9331 (false, 9332 (false, 9333 (false, 9334 (false, 9335 (false, 9336 (true, 9337 (false, 9338 (true, 9339 (rt'4, 9340 (rt'3, 9341 (rt'2, 9342 (rt'1, 9343 (rt'0, 9344 (rd'4, 9345 (rd'3, 9346 (rd'2, 9347 (rd'1, 9348 (rd'0, 9349 (false, 9350 (false, 9351 (false, 9352 (false, 9353 (false, 9354 (false,(false,(false,(sel'2,(sel'1,sel'0))))))))))))))))))))))))))))))) => 9355 CP(DMTC0 9356 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9357 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9358 BitsN.fromBitstring([sel'2,sel'1,sel'0],3)))) 9359 | (false, 9360 (false, 9361 (false, 9362 (true, 9363 (true, 9364 (false, 9365 (rs'4, 9366 (rs'3, 9367 (rs'2, 9368 (rs'1, 9369 (rs'0, 9370 (false, 9371 (false, 9372 (false, 9373 (false, 9374 (false, 9375 (immediate'15, 9376 (immediate'14, 9377 (immediate'13, 9378 (immediate'12, 9379 (immediate'11, 9380 (immediate'10, 9381 (immediate'9, 9382 (immediate'8, 9383 (immediate'7, 9384 (immediate'6, 9385 (immediate'5, 9386 (immediate'4, 9387 (immediate'3, 9388 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9389 Branch 9390 (BLEZ 9391 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9392 BitsN.fromBitstring 9393 ([immediate'15,immediate'14,immediate'13,immediate'12, 9394 immediate'11,immediate'10,immediate'9,immediate'8, 9395 immediate'7,immediate'6,immediate'5,immediate'4, 9396 immediate'3,immediate'2,immediate'1,immediate'0],16))) 9397 | (false, 9398 (false, 9399 (false, 9400 (true, 9401 (true, 9402 (true, 9403 (rs'4, 9404 (rs'3, 9405 (rs'2, 9406 (rs'1, 9407 (rs'0, 9408 (false, 9409 (false, 9410 (false, 9411 (false, 9412 (false, 9413 (immediate'15, 9414 (immediate'14, 9415 (immediate'13, 9416 (immediate'12, 9417 (immediate'11, 9418 (immediate'10, 9419 (immediate'9, 9420 (immediate'8, 9421 (immediate'7, 9422 (immediate'6, 9423 (immediate'5, 9424 (immediate'4, 9425 (immediate'3, 9426 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9427 Branch 9428 (BGTZ 9429 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9430 BitsN.fromBitstring 9431 ([immediate'15,immediate'14,immediate'13,immediate'12, 9432 immediate'11,immediate'10,immediate'9,immediate'8, 9433 immediate'7,immediate'6,immediate'5,immediate'4, 9434 immediate'3,immediate'2,immediate'1,immediate'0],16))) 9435 | (false, 9436 (false, 9437 (true, 9438 (true, 9439 (true, 9440 (true, 9441 (false, 9442 (false, 9443 (false, 9444 (false, 9445 (false, 9446 (rt'4, 9447 (rt'3, 9448 (rt'2, 9449 (rt'1, 9450 (rt'0, 9451 (immediate'15, 9452 (immediate'14, 9453 (immediate'13, 9454 (immediate'12, 9455 (immediate'11, 9456 (immediate'10, 9457 (immediate'9, 9458 (immediate'8, 9459 (immediate'7, 9460 (immediate'6, 9461 (immediate'5, 9462 (immediate'4, 9463 (immediate'3, 9464 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9465 ArithI 9466 (LUI(BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9467 BitsN.fromBitstring 9468 ([immediate'15,immediate'14,immediate'13,immediate'12, 9469 immediate'11,immediate'10,immediate'9,immediate'8, 9470 immediate'7,immediate'6,immediate'5,immediate'4, 9471 immediate'3,immediate'2,immediate'1,immediate'0],16))) 9472 | (false, 9473 (true, 9474 (false, 9475 (true, 9476 (true, 9477 (false, 9478 (rs'4, 9479 (rs'3, 9480 (rs'2, 9481 (rs'1, 9482 (rs'0, 9483 (false, 9484 (false, 9485 (false, 9486 (false, 9487 (false, 9488 (immediate'15, 9489 (immediate'14, 9490 (immediate'13, 9491 (immediate'12, 9492 (immediate'11, 9493 (immediate'10, 9494 (immediate'9, 9495 (immediate'8, 9496 (immediate'7, 9497 (immediate'6, 9498 (immediate'5, 9499 (immediate'4, 9500 (immediate'3, 9501 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9502 Branch 9503 (BLEZL 9504 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9505 BitsN.fromBitstring 9506 ([immediate'15,immediate'14,immediate'13,immediate'12, 9507 immediate'11,immediate'10,immediate'9,immediate'8, 9508 immediate'7,immediate'6,immediate'5,immediate'4, 9509 immediate'3,immediate'2,immediate'1,immediate'0],16))) 9510 | (false, 9511 (true, 9512 (false, 9513 (true, 9514 (true, 9515 (true, 9516 (rs'4, 9517 (rs'3, 9518 (rs'2, 9519 (rs'1, 9520 (rs'0, 9521 (false, 9522 (false, 9523 (false, 9524 (false, 9525 (false, 9526 (immediate'15, 9527 (immediate'14, 9528 (immediate'13, 9529 (immediate'12, 9530 (immediate'11, 9531 (immediate'10, 9532 (immediate'9, 9533 (immediate'8, 9534 (immediate'7, 9535 (immediate'6, 9536 (immediate'5, 9537 (immediate'4, 9538 (immediate'3, 9539 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9540 Branch 9541 (BGTZL 9542 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9543 BitsN.fromBitstring 9544 ([immediate'15,immediate'14,immediate'13,immediate'12, 9545 immediate'11,immediate'10,immediate'9,immediate'8, 9546 immediate'7,immediate'6,immediate'5,immediate'4, 9547 immediate'3,immediate'2,immediate'1,immediate'0],16))) 9548 | (false, 9549 (true, 9550 (true, 9551 (true, 9552 (false, 9553 (false, 9554 (rs'4, 9555 (rs'3, 9556 (rs'2, 9557 (rs'1, 9558 (rs'0, 9559 (rt'4, 9560 (rt'3, 9561 (rt'2, 9562 (rt'1, 9563 (rt'0, 9564 (false, 9565 (false, 9566 (false, 9567 (false, 9568 (false, 9569 (false, 9570 (false, 9571 (false, 9572 (false, 9573 (false, 9574 (false,(false,(false,(false,(false,false))))))))))))))))))))))))))))))) => 9575 MultDiv 9576 (MADD 9577 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9578 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 9579 | (false, 9580 (true, 9581 (true, 9582 (true, 9583 (false, 9584 (false, 9585 (rs'4, 9586 (rs'3, 9587 (rs'2, 9588 (rs'1, 9589 (rs'0, 9590 (rt'4, 9591 (rt'3, 9592 (rt'2, 9593 (rt'1, 9594 (rt'0, 9595 (false, 9596 (false, 9597 (false, 9598 (false, 9599 (false, 9600 (false, 9601 (false, 9602 (false, 9603 (false, 9604 (false, 9605 (false,(false,(false,(false,(false,true))))))))))))))))))))))))))))))) => 9606 MultDiv 9607 (MADDU 9608 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9609 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 9610 | (false, 9611 (true, 9612 (true, 9613 (true, 9614 (false, 9615 (false, 9616 (rs'4, 9617 (rs'3, 9618 (rs'2, 9619 (rs'1, 9620 (rs'0, 9621 (rt'4, 9622 (rt'3, 9623 (rt'2, 9624 (rt'1, 9625 (rt'0, 9626 (false, 9627 (false, 9628 (false, 9629 (false, 9630 (false, 9631 (false, 9632 (false, 9633 (false, 9634 (false, 9635 (false, 9636 (false,(false,(false,(true,(false,false))))))))))))))))))))))))))))))) => 9637 MultDiv 9638 (MSUB 9639 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9640 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 9641 | (false, 9642 (true, 9643 (true, 9644 (true, 9645 (false, 9646 (false, 9647 (rs'4, 9648 (rs'3, 9649 (rs'2, 9650 (rs'1, 9651 (rs'0, 9652 (rt'4, 9653 (rt'3, 9654 (rt'2, 9655 (rt'1, 9656 (rt'0, 9657 (false, 9658 (false, 9659 (false, 9660 (false, 9661 (false, 9662 (false, 9663 (false, 9664 (false, 9665 (false, 9666 (false, 9667 (false,(false,(false,(true,(false,true))))))))))))))))))))))))))))))) => 9668 MultDiv 9669 (MSUBU 9670 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9671 BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) 9672 | (false, 9673 (true, 9674 (true, 9675 (true, 9676 (false, 9677 (false, 9678 (rs'4, 9679 (rs'3, 9680 (rs'2, 9681 (rs'1, 9682 (rs'0, 9683 (rt'4, 9684 (rt'3, 9685 (rt'2, 9686 (rt'1, 9687 (rt'0, 9688 (rd'4, 9689 (rd'3, 9690 (rd'2, 9691 (rd'1, 9692 (rd'0, 9693 (false, 9694 (false, 9695 (false, 9696 (false, 9697 (false, 9698 (false,(false,(false,(false,(true,false))))))))))))))))))))))))))))))) => 9699 MultDiv 9700 (MUL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9701 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9702 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) 9703 | (false, 9704 (false, 9705 (false, 9706 (true, 9707 (false, 9708 (false, 9709 (rs'4, 9710 (rs'3, 9711 (rs'2, 9712 (rs'1, 9713 (rs'0, 9714 (rt'4, 9715 (rt'3, 9716 (rt'2, 9717 (rt'1, 9718 (rt'0, 9719 (immediate'15, 9720 (immediate'14, 9721 (immediate'13, 9722 (immediate'12, 9723 (immediate'11, 9724 (immediate'10, 9725 (immediate'9, 9726 (immediate'8, 9727 (immediate'7, 9728 (immediate'6, 9729 (immediate'5, 9730 (immediate'4, 9731 (immediate'3, 9732 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9733 Branch 9734 (BEQ(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9735 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9736 BitsN.fromBitstring 9737 ([immediate'15,immediate'14,immediate'13,immediate'12, 9738 immediate'11,immediate'10,immediate'9,immediate'8, 9739 immediate'7,immediate'6,immediate'5,immediate'4, 9740 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 9741 | (false, 9742 (false, 9743 (false, 9744 (true, 9745 (false, 9746 (true, 9747 (rs'4, 9748 (rs'3, 9749 (rs'2, 9750 (rs'1, 9751 (rs'0, 9752 (rt'4, 9753 (rt'3, 9754 (rt'2, 9755 (rt'1, 9756 (rt'0, 9757 (immediate'15, 9758 (immediate'14, 9759 (immediate'13, 9760 (immediate'12, 9761 (immediate'11, 9762 (immediate'10, 9763 (immediate'9, 9764 (immediate'8, 9765 (immediate'7, 9766 (immediate'6, 9767 (immediate'5, 9768 (immediate'4, 9769 (immediate'3, 9770 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9771 Branch 9772 (BNE(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9773 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9774 BitsN.fromBitstring 9775 ([immediate'15,immediate'14,immediate'13,immediate'12, 9776 immediate'11,immediate'10,immediate'9,immediate'8, 9777 immediate'7,immediate'6,immediate'5,immediate'4, 9778 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 9779 | (false, 9780 (false, 9781 (true, 9782 (false, 9783 (false, 9784 (false, 9785 (rs'4, 9786 (rs'3, 9787 (rs'2, 9788 (rs'1, 9789 (rs'0, 9790 (rt'4, 9791 (rt'3, 9792 (rt'2, 9793 (rt'1, 9794 (rt'0, 9795 (immediate'15, 9796 (immediate'14, 9797 (immediate'13, 9798 (immediate'12, 9799 (immediate'11, 9800 (immediate'10, 9801 (immediate'9, 9802 (immediate'8, 9803 (immediate'7, 9804 (immediate'6, 9805 (immediate'5, 9806 (immediate'4, 9807 (immediate'3, 9808 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9809 ArithI 9810 (ADDI 9811 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9812 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9813 BitsN.fromBitstring 9814 ([immediate'15,immediate'14,immediate'13,immediate'12, 9815 immediate'11,immediate'10,immediate'9,immediate'8, 9816 immediate'7,immediate'6,immediate'5,immediate'4, 9817 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 9818 | (false, 9819 (false, 9820 (true, 9821 (false, 9822 (false, 9823 (true, 9824 (rs'4, 9825 (rs'3, 9826 (rs'2, 9827 (rs'1, 9828 (rs'0, 9829 (rt'4, 9830 (rt'3, 9831 (rt'2, 9832 (rt'1, 9833 (rt'0, 9834 (immediate'15, 9835 (immediate'14, 9836 (immediate'13, 9837 (immediate'12, 9838 (immediate'11, 9839 (immediate'10, 9840 (immediate'9, 9841 (immediate'8, 9842 (immediate'7, 9843 (immediate'6, 9844 (immediate'5, 9845 (immediate'4, 9846 (immediate'3, 9847 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9848 ArithI 9849 (ADDIU 9850 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9851 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9852 BitsN.fromBitstring 9853 ([immediate'15,immediate'14,immediate'13,immediate'12, 9854 immediate'11,immediate'10,immediate'9,immediate'8, 9855 immediate'7,immediate'6,immediate'5,immediate'4, 9856 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 9857 | (false, 9858 (false, 9859 (true, 9860 (false, 9861 (true, 9862 (false, 9863 (rs'4, 9864 (rs'3, 9865 (rs'2, 9866 (rs'1, 9867 (rs'0, 9868 (rt'4, 9869 (rt'3, 9870 (rt'2, 9871 (rt'1, 9872 (rt'0, 9873 (immediate'15, 9874 (immediate'14, 9875 (immediate'13, 9876 (immediate'12, 9877 (immediate'11, 9878 (immediate'10, 9879 (immediate'9, 9880 (immediate'8, 9881 (immediate'7, 9882 (immediate'6, 9883 (immediate'5, 9884 (immediate'4, 9885 (immediate'3, 9886 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9887 ArithI 9888 (SLTI 9889 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9890 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9891 BitsN.fromBitstring 9892 ([immediate'15,immediate'14,immediate'13,immediate'12, 9893 immediate'11,immediate'10,immediate'9,immediate'8, 9894 immediate'7,immediate'6,immediate'5,immediate'4, 9895 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 9896 | (false, 9897 (false, 9898 (true, 9899 (false, 9900 (true, 9901 (true, 9902 (rs'4, 9903 (rs'3, 9904 (rs'2, 9905 (rs'1, 9906 (rs'0, 9907 (rt'4, 9908 (rt'3, 9909 (rt'2, 9910 (rt'1, 9911 (rt'0, 9912 (immediate'15, 9913 (immediate'14, 9914 (immediate'13, 9915 (immediate'12, 9916 (immediate'11, 9917 (immediate'10, 9918 (immediate'9, 9919 (immediate'8, 9920 (immediate'7, 9921 (immediate'6, 9922 (immediate'5, 9923 (immediate'4, 9924 (immediate'3, 9925 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9926 ArithI 9927 (SLTIU 9928 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9929 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9930 BitsN.fromBitstring 9931 ([immediate'15,immediate'14,immediate'13,immediate'12, 9932 immediate'11,immediate'10,immediate'9,immediate'8, 9933 immediate'7,immediate'6,immediate'5,immediate'4, 9934 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 9935 | (false, 9936 (false, 9937 (true, 9938 (true, 9939 (false, 9940 (false, 9941 (rs'4, 9942 (rs'3, 9943 (rs'2, 9944 (rs'1, 9945 (rs'0, 9946 (rt'4, 9947 (rt'3, 9948 (rt'2, 9949 (rt'1, 9950 (rt'0, 9951 (immediate'15, 9952 (immediate'14, 9953 (immediate'13, 9954 (immediate'12, 9955 (immediate'11, 9956 (immediate'10, 9957 (immediate'9, 9958 (immediate'8, 9959 (immediate'7, 9960 (immediate'6, 9961 (immediate'5, 9962 (immediate'4, 9963 (immediate'3, 9964 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 9965 ArithI 9966 (ANDI 9967 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 9968 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 9969 BitsN.fromBitstring 9970 ([immediate'15,immediate'14,immediate'13,immediate'12, 9971 immediate'11,immediate'10,immediate'9,immediate'8, 9972 immediate'7,immediate'6,immediate'5,immediate'4, 9973 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 9974 | (false, 9975 (false, 9976 (true, 9977 (true, 9978 (false, 9979 (true, 9980 (rs'4, 9981 (rs'3, 9982 (rs'2, 9983 (rs'1, 9984 (rs'0, 9985 (rt'4, 9986 (rt'3, 9987 (rt'2, 9988 (rt'1, 9989 (rt'0, 9990 (immediate'15, 9991 (immediate'14, 9992 (immediate'13, 9993 (immediate'12, 9994 (immediate'11, 9995 (immediate'10, 9996 (immediate'9, 9997 (immediate'8, 9998 (immediate'7, 9999 (immediate'6, 10000 (immediate'5, 10001 (immediate'4, 10002 (immediate'3, 10003 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10004 ArithI 10005 (ORI(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10006 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10007 BitsN.fromBitstring 10008 ([immediate'15,immediate'14,immediate'13,immediate'12, 10009 immediate'11,immediate'10,immediate'9,immediate'8, 10010 immediate'7,immediate'6,immediate'5,immediate'4, 10011 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10012 | (false, 10013 (false, 10014 (true, 10015 (true, 10016 (true, 10017 (false, 10018 (rs'4, 10019 (rs'3, 10020 (rs'2, 10021 (rs'1, 10022 (rs'0, 10023 (rt'4, 10024 (rt'3, 10025 (rt'2, 10026 (rt'1, 10027 (rt'0, 10028 (immediate'15, 10029 (immediate'14, 10030 (immediate'13, 10031 (immediate'12, 10032 (immediate'11, 10033 (immediate'10, 10034 (immediate'9, 10035 (immediate'8, 10036 (immediate'7, 10037 (immediate'6, 10038 (immediate'5, 10039 (immediate'4, 10040 (immediate'3, 10041 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10042 ArithI 10043 (XORI 10044 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10045 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10046 BitsN.fromBitstring 10047 ([immediate'15,immediate'14,immediate'13,immediate'12, 10048 immediate'11,immediate'10,immediate'9,immediate'8, 10049 immediate'7,immediate'6,immediate'5,immediate'4, 10050 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10051 | (false, 10052 (true, 10053 (false, 10054 (true, 10055 (false, 10056 (false, 10057 (rs'4, 10058 (rs'3, 10059 (rs'2, 10060 (rs'1, 10061 (rs'0, 10062 (rt'4, 10063 (rt'3, 10064 (rt'2, 10065 (rt'1, 10066 (rt'0, 10067 (immediate'15, 10068 (immediate'14, 10069 (immediate'13, 10070 (immediate'12, 10071 (immediate'11, 10072 (immediate'10, 10073 (immediate'9, 10074 (immediate'8, 10075 (immediate'7, 10076 (immediate'6, 10077 (immediate'5, 10078 (immediate'4, 10079 (immediate'3, 10080 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10081 Branch 10082 (BEQL 10083 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10084 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10085 BitsN.fromBitstring 10086 ([immediate'15,immediate'14,immediate'13,immediate'12, 10087 immediate'11,immediate'10,immediate'9,immediate'8, 10088 immediate'7,immediate'6,immediate'5,immediate'4, 10089 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10090 | (false, 10091 (true, 10092 (false, 10093 (true, 10094 (false, 10095 (true, 10096 (rs'4, 10097 (rs'3, 10098 (rs'2, 10099 (rs'1, 10100 (rs'0, 10101 (rt'4, 10102 (rt'3, 10103 (rt'2, 10104 (rt'1, 10105 (rt'0, 10106 (immediate'15, 10107 (immediate'14, 10108 (immediate'13, 10109 (immediate'12, 10110 (immediate'11, 10111 (immediate'10, 10112 (immediate'9, 10113 (immediate'8, 10114 (immediate'7, 10115 (immediate'6, 10116 (immediate'5, 10117 (immediate'4, 10118 (immediate'3, 10119 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10120 Branch 10121 (BNEL 10122 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10123 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10124 BitsN.fromBitstring 10125 ([immediate'15,immediate'14,immediate'13,immediate'12, 10126 immediate'11,immediate'10,immediate'9,immediate'8, 10127 immediate'7,immediate'6,immediate'5,immediate'4, 10128 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10129 | (false, 10130 (true, 10131 (true, 10132 (false, 10133 (false, 10134 (false, 10135 (rs'4, 10136 (rs'3, 10137 (rs'2, 10138 (rs'1, 10139 (rs'0, 10140 (rt'4, 10141 (rt'3, 10142 (rt'2, 10143 (rt'1, 10144 (rt'0, 10145 (immediate'15, 10146 (immediate'14, 10147 (immediate'13, 10148 (immediate'12, 10149 (immediate'11, 10150 (immediate'10, 10151 (immediate'9, 10152 (immediate'8, 10153 (immediate'7, 10154 (immediate'6, 10155 (immediate'5, 10156 (immediate'4, 10157 (immediate'3, 10158 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10159 ArithI 10160 (DADDI 10161 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10162 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10163 BitsN.fromBitstring 10164 ([immediate'15,immediate'14,immediate'13,immediate'12, 10165 immediate'11,immediate'10,immediate'9,immediate'8, 10166 immediate'7,immediate'6,immediate'5,immediate'4, 10167 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10168 | (false, 10169 (true, 10170 (true, 10171 (false, 10172 (false, 10173 (true, 10174 (rs'4, 10175 (rs'3, 10176 (rs'2, 10177 (rs'1, 10178 (rs'0, 10179 (rt'4, 10180 (rt'3, 10181 (rt'2, 10182 (rt'1, 10183 (rt'0, 10184 (immediate'15, 10185 (immediate'14, 10186 (immediate'13, 10187 (immediate'12, 10188 (immediate'11, 10189 (immediate'10, 10190 (immediate'9, 10191 (immediate'8, 10192 (immediate'7, 10193 (immediate'6, 10194 (immediate'5, 10195 (immediate'4, 10196 (immediate'3, 10197 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10198 ArithI 10199 (DADDIU 10200 (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10201 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10202 BitsN.fromBitstring 10203 ([immediate'15,immediate'14,immediate'13,immediate'12, 10204 immediate'11,immediate'10,immediate'9,immediate'8, 10205 immediate'7,immediate'6,immediate'5,immediate'4, 10206 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10207 | (false, 10208 (true, 10209 (true, 10210 (false, 10211 (true, 10212 (false, 10213 (rs'4, 10214 (rs'3, 10215 (rs'2, 10216 (rs'1, 10217 (rs'0, 10218 (rt'4, 10219 (rt'3, 10220 (rt'2, 10221 (rt'1, 10222 (rt'0, 10223 (immediate'15, 10224 (immediate'14, 10225 (immediate'13, 10226 (immediate'12, 10227 (immediate'11, 10228 (immediate'10, 10229 (immediate'9, 10230 (immediate'8, 10231 (immediate'7, 10232 (immediate'6, 10233 (immediate'5, 10234 (immediate'4, 10235 (immediate'3, 10236 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10237 Load 10238 (LDL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10239 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10240 BitsN.fromBitstring 10241 ([immediate'15,immediate'14,immediate'13,immediate'12, 10242 immediate'11,immediate'10,immediate'9,immediate'8, 10243 immediate'7,immediate'6,immediate'5,immediate'4, 10244 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10245 | (false, 10246 (true, 10247 (true, 10248 (false, 10249 (true, 10250 (true, 10251 (rs'4, 10252 (rs'3, 10253 (rs'2, 10254 (rs'1, 10255 (rs'0, 10256 (rt'4, 10257 (rt'3, 10258 (rt'2, 10259 (rt'1, 10260 (rt'0, 10261 (immediate'15, 10262 (immediate'14, 10263 (immediate'13, 10264 (immediate'12, 10265 (immediate'11, 10266 (immediate'10, 10267 (immediate'9, 10268 (immediate'8, 10269 (immediate'7, 10270 (immediate'6, 10271 (immediate'5, 10272 (immediate'4, 10273 (immediate'3, 10274 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10275 Load 10276 (LDR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10277 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10278 BitsN.fromBitstring 10279 ([immediate'15,immediate'14,immediate'13,immediate'12, 10280 immediate'11,immediate'10,immediate'9,immediate'8, 10281 immediate'7,immediate'6,immediate'5,immediate'4, 10282 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10283 | (true, 10284 (false, 10285 (false, 10286 (false, 10287 (false, 10288 (false, 10289 (rs'4, 10290 (rs'3, 10291 (rs'2, 10292 (rs'1, 10293 (rs'0, 10294 (rt'4, 10295 (rt'3, 10296 (rt'2, 10297 (rt'1, 10298 (rt'0, 10299 (immediate'15, 10300 (immediate'14, 10301 (immediate'13, 10302 (immediate'12, 10303 (immediate'11, 10304 (immediate'10, 10305 (immediate'9, 10306 (immediate'8, 10307 (immediate'7, 10308 (immediate'6, 10309 (immediate'5, 10310 (immediate'4, 10311 (immediate'3, 10312 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10313 Load 10314 (LB(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10315 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10316 BitsN.fromBitstring 10317 ([immediate'15,immediate'14,immediate'13,immediate'12, 10318 immediate'11,immediate'10,immediate'9,immediate'8, 10319 immediate'7,immediate'6,immediate'5,immediate'4, 10320 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10321 | (true, 10322 (false, 10323 (false, 10324 (false, 10325 (false, 10326 (true, 10327 (rs'4, 10328 (rs'3, 10329 (rs'2, 10330 (rs'1, 10331 (rs'0, 10332 (rt'4, 10333 (rt'3, 10334 (rt'2, 10335 (rt'1, 10336 (rt'0, 10337 (immediate'15, 10338 (immediate'14, 10339 (immediate'13, 10340 (immediate'12, 10341 (immediate'11, 10342 (immediate'10, 10343 (immediate'9, 10344 (immediate'8, 10345 (immediate'7, 10346 (immediate'6, 10347 (immediate'5, 10348 (immediate'4, 10349 (immediate'3, 10350 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10351 Load 10352 (LH(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10353 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10354 BitsN.fromBitstring 10355 ([immediate'15,immediate'14,immediate'13,immediate'12, 10356 immediate'11,immediate'10,immediate'9,immediate'8, 10357 immediate'7,immediate'6,immediate'5,immediate'4, 10358 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10359 | (true, 10360 (false, 10361 (false, 10362 (false, 10363 (true, 10364 (false, 10365 (rs'4, 10366 (rs'3, 10367 (rs'2, 10368 (rs'1, 10369 (rs'0, 10370 (rt'4, 10371 (rt'3, 10372 (rt'2, 10373 (rt'1, 10374 (rt'0, 10375 (immediate'15, 10376 (immediate'14, 10377 (immediate'13, 10378 (immediate'12, 10379 (immediate'11, 10380 (immediate'10, 10381 (immediate'9, 10382 (immediate'8, 10383 (immediate'7, 10384 (immediate'6, 10385 (immediate'5, 10386 (immediate'4, 10387 (immediate'3, 10388 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10389 Load 10390 (LWL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10391 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10392 BitsN.fromBitstring 10393 ([immediate'15,immediate'14,immediate'13,immediate'12, 10394 immediate'11,immediate'10,immediate'9,immediate'8, 10395 immediate'7,immediate'6,immediate'5,immediate'4, 10396 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10397 | (true, 10398 (false, 10399 (false, 10400 (false, 10401 (true, 10402 (true, 10403 (rs'4, 10404 (rs'3, 10405 (rs'2, 10406 (rs'1, 10407 (rs'0, 10408 (rt'4, 10409 (rt'3, 10410 (rt'2, 10411 (rt'1, 10412 (rt'0, 10413 (immediate'15, 10414 (immediate'14, 10415 (immediate'13, 10416 (immediate'12, 10417 (immediate'11, 10418 (immediate'10, 10419 (immediate'9, 10420 (immediate'8, 10421 (immediate'7, 10422 (immediate'6, 10423 (immediate'5, 10424 (immediate'4, 10425 (immediate'3, 10426 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10427 Load 10428 (LW(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10429 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10430 BitsN.fromBitstring 10431 ([immediate'15,immediate'14,immediate'13,immediate'12, 10432 immediate'11,immediate'10,immediate'9,immediate'8, 10433 immediate'7,immediate'6,immediate'5,immediate'4, 10434 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10435 | (true, 10436 (false, 10437 (false, 10438 (true, 10439 (false, 10440 (false, 10441 (rs'4, 10442 (rs'3, 10443 (rs'2, 10444 (rs'1, 10445 (rs'0, 10446 (rt'4, 10447 (rt'3, 10448 (rt'2, 10449 (rt'1, 10450 (rt'0, 10451 (immediate'15, 10452 (immediate'14, 10453 (immediate'13, 10454 (immediate'12, 10455 (immediate'11, 10456 (immediate'10, 10457 (immediate'9, 10458 (immediate'8, 10459 (immediate'7, 10460 (immediate'6, 10461 (immediate'5, 10462 (immediate'4, 10463 (immediate'3, 10464 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10465 Load 10466 (LBU(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10467 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10468 BitsN.fromBitstring 10469 ([immediate'15,immediate'14,immediate'13,immediate'12, 10470 immediate'11,immediate'10,immediate'9,immediate'8, 10471 immediate'7,immediate'6,immediate'5,immediate'4, 10472 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10473 | (true, 10474 (false, 10475 (false, 10476 (true, 10477 (false, 10478 (true, 10479 (rs'4, 10480 (rs'3, 10481 (rs'2, 10482 (rs'1, 10483 (rs'0, 10484 (rt'4, 10485 (rt'3, 10486 (rt'2, 10487 (rt'1, 10488 (rt'0, 10489 (immediate'15, 10490 (immediate'14, 10491 (immediate'13, 10492 (immediate'12, 10493 (immediate'11, 10494 (immediate'10, 10495 (immediate'9, 10496 (immediate'8, 10497 (immediate'7, 10498 (immediate'6, 10499 (immediate'5, 10500 (immediate'4, 10501 (immediate'3, 10502 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10503 Load 10504 (LHU(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10505 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10506 BitsN.fromBitstring 10507 ([immediate'15,immediate'14,immediate'13,immediate'12, 10508 immediate'11,immediate'10,immediate'9,immediate'8, 10509 immediate'7,immediate'6,immediate'5,immediate'4, 10510 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10511 | (true, 10512 (false, 10513 (false, 10514 (true, 10515 (true, 10516 (false, 10517 (rs'4, 10518 (rs'3, 10519 (rs'2, 10520 (rs'1, 10521 (rs'0, 10522 (rt'4, 10523 (rt'3, 10524 (rt'2, 10525 (rt'1, 10526 (rt'0, 10527 (immediate'15, 10528 (immediate'14, 10529 (immediate'13, 10530 (immediate'12, 10531 (immediate'11, 10532 (immediate'10, 10533 (immediate'9, 10534 (immediate'8, 10535 (immediate'7, 10536 (immediate'6, 10537 (immediate'5, 10538 (immediate'4, 10539 (immediate'3, 10540 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10541 Load 10542 (LWR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10543 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10544 BitsN.fromBitstring 10545 ([immediate'15,immediate'14,immediate'13,immediate'12, 10546 immediate'11,immediate'10,immediate'9,immediate'8, 10547 immediate'7,immediate'6,immediate'5,immediate'4, 10548 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10549 | (true, 10550 (false, 10551 (false, 10552 (true, 10553 (true, 10554 (true, 10555 (rs'4, 10556 (rs'3, 10557 (rs'2, 10558 (rs'1, 10559 (rs'0, 10560 (rt'4, 10561 (rt'3, 10562 (rt'2, 10563 (rt'1, 10564 (rt'0, 10565 (immediate'15, 10566 (immediate'14, 10567 (immediate'13, 10568 (immediate'12, 10569 (immediate'11, 10570 (immediate'10, 10571 (immediate'9, 10572 (immediate'8, 10573 (immediate'7, 10574 (immediate'6, 10575 (immediate'5, 10576 (immediate'4, 10577 (immediate'3, 10578 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10579 Load 10580 (LWU(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10581 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10582 BitsN.fromBitstring 10583 ([immediate'15,immediate'14,immediate'13,immediate'12, 10584 immediate'11,immediate'10,immediate'9,immediate'8, 10585 immediate'7,immediate'6,immediate'5,immediate'4, 10586 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10587 | (true, 10588 (false, 10589 (true, 10590 (false, 10591 (false, 10592 (false, 10593 (rs'4, 10594 (rs'3, 10595 (rs'2, 10596 (rs'1, 10597 (rs'0, 10598 (rt'4, 10599 (rt'3, 10600 (rt'2, 10601 (rt'1, 10602 (rt'0, 10603 (immediate'15, 10604 (immediate'14, 10605 (immediate'13, 10606 (immediate'12, 10607 (immediate'11, 10608 (immediate'10, 10609 (immediate'9, 10610 (immediate'8, 10611 (immediate'7, 10612 (immediate'6, 10613 (immediate'5, 10614 (immediate'4, 10615 (immediate'3, 10616 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10617 Store 10618 (SB(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10619 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10620 BitsN.fromBitstring 10621 ([immediate'15,immediate'14,immediate'13,immediate'12, 10622 immediate'11,immediate'10,immediate'9,immediate'8, 10623 immediate'7,immediate'6,immediate'5,immediate'4, 10624 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10625 | (true, 10626 (false, 10627 (true, 10628 (false, 10629 (false, 10630 (true, 10631 (rs'4, 10632 (rs'3, 10633 (rs'2, 10634 (rs'1, 10635 (rs'0, 10636 (rt'4, 10637 (rt'3, 10638 (rt'2, 10639 (rt'1, 10640 (rt'0, 10641 (immediate'15, 10642 (immediate'14, 10643 (immediate'13, 10644 (immediate'12, 10645 (immediate'11, 10646 (immediate'10, 10647 (immediate'9, 10648 (immediate'8, 10649 (immediate'7, 10650 (immediate'6, 10651 (immediate'5, 10652 (immediate'4, 10653 (immediate'3, 10654 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10655 Store 10656 (SH(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10657 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10658 BitsN.fromBitstring 10659 ([immediate'15,immediate'14,immediate'13,immediate'12, 10660 immediate'11,immediate'10,immediate'9,immediate'8, 10661 immediate'7,immediate'6,immediate'5,immediate'4, 10662 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10663 | (true, 10664 (false, 10665 (true, 10666 (false, 10667 (true, 10668 (false, 10669 (rs'4, 10670 (rs'3, 10671 (rs'2, 10672 (rs'1, 10673 (rs'0, 10674 (rt'4, 10675 (rt'3, 10676 (rt'2, 10677 (rt'1, 10678 (rt'0, 10679 (immediate'15, 10680 (immediate'14, 10681 (immediate'13, 10682 (immediate'12, 10683 (immediate'11, 10684 (immediate'10, 10685 (immediate'9, 10686 (immediate'8, 10687 (immediate'7, 10688 (immediate'6, 10689 (immediate'5, 10690 (immediate'4, 10691 (immediate'3, 10692 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10693 Store 10694 (SWL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10695 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10696 BitsN.fromBitstring 10697 ([immediate'15,immediate'14,immediate'13,immediate'12, 10698 immediate'11,immediate'10,immediate'9,immediate'8, 10699 immediate'7,immediate'6,immediate'5,immediate'4, 10700 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10701 | (true, 10702 (false, 10703 (true, 10704 (false, 10705 (true, 10706 (true, 10707 (rs'4, 10708 (rs'3, 10709 (rs'2, 10710 (rs'1, 10711 (rs'0, 10712 (rt'4, 10713 (rt'3, 10714 (rt'2, 10715 (rt'1, 10716 (rt'0, 10717 (immediate'15, 10718 (immediate'14, 10719 (immediate'13, 10720 (immediate'12, 10721 (immediate'11, 10722 (immediate'10, 10723 (immediate'9, 10724 (immediate'8, 10725 (immediate'7, 10726 (immediate'6, 10727 (immediate'5, 10728 (immediate'4, 10729 (immediate'3, 10730 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10731 Store 10732 (SW(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10733 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10734 BitsN.fromBitstring 10735 ([immediate'15,immediate'14,immediate'13,immediate'12, 10736 immediate'11,immediate'10,immediate'9,immediate'8, 10737 immediate'7,immediate'6,immediate'5,immediate'4, 10738 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10739 | (true, 10740 (false, 10741 (true, 10742 (true, 10743 (false, 10744 (false, 10745 (rs'4, 10746 (rs'3, 10747 (rs'2, 10748 (rs'1, 10749 (rs'0, 10750 (rt'4, 10751 (rt'3, 10752 (rt'2, 10753 (rt'1, 10754 (rt'0, 10755 (immediate'15, 10756 (immediate'14, 10757 (immediate'13, 10758 (immediate'12, 10759 (immediate'11, 10760 (immediate'10, 10761 (immediate'9, 10762 (immediate'8, 10763 (immediate'7, 10764 (immediate'6, 10765 (immediate'5, 10766 (immediate'4, 10767 (immediate'3, 10768 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10769 Store 10770 (SDL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10771 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10772 BitsN.fromBitstring 10773 ([immediate'15,immediate'14,immediate'13,immediate'12, 10774 immediate'11,immediate'10,immediate'9,immediate'8, 10775 immediate'7,immediate'6,immediate'5,immediate'4, 10776 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10777 | (true, 10778 (false, 10779 (true, 10780 (true, 10781 (false, 10782 (true, 10783 (rs'4, 10784 (rs'3, 10785 (rs'2, 10786 (rs'1, 10787 (rs'0, 10788 (rt'4, 10789 (rt'3, 10790 (rt'2, 10791 (rt'1, 10792 (rt'0, 10793 (immediate'15, 10794 (immediate'14, 10795 (immediate'13, 10796 (immediate'12, 10797 (immediate'11, 10798 (immediate'10, 10799 (immediate'9, 10800 (immediate'8, 10801 (immediate'7, 10802 (immediate'6, 10803 (immediate'5, 10804 (immediate'4, 10805 (immediate'3, 10806 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10807 Store 10808 (SDR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10809 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10810 BitsN.fromBitstring 10811 ([immediate'15,immediate'14,immediate'13,immediate'12, 10812 immediate'11,immediate'10,immediate'9,immediate'8, 10813 immediate'7,immediate'6,immediate'5,immediate'4, 10814 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10815 | (true, 10816 (false, 10817 (true, 10818 (true, 10819 (true, 10820 (false, 10821 (rs'4, 10822 (rs'3, 10823 (rs'2, 10824 (rs'1, 10825 (rs'0, 10826 (rt'4, 10827 (rt'3, 10828 (rt'2, 10829 (rt'1, 10830 (rt'0, 10831 (immediate'15, 10832 (immediate'14, 10833 (immediate'13, 10834 (immediate'12, 10835 (immediate'11, 10836 (immediate'10, 10837 (immediate'9, 10838 (immediate'8, 10839 (immediate'7, 10840 (immediate'6, 10841 (immediate'5, 10842 (immediate'4, 10843 (immediate'3, 10844 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10845 Store 10846 (SWR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10847 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10848 BitsN.fromBitstring 10849 ([immediate'15,immediate'14,immediate'13,immediate'12, 10850 immediate'11,immediate'10,immediate'9,immediate'8, 10851 immediate'7,immediate'6,immediate'5,immediate'4, 10852 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10853 | (true, 10854 (true, 10855 (false, 10856 (false, 10857 (false, 10858 (false, 10859 (rs'4, 10860 (rs'3, 10861 (rs'2, 10862 (rs'1, 10863 (rs'0, 10864 (rt'4, 10865 (rt'3, 10866 (rt'2, 10867 (rt'1, 10868 (rt'0, 10869 (immediate'15, 10870 (immediate'14, 10871 (immediate'13, 10872 (immediate'12, 10873 (immediate'11, 10874 (immediate'10, 10875 (immediate'9, 10876 (immediate'8, 10877 (immediate'7, 10878 (immediate'6, 10879 (immediate'5, 10880 (immediate'4, 10881 (immediate'3, 10882 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10883 Load 10884 (LL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10885 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10886 BitsN.fromBitstring 10887 ([immediate'15,immediate'14,immediate'13,immediate'12, 10888 immediate'11,immediate'10,immediate'9,immediate'8, 10889 immediate'7,immediate'6,immediate'5,immediate'4, 10890 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10891 | (true, 10892 (true, 10893 (false, 10894 (true, 10895 (false, 10896 (false, 10897 (rs'4, 10898 (rs'3, 10899 (rs'2, 10900 (rs'1, 10901 (rs'0, 10902 (rt'4, 10903 (rt'3, 10904 (rt'2, 10905 (rt'1, 10906 (rt'0, 10907 (immediate'15, 10908 (immediate'14, 10909 (immediate'13, 10910 (immediate'12, 10911 (immediate'11, 10912 (immediate'10, 10913 (immediate'9, 10914 (immediate'8, 10915 (immediate'7, 10916 (immediate'6, 10917 (immediate'5, 10918 (immediate'4, 10919 (immediate'3, 10920 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10921 Load 10922 (LLD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10923 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10924 BitsN.fromBitstring 10925 ([immediate'15,immediate'14,immediate'13,immediate'12, 10926 immediate'11,immediate'10,immediate'9,immediate'8, 10927 immediate'7,immediate'6,immediate'5,immediate'4, 10928 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10929 | (true, 10930 (true, 10931 (false, 10932 (true, 10933 (true, 10934 (true, 10935 (rs'4, 10936 (rs'3, 10937 (rs'2, 10938 (rs'1, 10939 (rs'0, 10940 (rt'4, 10941 (rt'3, 10942 (rt'2, 10943 (rt'1, 10944 (rt'0, 10945 (immediate'15, 10946 (immediate'14, 10947 (immediate'13, 10948 (immediate'12, 10949 (immediate'11, 10950 (immediate'10, 10951 (immediate'9, 10952 (immediate'8, 10953 (immediate'7, 10954 (immediate'6, 10955 (immediate'5, 10956 (immediate'4, 10957 (immediate'3, 10958 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10959 Load 10960 (LD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10961 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 10962 BitsN.fromBitstring 10963 ([immediate'15,immediate'14,immediate'13,immediate'12, 10964 immediate'11,immediate'10,immediate'9,immediate'8, 10965 immediate'7,immediate'6,immediate'5,immediate'4, 10966 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 10967 | (true, 10968 (true, 10969 (true, 10970 (false, 10971 (false, 10972 (false, 10973 (rs'4, 10974 (rs'3, 10975 (rs'2, 10976 (rs'1, 10977 (rs'0, 10978 (rt'4, 10979 (rt'3, 10980 (rt'2, 10981 (rt'1, 10982 (rt'0, 10983 (immediate'15, 10984 (immediate'14, 10985 (immediate'13, 10986 (immediate'12, 10987 (immediate'11, 10988 (immediate'10, 10989 (immediate'9, 10990 (immediate'8, 10991 (immediate'7, 10992 (immediate'6, 10993 (immediate'5, 10994 (immediate'4, 10995 (immediate'3, 10996 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 10997 Store 10998 (SC(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 10999 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 11000 BitsN.fromBitstring 11001 ([immediate'15,immediate'14,immediate'13,immediate'12, 11002 immediate'11,immediate'10,immediate'9,immediate'8, 11003 immediate'7,immediate'6,immediate'5,immediate'4, 11004 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 11005 | (true, 11006 (true, 11007 (true, 11008 (true, 11009 (false, 11010 (false, 11011 (rs'4, 11012 (rs'3, 11013 (rs'2, 11014 (rs'1, 11015 (rs'0, 11016 (rt'4, 11017 (rt'3, 11018 (rt'2, 11019 (rt'1, 11020 (rt'0, 11021 (immediate'15, 11022 (immediate'14, 11023 (immediate'13, 11024 (immediate'12, 11025 (immediate'11, 11026 (immediate'10, 11027 (immediate'9, 11028 (immediate'8, 11029 (immediate'7, 11030 (immediate'6, 11031 (immediate'5, 11032 (immediate'4, 11033 (immediate'3, 11034 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 11035 Store 11036 (SCD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 11037 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 11038 BitsN.fromBitstring 11039 ([immediate'15,immediate'14,immediate'13,immediate'12, 11040 immediate'11,immediate'10,immediate'9,immediate'8, 11041 immediate'7,immediate'6,immediate'5,immediate'4, 11042 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 11043 | (true, 11044 (true, 11045 (true, 11046 (true, 11047 (true, 11048 (true, 11049 (rs'4, 11050 (rs'3, 11051 (rs'2, 11052 (rs'1, 11053 (rs'0, 11054 (rt'4, 11055 (rt'3, 11056 (rt'2, 11057 (rt'1, 11058 (rt'0, 11059 (immediate'15, 11060 (immediate'14, 11061 (immediate'13, 11062 (immediate'12, 11063 (immediate'11, 11064 (immediate'10, 11065 (immediate'9, 11066 (immediate'8, 11067 (immediate'7, 11068 (immediate'6, 11069 (immediate'5, 11070 (immediate'4, 11071 (immediate'3, 11072 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 11073 Store 11074 (SD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), 11075 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 11076 BitsN.fromBitstring 11077 ([immediate'15,immediate'14,immediate'13,immediate'12, 11078 immediate'11,immediate'10,immediate'9,immediate'8, 11079 immediate'7,immediate'6,immediate'5,immediate'4, 11080 immediate'3,immediate'2,immediate'1,immediate'0],16)))) 11081 | (true, 11082 (false, 11083 (true, 11084 (true, 11085 (true, 11086 (true, 11087 (base'4, 11088 (base'3, 11089 (base'2, 11090 (base'1, 11091 (base'0, 11092 (opn'4, 11093 (opn'3, 11094 (opn'2, 11095 (opn'1, 11096 (opn'0, 11097 (immediate'15, 11098 (immediate'14, 11099 (immediate'13, 11100 (immediate'12, 11101 (immediate'11, 11102 (immediate'10, 11103 (immediate'9, 11104 (immediate'8, 11105 (immediate'7, 11106 (immediate'6, 11107 (immediate'5, 11108 (immediate'4, 11109 (immediate'3, 11110 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 11111 CACHE 11112 (BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5), 11113 (BitsN.fromBitstring([opn'4,opn'3,opn'2,opn'1,opn'0],5), 11114 BitsN.fromBitstring 11115 ([immediate'15,immediate'14,immediate'13,immediate'12, 11116 immediate'11,immediate'10,immediate'9,immediate'8, 11117 immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, 11118 immediate'2,immediate'1,immediate'0],16))) 11119 | (false, 11120 (true, 11121 (true, 11122 (true, 11123 (true, 11124 (true, 11125 (false, 11126 (false, 11127 (false, 11128 (false, 11129 (false, 11130 (rt'4, 11131 (rt'3, 11132 (rt'2, 11133 (rt'1, 11134 (rt'0, 11135 (rd'4, 11136 (rd'3, 11137 (rd'2, 11138 (rd'1, 11139 (rd'0, 11140 (false, 11141 (false, 11142 (false, 11143 (false, 11144 (false, 11145 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 11146 RDHWR 11147 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 11148 BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)) 11149 | (false, 11150 (true, 11151 (false, 11152 (false, 11153 (false, 11154 (false, 11155 (true, 11156 (false, 11157 (false, 11158 (false, 11159 (false, 11160 (false, 11161 (false, 11162 (false, 11163 (false, 11164 (false, 11165 (false, 11166 (false, 11167 (false, 11168 (false, 11169 (false, 11170 (false, 11171 (false, 11172 (false, 11173 (false, 11174 (false, 11175 (true,(false,(false,(false,(false,false))))))))))))))))))))))))))))))) => 11176 WAIT 11177 | (false, 11178 (true, 11179 (false, 11180 (false, 11181 (false, 11182 (true, 11183 (v'25, 11184 (v'24, 11185 (v'23, 11186 (v'22, 11187 (v'21, 11188 (v'20, 11189 (v'19, 11190 (v'18, 11191 (v'17, 11192 (v'16, 11193 (v'15, 11194 (v'14, 11195 (v'13, 11196 (v'12, 11197 (v'11, 11198 (v'10, 11199 (v'9, 11200 (v'8, 11201 (v'7,(v'6,(v'5,(v'4,(v'3,(v'2,(v'1,v'0))))))))))))))))))))))))))))))) => 11202 COP1Decode 11203 (BitsN.fromBitstring 11204 ([v'25,v'24,v'23,v'22,v'21,v'20,v'19,v'18,v'17,v'16,v'15,v'14, 11205 v'13,v'12,v'11,v'10,v'9,v'8,v'7,v'6,v'5,v'4,v'3,v'2,v'1,v'0], 11206 26)) 11207 | (false, 11208 (true, 11209 (false, 11210 (false, 11211 (true, 11212 (true, 11213 (v'25, 11214 (v'24, 11215 (v'23, 11216 (v'22, 11217 (v'21, 11218 (v'20, 11219 (v'19, 11220 (v'18, 11221 (v'17, 11222 (v'16, 11223 (v'15, 11224 (v'14, 11225 (v'13, 11226 (v'12, 11227 (v'11, 11228 (v'10, 11229 (v'9, 11230 (v'8, 11231 (v'7,(v'6,(v'5,(v'4,(v'3,(v'2,(v'1,v'0))))))))))))))))))))))))))))))) => 11232 COP3Decode 11233 (BitsN.fromBitstring 11234 ([v'25,v'24,v'23,v'22,v'21,v'20,v'19,v'18,v'17,v'16,v'15,v'14, 11235 v'13,v'12,v'11,v'10,v'9,v'8,v'7,v'6,v'5,v'4,v'3,v'2,v'1,v'0], 11236 26)) 11237 | (true, 11238 (true, 11239 (false, 11240 (false, 11241 (false, 11242 (true, 11243 (rs'4, 11244 (rs'3, 11245 (rs'2, 11246 (rs'1, 11247 (rs'0, 11248 (rt'4, 11249 (rt'3, 11250 (rt'2, 11251 (rt'1, 11252 (rt'0, 11253 (immediate'15, 11254 (immediate'14, 11255 (immediate'13, 11256 (immediate'12, 11257 (immediate'11, 11258 (immediate'10, 11259 (immediate'9, 11260 (immediate'8, 11261 (immediate'7, 11262 (immediate'6, 11263 (immediate'5, 11264 (immediate'4, 11265 (immediate'3, 11266 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 11267 LWC1Decode 11268 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 11269 (BitsN.fromBitstring 11270 ([immediate'15,immediate'14,immediate'13,immediate'12, 11271 immediate'11,immediate'10,immediate'9,immediate'8, 11272 immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, 11273 immediate'2,immediate'1,immediate'0],16), 11274 BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) 11275 | (true, 11276 (true, 11277 (true, 11278 (false, 11279 (false, 11280 (true, 11281 (rs'4, 11282 (rs'3, 11283 (rs'2, 11284 (rs'1, 11285 (rs'0, 11286 (rt'4, 11287 (rt'3, 11288 (rt'2, 11289 (rt'1, 11290 (rt'0, 11291 (immediate'15, 11292 (immediate'14, 11293 (immediate'13, 11294 (immediate'12, 11295 (immediate'11, 11296 (immediate'10, 11297 (immediate'9, 11298 (immediate'8, 11299 (immediate'7, 11300 (immediate'6, 11301 (immediate'5, 11302 (immediate'4, 11303 (immediate'3, 11304 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 11305 SWC1Decode 11306 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 11307 (BitsN.fromBitstring 11308 ([immediate'15,immediate'14,immediate'13,immediate'12, 11309 immediate'11,immediate'10,immediate'9,immediate'8, 11310 immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, 11311 immediate'2,immediate'1,immediate'0],16), 11312 BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) 11313 | (true, 11314 (true, 11315 (false, 11316 (true, 11317 (false, 11318 (true, 11319 (rs'4, 11320 (rs'3, 11321 (rs'2, 11322 (rs'1, 11323 (rs'0, 11324 (rt'4, 11325 (rt'3, 11326 (rt'2, 11327 (rt'1, 11328 (rt'0, 11329 (immediate'15, 11330 (immediate'14, 11331 (immediate'13, 11332 (immediate'12, 11333 (immediate'11, 11334 (immediate'10, 11335 (immediate'9, 11336 (immediate'8, 11337 (immediate'7, 11338 (immediate'6, 11339 (immediate'5, 11340 (immediate'4, 11341 (immediate'3, 11342 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 11343 LDC1Decode 11344 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 11345 (BitsN.fromBitstring 11346 ([immediate'15,immediate'14,immediate'13,immediate'12, 11347 immediate'11,immediate'10,immediate'9,immediate'8, 11348 immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, 11349 immediate'2,immediate'1,immediate'0],16), 11350 BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) 11351 | (true, 11352 (true, 11353 (true, 11354 (true, 11355 (false, 11356 (true, 11357 (rs'4, 11358 (rs'3, 11359 (rs'2, 11360 (rs'1, 11361 (rs'0, 11362 (rt'4, 11363 (rt'3, 11364 (rt'2, 11365 (rt'1, 11366 (rt'0, 11367 (immediate'15, 11368 (immediate'14, 11369 (immediate'13, 11370 (immediate'12, 11371 (immediate'11, 11372 (immediate'10, 11373 (immediate'9, 11374 (immediate'8, 11375 (immediate'7, 11376 (immediate'6, 11377 (immediate'5, 11378 (immediate'4, 11379 (immediate'3, 11380 (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => 11381 SDC1Decode 11382 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), 11383 (BitsN.fromBitstring 11384 ([immediate'15,immediate'14,immediate'13,immediate'12, 11385 immediate'11,immediate'10,immediate'9,immediate'8, 11386 immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, 11387 immediate'2,immediate'1,immediate'0],16), 11388 BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) 11389 | _ => ReservedInstruction; 11390 11391fun Next () = 11392 ( case Fetch () of Option.SOME w => Run(Decode w) | NONE => () 11393 ; case ((!BranchDelay),(!BranchTo)) of 11394 (NONE,NONE) => PC := (BitsN.+((!PC),BitsN.B(0x4,64))) 11395 | (NONE,Option.SOME(true,addr)) => 11396 ( BranchDelay := (Option.SOME NONE); BranchTo := NONE; PC := addr ) 11397 | (NONE,Option.SOME(false,addr)) => 11398 ( BranchDelay := (Option.SOME(Option.SOME addr)) 11399 ; BranchTo := NONE 11400 ; PC := (BitsN.+((!PC),BitsN.B(0x4,64))) 11401 ) 11402 | (Option.SOME NONE,NONE) => 11403 ( BranchDelay := NONE; PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ) 11404 | (Option.SOME(Option.SOME addr),NONE) => 11405 ( BranchDelay := NONE; PC := addr ) 11406 | _ => raise UNPREDICTABLE "Branch follows branch" 11407 ; exceptionSignalled := false 11408 ; CP0 := 11409 (CP0_Count_rupd((!CP0),BitsN.+(#Count((!CP0) : CP0),BitsN.B(0x1,32)))) 11410 ); 11411 11412fun cpr r = 11413 "c0_" 11414 ^ 11415 (case r of 11416 BitsN.B(0x0,_) => "index" 11417 | BitsN.B(0x1,_) => "random" 11418 | BitsN.B(0x2,_) => "entrylo0" 11419 | BitsN.B(0x3,_) => "entrylo1" 11420 | BitsN.B(0x4,_) => "context" 11421 | BitsN.B(0x5,_) => "pagemask" 11422 | BitsN.B(0x6,_) => "wired" 11423 | BitsN.B(0x7,_) => "hwrena" 11424 | BitsN.B(0x8,_) => "badvaddr" 11425 | BitsN.B(0x9,_) => "count" 11426 | BitsN.B(0xA,_) => "entryhi" 11427 | BitsN.B(0xB,_) => "compare" 11428 | BitsN.B(0xC,_) => "status" 11429 | BitsN.B(0xD,_) => "cause" 11430 | BitsN.B(0xE,_) => "epc" 11431 | BitsN.B(0xF,_) => "prid" 11432 | BitsN.B(0x10,_) => "config" 11433 | BitsN.B(0x11,_) => "lladdr" 11434 | BitsN.B(0x12,_) => "watchlo" 11435 | BitsN.B(0x13,_) => "watchhi" 11436 | BitsN.B(0x14,_) => "xcontext" 11437 | BitsN.B(0x15,_) => "21" 11438 | BitsN.B(0x16,_) => "22" 11439 | BitsN.B(0x17,_) => "debug" 11440 | BitsN.B(0x18,_) => "depc" 11441 | BitsN.B(0x19,_) => "perfcnt" 11442 | BitsN.B(0x1A,_) => "errctl" 11443 | BitsN.B(0x1B,_) => "cacheerr" 11444 | BitsN.B(0x1C,_) => "taglo" 11445 | BitsN.B(0x1D,_) => "taghi" 11446 | BitsN.B(0x1E,_) => "errorepc" 11447 | BitsN.B(0x1F,_) => "kscratch" 11448 | _ => raise General.Bind); 11449 11450fun reg_name n = 11451 "$" 11452 ^ 11453 (case n of 11454 BitsN.B(0x0,_) => "zero" 11455 | BitsN.B(0x1,_) => "at" 11456 | BitsN.B(0x2,_) => "v0" 11457 | BitsN.B(0x3,_) => "v1" 11458 | BitsN.B(0x4,_) => "a0" 11459 | BitsN.B(0x5,_) => "a1" 11460 | BitsN.B(0x6,_) => "a2" 11461 | BitsN.B(0x7,_) => "a3" 11462 | BitsN.B(0x8,_) => "t0" 11463 | BitsN.B(0x9,_) => "t1" 11464 | BitsN.B(0xA,_) => "t2" 11465 | BitsN.B(0xB,_) => "t3" 11466 | BitsN.B(0xC,_) => "t4" 11467 | BitsN.B(0xD,_) => "t5" 11468 | BitsN.B(0xE,_) => "t6" 11469 | BitsN.B(0xF,_) => "t7" 11470 | BitsN.B(0x10,_) => "s0" 11471 | BitsN.B(0x11,_) => "s1" 11472 | BitsN.B(0x12,_) => "s2" 11473 | BitsN.B(0x13,_) => "s3" 11474 | BitsN.B(0x14,_) => "s4" 11475 | BitsN.B(0x15,_) => "s5" 11476 | BitsN.B(0x16,_) => "s6" 11477 | BitsN.B(0x17,_) => "s7" 11478 | BitsN.B(0x18,_) => "t8" 11479 | BitsN.B(0x19,_) => "t9" 11480 | BitsN.B(0x1A,_) => "k0" 11481 | BitsN.B(0x1B,_) => "k1" 11482 | BitsN.B(0x1C,_) => "gp" 11483 | BitsN.B(0x1D,_) => "sp" 11484 | BitsN.B(0x1E,_) => "fp" 11485 | BitsN.B(0x1F,_) => "ra" 11486 | _ => raise General.Bind); 11487 11488fun op1i N (s,n) = 11489 String.concat 11490 [L3.padRightString(#" ",(12,s ^ " ")), 11491 if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x",BitsN.toHexString n]; 11492 11493fun op1ai N (s,n) = 11494 String.concat 11495 [L3.padRightString(#" ",(12,s ^ " ")), 11496 if BitsN.<+ 11497 (BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2),BitsN.B(0xA,32)) 11498 then "" 11499 else "0x", 11500 BitsN.toHexString(BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2))]; 11501 11502fun op1lai N (s,n) = 11503 String.concat 11504 [L3.padRightString(#" ",(12,s ^ " ")), 11505 if BitsN.<+ 11506 (BitsN.<< 11507 (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2), 11508 BitsN.B(0xA,32)) 11509 then "" 11510 else "0x", 11511 BitsN.toHexString 11512 (BitsN.<< 11513 (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2))]; 11514 11515fun op1r (s,n) = (L3.padRightString(#" ",(12,s ^ " "))) ^ (reg_name n); 11516 11517fun op1ri N (s,(r1,n)) = 11518 String.concat 11519 [op1r(s,r1),", ",if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x", 11520 BitsN.toHexString n]; 11521 11522fun op1rai N (s,(r1,n)) = 11523 String.concat 11524 [op1r(s,r1),", ", 11525 if BitsN.<+ 11526 (BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2),BitsN.B(0xA,32)) 11527 then "" 11528 else "0x", 11529 BitsN.toHexString(BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2))]; 11530 11531fun op1rlai N (s,(r1,n)) = 11532 String.concat 11533 [op1r(s,r1),", ", 11534 if BitsN.<+ 11535 (BitsN.<< 11536 (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2), 11537 BitsN.B(0xA,32)) 11538 then "" 11539 else "0x", 11540 BitsN.toHexString 11541 (BitsN.<< 11542 (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2))]; 11543 11544fun op2r (s,(r1,r2)) = String.concat[op1r(s,r1),", ",reg_name r2]; 11545 11546fun op2ri N (s,(r1,(r2,n))) = 11547 String.concat 11548 [op2r(s,(r1,r2)),", ", 11549 if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x",BitsN.toHexString n]; 11550 11551fun op2rai N (s,(r1,(r2,n))) = 11552 String.concat 11553 [op2r(s,(r1,r2)),", ", 11554 if BitsN.<+ 11555 (BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2),BitsN.B(0xA,32)) 11556 then "" 11557 else "0x", 11558 BitsN.toHexString(BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2))]; 11559 11560fun op2rlai N (s,(r1,(r2,n))) = 11561 String.concat 11562 [op2r(s,(r1,r2)),", ", 11563 if BitsN.<+ 11564 (BitsN.<< 11565 (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2), 11566 BitsN.B(0xA,32)) 11567 then "" 11568 else "0x", 11569 BitsN.toHexString 11570 (BitsN.<< 11571 (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2))]; 11572 11573fun op3r (s,(r1,(r2,r3))) = 11574 String.concat[op2r(s,(r1,r2)),", ",reg_name r3]; 11575 11576fun op2roi N (s,(r1,(r2,n))) = 11577 String.concat 11578 [op1r(s,r1),", ",cpr r2, 11579 if n = (BitsN.BV(0x0,N)) 11580 then "" 11581 else String.concat 11582 [", ",if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x", 11583 BitsN.toHexString n]]; 11584 11585fun opmem N (s,(r1,(r2,n))) = 11586 String.concat[op1ri N (s,(r1,n)),"(",reg_name r2,")"]; 11587 11588fun op1fpr (s,n) = 11589 String.concat 11590 [L3.padRightString(#" ",(12,s ^ " ")),"$f",Nat.toString(BitsN.toNat n)]; 11591 11592fun op1fpri N (s,(r1,n)) = 11593 String.concat 11594 [op1fpr(s,r1),", ",if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x", 11595 BitsN.toHexString n]; 11596 11597fun op2fpr (s,(r1,r2)) = 11598 String.concat[op1fpr(s,r1),", ","$f",Nat.toString(BitsN.toNat r2)]; 11599 11600fun op2rfpr (s,(r1,r2)) = 11601 String.concat[op1r(s,r1),", ","$f",Nat.toString(BitsN.toNat r2)]; 11602 11603fun op2rcfpr (s,(r1,r2)) = 11604 String.concat[op1r(s,r1),", $",Nat.toString(BitsN.toNat r2)]; 11605 11606fun op2ccfpr (s,(r1,(r2,n))) = 11607 String.concat 11608 [L3.padRightString(#" ",(12,s ^ " ")), 11609 if n = (BitsN.B(0x0,3)) 11610 then "" 11611 else String.concat["$fcc",Nat.toString(BitsN.toNat n),", "], 11612 "$f" ^ (Nat.toString(BitsN.toNat r1)),", ","$f", 11613 Nat.toString(BitsN.toNat r2)]; 11614 11615fun op3fpr (s,(r1,(r2,r3))) = 11616 String.concat[op2fpr(s,(r1,r2)),", ","$f",Nat.toString(BitsN.toNat r3)]; 11617 11618fun op4fpr (s,(r1,(r2,(r3,r4)))) = 11619 String.concat 11620 [op3fpr(s,(r1,(r2,r3))),", ","$f",Nat.toString(BitsN.toNat r4)]; 11621 11622fun opfpmem N (s,(r1,(r2,n))) = 11623 String.concat[op1fpri N (s,(r1,n)),"(",reg_name r2,")"]; 11624 11625fun opfpmem2 (s,(r1,(r2,r3))) = 11626 String.concat[op1fpr(s,r1),", ",reg_name r3,"(",reg_name r2,")"]; 11627 11628fun COP1Encode j = 11629 case j of 11630 MFC1(rt,fs) => BitsN.concat[BitsN.B(0x220,11),rt,fs,BitsN.B(0x0,11)] 11631 | DMFC1(rt,fs) => BitsN.concat[BitsN.B(0x221,11),rt,fs,BitsN.B(0x0,11)] 11632 | CFC1(rt,fs) => BitsN.concat[BitsN.B(0x222,11),rt,fs,BitsN.B(0x0,11)] 11633 | MTC1(rt,fs) => BitsN.concat[BitsN.B(0x224,11),rt,fs,BitsN.B(0x0,11)] 11634 | DMTC1(rt,fs) => BitsN.concat[BitsN.B(0x225,11),rt,fs,BitsN.B(0x0,11)] 11635 | CTC1(rt,fs) => BitsN.concat[BitsN.B(0x226,11),rt,fs,BitsN.B(0x0,11)] 11636 | BC1F(i,cc) => BitsN.concat[BitsN.B(0x228,11),cc,BitsN.B(0x0,2),i] 11637 | BC1T(i,cc) => BitsN.concat[BitsN.B(0x228,11),cc,BitsN.B(0x1,2),i] 11638 | BC1FL(i,cc) => BitsN.concat[BitsN.B(0x228,11),cc,BitsN.B(0x2,2),i] 11639 | BC1TL(i,cc) => BitsN.concat[BitsN.B(0x228,11),cc,BitsN.B(0x3,2),i] 11640 | ADD_S(fd,(fs,ft)) => 11641 BitsN.concat[BitsN.B(0x230,11),ft,fs,fd,BitsN.B(0x0,6)] 11642 | SUB_S(fd,(fs,ft)) => 11643 BitsN.concat[BitsN.B(0x230,11),ft,fs,fd,BitsN.B(0x1,6)] 11644 | MUL_S(fd,(fs,ft)) => 11645 BitsN.concat[BitsN.B(0x230,11),ft,fs,fd,BitsN.B(0x2,6)] 11646 | DIV_S(fd,(fs,ft)) => 11647 BitsN.concat[BitsN.B(0x230,11),ft,fs,fd,BitsN.B(0x3,6)] 11648 | SQRT_S(fd,fs) => 11649 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x4,6)] 11650 | ABS_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x5,6)] 11651 | MOV_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x6,6)] 11652 | NEG_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x7,6)] 11653 | ROUND_L_S(fd,fs) => 11654 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x8,6)] 11655 | TRUNC_L_S(fd,fs) => 11656 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x9,6)] 11657 | CEIL_L_S(fd,fs) => 11658 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xA,6)] 11659 | FLOOR_L_S(fd,fs) => 11660 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xB,6)] 11661 | ROUND_W_S(fd,fs) => 11662 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xC,6)] 11663 | TRUNC_W_S(fd,fs) => 11664 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xD,6)] 11665 | CEIL_W_S(fd,fs) => 11666 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xE,6)] 11667 | FLOOR_W_S(fd,fs) => 11668 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xF,6)] 11669 | MOVF_S(fd,(fs,cc)) => 11670 BitsN.concat 11671 [BitsN.B(0x230,11),cc,BitsN.B(0x0,2),fs,fd,BitsN.B(0x11,6)] 11672 | MOVT_S(fd,(fs,cc)) => 11673 BitsN.concat 11674 [BitsN.B(0x230,11),cc,BitsN.B(0x1,2),fs,fd,BitsN.B(0x11,6)] 11675 | MOVZ_S(fd,(fs,rt)) => 11676 BitsN.concat[BitsN.B(0x230,11),rt,fs,fd,BitsN.B(0x12,6)] 11677 | MOVN_S(fd,(fs,rt)) => 11678 BitsN.concat[BitsN.B(0x230,11),rt,fs,fd,BitsN.B(0x13,6)] 11679 | C_cond_S(fs,(ft,(cnd,cc))) => 11680 BitsN.concat[BitsN.B(0x230,11),ft,fs,cc,BitsN.B(0x6,5),cnd] 11681 | ADD_D(fd,(fs,ft)) => 11682 BitsN.concat[BitsN.B(0x231,11),ft,fs,fd,BitsN.B(0x0,6)] 11683 | SUB_D(fd,(fs,ft)) => 11684 BitsN.concat[BitsN.B(0x231,11),ft,fs,fd,BitsN.B(0x1,6)] 11685 | MUL_D(fd,(fs,ft)) => 11686 BitsN.concat[BitsN.B(0x231,11),ft,fs,fd,BitsN.B(0x2,6)] 11687 | DIV_D(fd,(fs,ft)) => 11688 BitsN.concat[BitsN.B(0x231,11),ft,fs,fd,BitsN.B(0x3,6)] 11689 | SQRT_D(fd,fs) => 11690 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x4,6)] 11691 | ABS_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x5,6)] 11692 | MOV_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x6,6)] 11693 | NEG_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x7,6)] 11694 | ROUND_L_D(fd,fs) => 11695 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x8,6)] 11696 | TRUNC_L_D(fd,fs) => 11697 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x9,6)] 11698 | CEIL_L_D(fd,fs) => 11699 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xA,6)] 11700 | FLOOR_L_D(fd,fs) => 11701 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xB,6)] 11702 | ROUND_W_D(fd,fs) => 11703 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xC,6)] 11704 | TRUNC_W_D(fd,fs) => 11705 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xD,6)] 11706 | CEIL_W_D(fd,fs) => 11707 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xE,6)] 11708 | FLOOR_W_D(fd,fs) => 11709 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xF,6)] 11710 | MOVF_D(fd,(fs,cc)) => 11711 BitsN.concat 11712 [BitsN.B(0x231,11),cc,BitsN.B(0x0,2),fs,fd,BitsN.B(0x11,6)] 11713 | MOVT_D(fd,(fs,cc)) => 11714 BitsN.concat 11715 [BitsN.B(0x231,11),cc,BitsN.B(0x1,2),fs,fd,BitsN.B(0x11,6)] 11716 | MOVZ_D(fd,(fs,rt)) => 11717 BitsN.concat[BitsN.B(0x231,11),rt,fs,fd,BitsN.B(0x12,6)] 11718 | MOVN_D(fd,(fs,rt)) => 11719 BitsN.concat[BitsN.B(0x231,11),rt,fs,fd,BitsN.B(0x13,6)] 11720 | C_cond_D(fs,(ft,(cnd,cc))) => 11721 BitsN.concat[BitsN.B(0x231,11),ft,fs,cc,BitsN.B(0x6,5),cnd] 11722 | CVT_S_D(fd,fs) => 11723 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x20,6)] 11724 | CVT_S_W(fd,fs) => 11725 BitsN.concat[BitsN.B(0x4680,16),fs,fd,BitsN.B(0x20,6)] 11726 | CVT_S_L(fd,fs) => 11727 BitsN.concat[BitsN.B(0x46A0,16),fs,fd,BitsN.B(0x20,6)] 11728 | CVT_D_S(fd,fs) => 11729 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x21,6)] 11730 | CVT_D_W(fd,fs) => 11731 BitsN.concat[BitsN.B(0x4680,16),fs,fd,BitsN.B(0x21,6)] 11732 | CVT_D_L(fd,fs) => 11733 BitsN.concat[BitsN.B(0x46A0,16),fs,fd,BitsN.B(0x21,6)] 11734 | CVT_W_S(fd,fs) => 11735 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x24,6)] 11736 | CVT_W_D(fd,fs) => 11737 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x24,6)] 11738 | CVT_L_S(fd,fs) => 11739 BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x25,6)] 11740 | CVT_L_D(fd,fs) => 11741 BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x25,6)] 11742 | LDC1(base,(offset,ft)) => 11743 BitsN.concat[BitsN.B(0x35,6),base,ft,offset] 11744 | LWC1(base,(offset,ft)) => 11745 BitsN.concat[BitsN.B(0x31,6),base,ft,offset] 11746 | SDC1(base,(offset,ft)) => 11747 BitsN.concat[BitsN.B(0x3D,6),base,ft,offset] 11748 | SWC1(base,(offset,ft)) => 11749 BitsN.concat[BitsN.B(0x39,6),base,ft,offset] 11750 | LWXC1(fd,(index,base)) => 11751 BitsN.concat 11752 [BitsN.B(0x13,6),base,index,BitsN.B(0x0,5),fd,BitsN.B(0x0,6)] 11753 | LDXC1(fd,(index,base)) => 11754 BitsN.concat 11755 [BitsN.B(0x13,6),base,index,BitsN.B(0x0,5),fd,BitsN.B(0x1,6)] 11756 | SWXC1(fs,(index,base)) => 11757 BitsN.concat[BitsN.B(0x13,6),base,index,fs,BitsN.B(0x8,11)] 11758 | SDXC1(fs,(index,base)) => 11759 BitsN.concat[BitsN.B(0x13,6),base,index,fs,BitsN.B(0x9,11)] 11760 | MADD_S(fd,(fr,(fs,ft))) => 11761 BitsN.concat[BitsN.B(0x13,6),fr,ft,fs,fd,BitsN.B(0x20,6)] 11762 | MADD_D(fd,(fr,(fs,ft))) => 11763 BitsN.concat[BitsN.B(0x13,6),fr,ft,fs,fd,BitsN.B(0x21,6)] 11764 | MSUB_S(fd,(fr,(fs,ft))) => 11765 BitsN.concat[BitsN.B(0x13,6),fr,ft,fs,fd,BitsN.B(0x28,6)] 11766 | MSUB_D(fd,(fr,(fs,ft))) => 11767 BitsN.concat[BitsN.B(0x13,6),fr,ft,fs,fd,BitsN.B(0x29,6)] 11768 | MOVF(rd,(rs,cc)) => 11769 BitsN.concat[BitsN.B(0x0,6),rs,cc,BitsN.B(0x0,2),rd,BitsN.B(0x1,11)] 11770 | MOVT(rd,(rs,cc)) => 11771 BitsN.concat[BitsN.B(0x0,6),rs,cc,BitsN.B(0x1,2),rd,BitsN.B(0x1,11)] 11772 | UnknownFPInstruction => BitsN.B(0x0,32); 11773 11774fun form1 (rs,(rt,(rd,(imm5,function)))) = 11775 BitsN.concat[BitsN.B(0x0,6),rs,rt,rd,imm5,function]; 11776 11777fun form2 (rs,(function,imm)) = 11778 BitsN.concat[BitsN.B(0x1,6),rs,function,imm]; 11779 11780fun form3 (function,(rt,(rd,sel))) = 11781 BitsN.concat[BitsN.B(0x10,6),function,rt,rd,BitsN.B(0x0,8),sel]; 11782 11783fun form4 (function,(rs,(rt,imm))) = BitsN.concat[function,rs,rt,imm]; 11784 11785fun form5 (rs,(rt,(rd,function))) = 11786 BitsN.concat[BitsN.B(0x1C,6),rs,rt,rd,BitsN.B(0x0,5),function]; 11787 11788fun form6 (rt,(rd,function)) = 11789 BitsN.concat 11790 [BitsN.B(0x1F,6),BitsN.B(0x0,5),rt,rd,BitsN.B(0x0,5),function]; 11791 11792fun Encode i = 11793 case i of 11794 Shift(SLL(rt,(rd,imm5))) => 11795 form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x0,6))))) 11796 | Shift(SRL(rt,(rd,imm5))) => 11797 form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x2,6))))) 11798 | Shift(SRA(rt,(rd,imm5))) => 11799 form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3,6))))) 11800 | Shift(SLLV(rs,(rt,rd))) => 11801 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x4,6))))) 11802 | Shift(SRLV(rs,(rt,rd))) => 11803 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x6,6))))) 11804 | Shift(SRAV(rs,(rt,rd))) => 11805 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x7,6))))) 11806 | Branch(JR rs) => 11807 form1 11808 (rs, 11809 (BitsN.B(0x0,5),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x8,6))))) 11810 | Branch(JALR(rs,rd)) => 11811 form1(rs,(BitsN.B(0x0,5),(rd,(BitsN.B(0x0,5),BitsN.B(0x9,6))))) 11812 | MultDiv(MFHI rd) => 11813 form1 11814 (BitsN.B(0x0,5), 11815 (BitsN.B(0x0,5),(rd,(BitsN.B(0x0,5),BitsN.B(0x10,6))))) 11816 | MultDiv(MTHI rs) => 11817 form1 11818 (rs, 11819 (BitsN.B(0x0,5),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x11,6))))) 11820 | MultDiv(MFLO rd) => 11821 form1 11822 (BitsN.B(0x0,5), 11823 (BitsN.B(0x0,5),(rd,(BitsN.B(0x0,5),BitsN.B(0x12,6))))) 11824 | MultDiv(MTLO rs) => 11825 form1 11826 (rs, 11827 (BitsN.B(0x0,5),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x13,6))))) 11828 | Shift(DSLLV(rs,(rt,rd))) => 11829 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x14,6))))) 11830 | Shift(DSRLV(rs,(rt,rd))) => 11831 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x16,6))))) 11832 | Shift(DSRAV(rs,(rt,rd))) => 11833 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x17,6))))) 11834 | MultDiv(MADD(rs,rt)) => 11835 form5(rs,(rt,(BitsN.B(0x0,5),BitsN.B(0x0,6)))) 11836 | MultDiv(MADDU(rs,rt)) => 11837 form5(rs,(rt,(BitsN.B(0x0,5),BitsN.B(0x1,6)))) 11838 | MultDiv(MSUB(rs,rt)) => 11839 form5(rs,(rt,(BitsN.B(0x0,5),BitsN.B(0x4,6)))) 11840 | MultDiv(MSUBU(rs,rt)) => 11841 form5(rs,(rt,(BitsN.B(0x0,5),BitsN.B(0x5,6)))) 11842 | MultDiv(MUL(rs,(rt,rd))) => form5(rs,(rt,(rd,BitsN.B(0x2,6)))) 11843 | MultDiv(MULT(rs,rt)) => 11844 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x18,6))))) 11845 | MultDiv(MULTU(rs,rt)) => 11846 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x19,6))))) 11847 | MultDiv(DIV(rs,rt)) => 11848 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1A,6))))) 11849 | MultDiv(DIVU(rs,rt)) => 11850 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1B,6))))) 11851 | MultDiv(DMULT(rs,rt)) => 11852 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1C,6))))) 11853 | MultDiv(DMULTU(rs,rt)) => 11854 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1D,6))))) 11855 | MultDiv(DDIV(rs,rt)) => 11856 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1E,6))))) 11857 | MultDiv(DDIVU(rs,rt)) => 11858 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1F,6))))) 11859 | ArithR(MOVZ(rs,(rt,rd))) => 11860 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0xA,6))))) 11861 | ArithR(MOVN(rs,(rt,rd))) => 11862 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0xB,6))))) 11863 | ArithR(ADD(rs,(rt,rd))) => 11864 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x20,6))))) 11865 | ArithR(ADDU(rs,(rt,rd))) => 11866 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x21,6))))) 11867 | ArithR(SUB(rs,(rt,rd))) => 11868 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x22,6))))) 11869 | ArithR(SUBU(rs,(rt,rd))) => 11870 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x23,6))))) 11871 | ArithR(AND(rs,(rt,rd))) => 11872 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x24,6))))) 11873 | ArithR(OR(rs,(rt,rd))) => 11874 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x25,6))))) 11875 | ArithR(XOR(rs,(rt,rd))) => 11876 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x26,6))))) 11877 | ArithR(NOR(rs,(rt,rd))) => 11878 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x27,6))))) 11879 | ArithR(SLT(rs,(rt,rd))) => 11880 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2A,6))))) 11881 | ArithR(SLTU(rs,(rt,rd))) => 11882 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2B,6))))) 11883 | ArithR(DADD(rs,(rt,rd))) => 11884 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2C,6))))) 11885 | ArithR(DADDU(rs,(rt,rd))) => 11886 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2D,6))))) 11887 | ArithR(DSUB(rs,(rt,rd))) => 11888 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2E,6))))) 11889 | ArithR(DSUBU(rs,(rt,rd))) => 11890 form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2F,6))))) 11891 | Trap(TGE(rs,rt)) => 11892 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x30,6))))) 11893 | Trap(TGEU(rs,rt)) => 11894 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x31,6))))) 11895 | Trap(TLT(rs,rt)) => 11896 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x32,6))))) 11897 | Trap(TLTU(rs,rt)) => 11898 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x33,6))))) 11899 | Trap(TEQ(rs,rt)) => 11900 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x34,6))))) 11901 | Trap(TNE(rs,rt)) => 11902 form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x36,6))))) 11903 | Shift(DSLL(rt,(rd,imm5))) => 11904 form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x38,6))))) 11905 | Shift(DSRL(rt,(rd,imm5))) => 11906 form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3A,6))))) 11907 | Shift(DSRA(rt,(rd,imm5))) => 11908 form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3B,6))))) 11909 | Shift(DSLL32(rt,(rd,imm5))) => 11910 form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3C,6))))) 11911 | Shift(DSRL32(rt,(rd,imm5))) => 11912 form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3E,6))))) 11913 | Shift(DSRA32(rt,(rd,imm5))) => 11914 form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3F,6))))) 11915 | Branch(BLTZ(rs,imm)) => form2(rs,(BitsN.B(0x0,5),imm)) 11916 | Branch(BGEZ(rs,imm)) => form2(rs,(BitsN.B(0x1,5),imm)) 11917 | Branch(BLTZL(rs,imm)) => form2(rs,(BitsN.B(0x2,5),imm)) 11918 | Branch(BGEZL(rs,imm)) => form2(rs,(BitsN.B(0x3,5),imm)) 11919 | Trap(TGEI(rs,imm)) => form2(rs,(BitsN.B(0x8,5),imm)) 11920 | Trap(TGEIU(rs,imm)) => form2(rs,(BitsN.B(0x9,5),imm)) 11921 | Trap(TLTI(rs,imm)) => form2(rs,(BitsN.B(0xA,5),imm)) 11922 | Trap(TLTIU(rs,imm)) => form2(rs,(BitsN.B(0xB,5),imm)) 11923 | Trap(TEQI(rs,imm)) => form2(rs,(BitsN.B(0xC,5),imm)) 11924 | Trap(TNEI(rs,imm)) => form2(rs,(BitsN.B(0xE,5),imm)) 11925 | Branch(BLTZAL(rs,imm)) => form2(rs,(BitsN.B(0x10,5),imm)) 11926 | Branch(BGEZAL(rs,imm)) => form2(rs,(BitsN.B(0x11,5),imm)) 11927 | Branch(BLTZALL(rs,imm)) => form2(rs,(BitsN.B(0x12,5),imm)) 11928 | Branch(BGEZALL(rs,imm)) => form2(rs,(BitsN.B(0x13,5),imm)) 11929 | Branch(J imm) => BitsN.@@(BitsN.B(0x2,6),imm) 11930 | Branch(JAL imm) => BitsN.@@(BitsN.B(0x3,6),imm) 11931 | CP(MFC0(rt,(rd,sel))) => form3(BitsN.B(0x0,5),(rt,(rd,sel))) 11932 | CP(DMFC0(rt,(rd,sel))) => form3(BitsN.B(0x1,5),(rt,(rd,sel))) 11933 | CP(MTC0(rt,(rd,sel))) => form3(BitsN.B(0x4,5),(rt,(rd,sel))) 11934 | CP(DMTC0(rt,(rd,sel))) => form3(BitsN.B(0x5,5),(rt,(rd,sel))) 11935 | Branch(BEQ(rs,(rt,imm))) => form4(BitsN.B(0x4,6),(rs,(rt,imm))) 11936 | Branch(BNE(rs,(rt,imm))) => form4(BitsN.B(0x5,6),(rs,(rt,imm))) 11937 | Branch(BLEZ(rs,imm)) => 11938 form4(BitsN.B(0x6,6),(rs,(BitsN.B(0x0,5),imm))) 11939 | Branch(BGTZ(rs,imm)) => 11940 form4(BitsN.B(0x7,6),(rs,(BitsN.B(0x0,5),imm))) 11941 | ArithI(ADDI(rs,(rt,imm))) => form4(BitsN.B(0x8,6),(rs,(rt,imm))) 11942 | ArithI(ADDIU(rs,(rt,imm))) => form4(BitsN.B(0x9,6),(rs,(rt,imm))) 11943 | ArithI(SLTI(rs,(rt,imm))) => form4(BitsN.B(0xA,6),(rs,(rt,imm))) 11944 | ArithI(SLTIU(rs,(rt,imm))) => form4(BitsN.B(0xB,6),(rs,(rt,imm))) 11945 | ArithI(ANDI(rs,(rt,imm))) => form4(BitsN.B(0xC,6),(rs,(rt,imm))) 11946 | ArithI(ORI(rs,(rt,imm))) => form4(BitsN.B(0xD,6),(rs,(rt,imm))) 11947 | ArithI(XORI(rs,(rt,imm))) => form4(BitsN.B(0xE,6),(rs,(rt,imm))) 11948 | ArithI(LUI(rt,imm)) => 11949 form4(BitsN.B(0xF,6),(BitsN.B(0x0,5),(rt,imm))) 11950 | Branch(BEQL(rs,(rt,imm))) => form4(BitsN.B(0x14,6),(rs,(rt,imm))) 11951 | Branch(BNEL(rs,(rt,imm))) => form4(BitsN.B(0x15,6),(rs,(rt,imm))) 11952 | Branch(BLEZL(rs,imm)) => 11953 form4(BitsN.B(0x16,6),(rs,(BitsN.B(0x0,5),imm))) 11954 | Branch(BGTZL(rs,imm)) => 11955 form4(BitsN.B(0x17,6),(rs,(BitsN.B(0x0,5),imm))) 11956 | ArithI(DADDI(rs,(rt,imm))) => form4(BitsN.B(0x18,6),(rs,(rt,imm))) 11957 | ArithI(DADDIU(rs,(rt,imm))) => form4(BitsN.B(0x19,6),(rs,(rt,imm))) 11958 | Load(LDL(rs,(rt,imm))) => form4(BitsN.B(0x1A,6),(rs,(rt,imm))) 11959 | Load(LDR(rs,(rt,imm))) => form4(BitsN.B(0x1B,6),(rs,(rt,imm))) 11960 | Load(LB(rs,(rt,imm))) => form4(BitsN.B(0x20,6),(rs,(rt,imm))) 11961 | Load(LH(rs,(rt,imm))) => form4(BitsN.B(0x21,6),(rs,(rt,imm))) 11962 | Load(LWL(rs,(rt,imm))) => form4(BitsN.B(0x22,6),(rs,(rt,imm))) 11963 | Load(LW(rs,(rt,imm))) => form4(BitsN.B(0x23,6),(rs,(rt,imm))) 11964 | Load(LBU(rs,(rt,imm))) => form4(BitsN.B(0x24,6),(rs,(rt,imm))) 11965 | Load(LHU(rs,(rt,imm))) => form4(BitsN.B(0x25,6),(rs,(rt,imm))) 11966 | Load(LWR(rs,(rt,imm))) => form4(BitsN.B(0x26,6),(rs,(rt,imm))) 11967 | Load(LWU(rs,(rt,imm))) => form4(BitsN.B(0x27,6),(rs,(rt,imm))) 11968 | Store(SB(rs,(rt,imm))) => form4(BitsN.B(0x28,6),(rs,(rt,imm))) 11969 | Store(SH(rs,(rt,imm))) => form4(BitsN.B(0x29,6),(rs,(rt,imm))) 11970 | Store(SWL(rs,(rt,imm))) => form4(BitsN.B(0x2A,6),(rs,(rt,imm))) 11971 | Store(SW(rs,(rt,imm))) => form4(BitsN.B(0x2B,6),(rs,(rt,imm))) 11972 | Store(SDL(rs,(rt,imm))) => form4(BitsN.B(0x2C,6),(rs,(rt,imm))) 11973 | Store(SDR(rs,(rt,imm))) => form4(BitsN.B(0x2D,6),(rs,(rt,imm))) 11974 | Store(SWR(rs,(rt,imm))) => form4(BitsN.B(0x2E,6),(rs,(rt,imm))) 11975 | Load(LL(rs,(rt,imm))) => form4(BitsN.B(0x30,6),(rs,(rt,imm))) 11976 | Load(LLD(rs,(rt,imm))) => form4(BitsN.B(0x34,6),(rs,(rt,imm))) 11977 | Load(LD(rs,(rt,imm))) => form4(BitsN.B(0x37,6),(rs,(rt,imm))) 11978 | Store(SC(rs,(rt,imm))) => form4(BitsN.B(0x38,6),(rs,(rt,imm))) 11979 | Store(SCD(rs,(rt,imm))) => form4(BitsN.B(0x3C,6),(rs,(rt,imm))) 11980 | Store(SD(rs,(rt,imm))) => form4(BitsN.B(0x3F,6),(rs,(rt,imm))) 11981 | CACHE(rs,(opn,imm)) => form4(BitsN.B(0x2F,6),(rs,(opn,imm))) 11982 | SYSCALL => BitsN.fromNat(BitsN.toNat(BitsN.B(0xC,6)),32) 11983 | BREAK => BitsN.fromNat(BitsN.toNat(BitsN.B(0xD,6)),32) 11984 | SYNC imm5 => 11985 BitsN.fromNat(BitsN.toNat(BitsN.@@(imm5,BitsN.B(0xF,6))),32) 11986 | TLBR => BitsN.B(0x42000001,32) 11987 | TLBWI => BitsN.B(0x42000002,32) 11988 | TLBWR => BitsN.B(0x42000006,32) 11989 | TLBP => BitsN.B(0x42000008,32) 11990 | ERET => BitsN.B(0x42000018,32) 11991 | RDHWR(rt,rd) => form6(rt,(rd,BitsN.B(0x3B,6))) 11992 | WAIT => BitsN.B(0x42000020,32) 11993 | Unpredictable => BitsN.B(0x7F00000,32) 11994 | COP1 j => COP1Encode j 11995 | ReservedInstruction => BitsN.B(0x0,32); 11996 11997fun COP1InstructionToString j = 11998 case j of 11999 ABS_D(fd,fs) => op2fpr("abs.d",(fd,fs)) 12000 | ABS_S(fd,fs) => op2fpr("abs.s",(fd,fs)) 12001 | ADD_D(fd,(fs,ft)) => op3fpr("add.d",(fd,(fs,ft))) 12002 | ADD_S(fd,(fs,ft)) => op3fpr("add.s",(fd,(fs,ft))) 12003 | BC1F(i,cc) => 12004 String.concat 12005 [L3.padRightString(#" ",(12,"bc1f" ^ " ")), 12006 if cc = (BitsN.B(0x0,3)) 12007 then "" 12008 else String.concat["$fcc",Nat.toString(BitsN.toNat cc),", "], 12009 if BitsN.<+ 12010 (BitsN.<< 12011 (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32), 12012 2),BitsN.B(0xA,32)) 12013 then "" 12014 else "0x", 12015 BitsN.toHexString 12016 (BitsN.<< 12017 (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32),2))] 12018 | BC1FL(i,cc) => 12019 String.concat 12020 [L3.padRightString(#" ",(12,"bc1fl" ^ " ")), 12021 if cc = (BitsN.B(0x0,3)) 12022 then "" 12023 else String.concat["$fcc",Nat.toString(BitsN.toNat cc),", "], 12024 if BitsN.<+ 12025 (BitsN.<< 12026 (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32), 12027 2),BitsN.B(0xA,32)) 12028 then "" 12029 else "0x", 12030 BitsN.toHexString 12031 (BitsN.<< 12032 (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32),2))] 12033 | BC1T(i,cc) => 12034 String.concat 12035 [L3.padRightString(#" ",(12,"bc1t" ^ " ")), 12036 if cc = (BitsN.B(0x0,3)) 12037 then "" 12038 else String.concat["$fcc",Nat.toString(BitsN.toNat cc),", "], 12039 if BitsN.<+ 12040 (BitsN.<< 12041 (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32), 12042 2),BitsN.B(0xA,32)) 12043 then "" 12044 else "0x", 12045 BitsN.toHexString 12046 (BitsN.<< 12047 (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32),2))] 12048 | BC1TL(i,cc) => 12049 String.concat 12050 [L3.padRightString(#" ",(12,"bc1tl" ^ " ")), 12051 if cc = (BitsN.B(0x0,3)) 12052 then "" 12053 else String.concat["$fcc",Nat.toString(BitsN.toNat cc),", "], 12054 if BitsN.<+ 12055 (BitsN.<< 12056 (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32), 12057 2),BitsN.B(0xA,32)) 12058 then "" 12059 else "0x", 12060 BitsN.toHexString 12061 (BitsN.<< 12062 (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32),2))] 12063 | C_cond_D(fs,(ft,(BitsN.B(0x0,3),cc))) => 12064 op2ccfpr("c.f.d",(fs,(ft,cc))) 12065 | C_cond_D(fs,(ft,(BitsN.B(0x1,3),cc))) => 12066 op2ccfpr("c.un.d",(fs,(ft,cc))) 12067 | C_cond_D(fs,(ft,(BitsN.B(0x2,3),cc))) => 12068 op2ccfpr("c.eq.d",(fs,(ft,cc))) 12069 | C_cond_D(fs,(ft,(BitsN.B(0x3,3),cc))) => 12070 op2ccfpr("c.ueq.d",(fs,(ft,cc))) 12071 | C_cond_D(fs,(ft,(BitsN.B(0x4,3),cc))) => 12072 op2ccfpr("c.olt.d",(fs,(ft,cc))) 12073 | C_cond_D(fs,(ft,(BitsN.B(0x5,3),cc))) => 12074 op2ccfpr("c.ult.d",(fs,(ft,cc))) 12075 | C_cond_D(fs,(ft,(BitsN.B(0x6,3),cc))) => 12076 op2ccfpr("c.ole.d",(fs,(ft,cc))) 12077 | C_cond_D(fs,(ft,(BitsN.B(0x7,3),cc))) => 12078 op2ccfpr("c.ule.d",(fs,(ft,cc))) 12079 | C_cond_S(fs,(ft,(BitsN.B(0x0,3),cc))) => 12080 op2ccfpr("c.f.s",(fs,(ft,cc))) 12081 | C_cond_S(fs,(ft,(BitsN.B(0x1,3),cc))) => 12082 op2ccfpr("c.un.s",(fs,(ft,cc))) 12083 | C_cond_S(fs,(ft,(BitsN.B(0x2,3),cc))) => 12084 op2ccfpr("c.eq.s",(fs,(ft,cc))) 12085 | C_cond_S(fs,(ft,(BitsN.B(0x3,3),cc))) => 12086 op2ccfpr("c.ueq.s",(fs,(ft,cc))) 12087 | C_cond_S(fs,(ft,(BitsN.B(0x4,3),cc))) => 12088 op2ccfpr("c.olt.s",(fs,(ft,cc))) 12089 | C_cond_S(fs,(ft,(BitsN.B(0x5,3),cc))) => 12090 op2ccfpr("c.ult.s",(fs,(ft,cc))) 12091 | C_cond_S(fs,(ft,(BitsN.B(0x6,3),cc))) => 12092 op2ccfpr("c.ole.s",(fs,(ft,cc))) 12093 | C_cond_S(fs,(ft,(BitsN.B(0x7,3),cc))) => 12094 op2ccfpr("c.ule.s",(fs,(ft,cc))) 12095 | CEIL_L_D(fd,fs) => op2fpr("ceil.l.d",(fd,fs)) 12096 | CEIL_L_S(fd,fs) => op2fpr("ceil.l.s",(fd,fs)) 12097 | CEIL_W_D(fd,fs) => op2fpr("ceil.w.d",(fd,fs)) 12098 | CEIL_W_S(fd,fs) => op2fpr("ceil.w.s",(fd,fs)) 12099 | CFC1(rt,fs) => op2rcfpr("cfc1",(rt,fs)) 12100 | CTC1(rt,fs) => op2rcfpr("ctc1",(rt,fs)) 12101 | CVT_D_L(fd,fs) => op2fpr("cvt.d.l",(fd,fs)) 12102 | CVT_D_S(fd,fs) => op2fpr("cvt.d.s",(fd,fs)) 12103 | CVT_D_W(fd,fs) => op2fpr("cvt.d.w",(fd,fs)) 12104 | CVT_L_D(fd,fs) => op2fpr("cvt.l.d",(fd,fs)) 12105 | CVT_L_S(fd,fs) => op2fpr("cvt.l.s",(fd,fs)) 12106 | CVT_S_L(fd,fs) => op2fpr("cvt.s.l",(fd,fs)) 12107 | CVT_S_D(fd,fs) => op2fpr("cvt.s.d",(fd,fs)) 12108 | CVT_S_W(fd,fs) => op2fpr("cvt.s.w",(fd,fs)) 12109 | CVT_W_D(fd,fs) => op2fpr("cvt.w.d",(fd,fs)) 12110 | CVT_W_S(fd,fs) => op2fpr("cvt.w.s",(fd,fs)) 12111 | DIV_D(fd,(fs,ft)) => op3fpr("div.d",(fd,(fs,ft))) 12112 | DIV_S(fd,(fs,ft)) => op3fpr("div.s",(fd,(fs,ft))) 12113 | DMFC1(rt,fs) => op2rfpr("dmfc1",(rt,fs)) 12114 | DMTC1(rt,fs) => op2rfpr("dmtc1",(rt,fs)) 12115 | FLOOR_L_D(fd,fs) => op2fpr("floor.l.d",(fd,fs)) 12116 | FLOOR_L_S(fd,fs) => op2fpr("floor.l.s",(fd,fs)) 12117 | FLOOR_W_D(fd,fs) => op2fpr("floor.w.d",(fd,fs)) 12118 | FLOOR_W_S(fd,fs) => op2fpr("floor.w.s",(fd,fs)) 12119 | LDC1(ft,(offset,base)) => opfpmem 16 ("ldc1",(ft,(base,offset))) 12120 | LDXC1(fs,(index,base)) => opfpmem2("ldxc1",(fs,(base,index))) 12121 | LWC1(ft,(offset,base)) => opfpmem 16 ("lwc1",(ft,(base,offset))) 12122 | LWXC1(ft,(index,base)) => opfpmem2("lwxc1",(ft,(base,index))) 12123 | MFC1(rt,fs) => op2rfpr("mfc1",(rt,fs)) 12124 | MADD_D(fd,(fr,(fs,ft))) => op4fpr("madd.d",(fd,(fr,(fs,ft)))) 12125 | MADD_S(fd,(fr,(fs,ft))) => op4fpr("madd.s",(fd,(fr,(fs,ft)))) 12126 | MSUB_D(fd,(fr,(fs,ft))) => op4fpr("msub.d",(fd,(fr,(fs,ft)))) 12127 | MSUB_S(fd,(fr,(fs,ft))) => op4fpr("msub.s",(fd,(fr,(fs,ft)))) 12128 | MOV_D(fd,fs) => op2fpr("mov.d",(fd,fs)) 12129 | MOV_S(fd,fs) => op2fpr("mov.s",(fd,fs)) 12130 | MOVF(rd,(rs,cc)) => 12131 String.concat 12132 [op2r("movf",(rd,rs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] 12133 | MOVF_D(fd,(fs,cc)) => 12134 String.concat 12135 [op2fpr("movf.d",(fd,fs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] 12136 | MOVF_S(fd,(fs,cc)) => 12137 String.concat 12138 [op2fpr("movf.s",(fd,fs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] 12139 | MOVN_D(fd,(fs,rt)) => 12140 String.concat[op2fpr("movn.d",(fd,fs)),", ",reg_name rt] 12141 | MOVN_S(fd,(fs,rt)) => 12142 String.concat[op2fpr("movn.s",(fd,fs)),", ",reg_name rt] 12143 | MOVT(rd,(rs,cc)) => 12144 String.concat 12145 [op2r("movt",(rd,rs)),", ",", ","$fcc",Nat.toString(BitsN.toNat cc)] 12146 | MOVT_D(fd,(fs,cc)) => 12147 String.concat 12148 [op2fpr("movt.d",(fd,fs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] 12149 | MOVT_S(fd,(fs,cc)) => 12150 String.concat 12151 [op2fpr("movt.s",(fd,fs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] 12152 | MOVZ_D(fd,(fs,rt)) => 12153 String.concat[op2fpr("movz.d",(fd,fs)),", ",reg_name rt] 12154 | MOVZ_S(fd,(fs,rt)) => 12155 String.concat[op2fpr("movz.s",(fd,fs)),", ",reg_name rt] 12156 | MTC1(rt,fs) => op2rfpr("mtc1",(rt,fs)) 12157 | MUL_D(fd,(fs,ft)) => op3fpr("mul.d",(fd,(fs,ft))) 12158 | MUL_S(fd,(fs,ft)) => op3fpr("mul.s",(fd,(fs,ft))) 12159 | NEG_D(fd,fs) => op2fpr("neg.d",(fd,fs)) 12160 | NEG_S(fd,fs) => op2fpr("neg.s",(fd,fs)) 12161 | ROUND_L_D(fd,fs) => op2fpr("round.l.d",(fd,fs)) 12162 | ROUND_L_S(fd,fs) => op2fpr("round.l.s",(fd,fs)) 12163 | ROUND_W_D(fd,fs) => op2fpr("round.w.d",(fd,fs)) 12164 | ROUND_W_S(fd,fs) => op2fpr("round.w.s",(fd,fs)) 12165 | SDC1(ft,(offset,base)) => opfpmem 16 ("sdc1",(ft,(base,offset))) 12166 | SDXC1(fs,(index,base)) => opfpmem2("sdxc1",(fs,(base,index))) 12167 | SWC1(ft,(offset,base)) => opfpmem 16 ("swc1",(ft,(base,offset))) 12168 | SWXC1(ft,(offset,base)) => opfpmem2("swxc1",(ft,(base,offset))) 12169 | SUB_D(fd,(fs,ft)) => op3fpr("sub.d",(fd,(fs,ft))) 12170 | SUB_S(fd,(fs,ft)) => op3fpr("sub.s",(fd,(fs,ft))) 12171 | SQRT_D(fd,fs) => op2fpr("sqrt.d",(fd,fs)) 12172 | SQRT_S(fd,fs) => op2fpr("sqrt.s",(fd,fs)) 12173 | TRUNC_L_D(fd,fs) => op2fpr("trunc.l.d",(fd,fs)) 12174 | TRUNC_L_S(fd,fs) => op2fpr("trunc.l.s",(fd,fs)) 12175 | TRUNC_W_D(fd,fs) => op2fpr("trunc.w.d",(fd,fs)) 12176 | TRUNC_W_S(fd,fs) => op2fpr("trunc.w.s",(fd,fs)) 12177 | UnknownFPInstruction => "Unknown floating point instruction"; 12178 12179fun instructionToString i = 12180 case i of 12181 Shift(SLL(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x0,5)))) => "nop" 12182 | Shift(SLL(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1,5)))) => "ssnop" 12183 | Shift(SLL(rt,(rd,imm5))) => op2ri 5 ("sll",(rd,(rt,imm5))) 12184 | Shift(SRL(rt,(rd,imm5))) => op2ri 5 ("srl",(rd,(rt,imm5))) 12185 | Shift(SRA(rt,(rd,imm5))) => op2ri 5 ("sra",(rd,(rt,imm5))) 12186 | Shift(SLLV(rs,(rt,rd))) => op3r("sllv",(rd,(rt,rs))) 12187 | Shift(SRLV(rs,(rt,rd))) => op3r("srlv",(rd,(rt,rs))) 12188 | Shift(SRAV(rs,(rt,rd))) => op3r("srav",(rd,(rt,rs))) 12189 | Branch(JR rs) => op1r("jr",rs) 12190 | Branch(JALR(rs,rd)) => op2r("jalr",(rd,rs)) 12191 | MultDiv(MFHI rd) => op1r("mfhi",rd) 12192 | MultDiv(MTHI rd) => op1r("mthi",rd) 12193 | MultDiv(MFLO rs) => op1r("mflo",rs) 12194 | MultDiv(MTLO rs) => op1r("mtlo",rs) 12195 | Shift(DSLLV(rs,(rt,rd))) => op3r("dsllv",(rd,(rt,rs))) 12196 | Shift(DSRLV(rs,(rt,rd))) => op3r("dsrlv",(rd,(rt,rs))) 12197 | Shift(DSRAV(rs,(rt,rd))) => op3r("dsrav",(rd,(rt,rs))) 12198 | MultDiv(MADD(rs,rt)) => op2r("madd",(rs,rt)) 12199 | MultDiv(MADDU(rs,rt)) => op2r("maddu",(rs,rt)) 12200 | MultDiv(MSUB(rs,rt)) => op2r("msub",(rs,rt)) 12201 | MultDiv(MSUBU(rs,rt)) => op2r("msubu",(rs,rt)) 12202 | MultDiv(MUL(rs,(rt,rd))) => op3r("mul",(rd,(rs,rt))) 12203 | MultDiv(MULT(rs,rt)) => op2r("mult",(rs,rt)) 12204 | MultDiv(MULTU(rs,rt)) => op2r("multu",(rs,rt)) 12205 | MultDiv(DIV(rs,rt)) => op2r("div",(rs,rt)) 12206 | MultDiv(DIVU(rs,rt)) => op2r("divu",(rs,rt)) 12207 | MultDiv(DMULT(rs,rt)) => op2r("dmult",(rs,rt)) 12208 | MultDiv(DMULTU(rs,rt)) => op2r("dmultu",(rs,rt)) 12209 | MultDiv(DDIV(rs,rt)) => op2r("ddiv",(rs,rt)) 12210 | MultDiv(DDIVU(rs,rt)) => op2r("ddivu",(rs,rt)) 12211 | ArithR(MOVN(rs,(rt,rd))) => op3r("movn",(rd,(rs,rt))) 12212 | ArithR(MOVZ(rs,(rt,rd))) => op3r("movz",(rd,(rs,rt))) 12213 | ArithR(ADD(rs,(rt,rd))) => op3r("add",(rd,(rs,rt))) 12214 | ArithR(ADDU(rs,(rt,rd))) => op3r("addu",(rd,(rs,rt))) 12215 | ArithR(SUB(rs,(rt,rd))) => op3r("sub",(rd,(rs,rt))) 12216 | ArithR(SUBU(rs,(rt,rd))) => op3r("subu",(rd,(rs,rt))) 12217 | ArithR(AND(rs,(rt,rd))) => op3r("and",(rd,(rs,rt))) 12218 | ArithR(OR(rs,(rt,rd))) => op3r("or",(rd,(rs,rt))) 12219 | ArithR(XOR(rs,(rt,rd))) => op3r("xor",(rd,(rs,rt))) 12220 | ArithR(NOR(rs,(rt,rd))) => op3r("nor",(rd,(rs,rt))) 12221 | ArithR(SLT(rs,(rt,rd))) => op3r("slt",(rd,(rs,rt))) 12222 | ArithR(SLTU(rs,(rt,rd))) => op3r("sltu",(rd,(rs,rt))) 12223 | ArithR(DADD(rs,(rt,rd))) => op3r("dadd",(rd,(rs,rt))) 12224 | ArithR(DADDU(rs,(rt,rd))) => op3r("daddu",(rd,(rs,rt))) 12225 | ArithR(DSUB(rs,(rt,rd))) => op3r("dsub",(rd,(rs,rt))) 12226 | ArithR(DSUBU(rs,(rt,rd))) => op3r("dsubu",(rd,(rs,rt))) 12227 | Trap(TGE(rs,rt)) => op2r("tge",(rs,rt)) 12228 | Trap(TGEU(rs,rt)) => op2r("tgeu",(rs,rt)) 12229 | Trap(TLT(rs,rt)) => op2r("tlt",(rs,rt)) 12230 | Trap(TLTU(rs,rt)) => op2r("tltu",(rs,rt)) 12231 | Trap(TEQ(rs,rt)) => op2r("teq",(rs,rt)) 12232 | Trap(TNE(rs,rt)) => op2r("tne",(rs,rt)) 12233 | Shift(DSLL(rt,(rd,imm5))) => op2ri 5 ("dsll",(rd,(rt,imm5))) 12234 | Shift(DSRL(rt,(rd,imm5))) => op2ri 5 ("dsrl",(rd,(rt,imm5))) 12235 | Shift(DSRA(rt,(rd,imm5))) => op2ri 5 ("dsra",(rd,(rt,imm5))) 12236 | Shift(DSLL32(rt,(rd,imm5))) => op2ri 5 ("dsll32",(rd,(rt,imm5))) 12237 | Shift(DSRL32(rt,(rd,imm5))) => op2ri 5 ("dsrl32",(rd,(rt,imm5))) 12238 | Shift(DSRA32(rt,(rd,imm5))) => op2ri 5 ("dsra32",(rd,(rt,imm5))) 12239 | Branch(BLTZ(rs,imm)) => op1rai 16 ("bltz",(rs,imm)) 12240 | Branch(BGEZ(rs,imm)) => op1rai 16 ("bgez",(rs,imm)) 12241 | Branch(BLTZL(rs,imm)) => op1rlai 16 ("bltzl",(rs,imm)) 12242 | Branch(BGEZL(rs,imm)) => op1rlai 16 ("bgezl",(rs,imm)) 12243 | Trap(TGEI(rs,imm)) => op1ri 16 ("tgei",(rs,imm)) 12244 | Trap(TGEIU(rs,imm)) => op1ri 16 ("tgeiu",(rs,imm)) 12245 | Trap(TLTI(rs,imm)) => op1ri 16 ("tlti",(rs,imm)) 12246 | Trap(TLTIU(rs,imm)) => op1ri 16 ("tltiu",(rs,imm)) 12247 | Trap(TEQI(rs,imm)) => op1ri 16 ("teqi",(rs,imm)) 12248 | Trap(TNEI(rs,imm)) => op1ri 16 ("tnei",(rs,imm)) 12249 | Branch(BLTZAL(rs,imm)) => op1rai 16 ("bltzal",(rs,imm)) 12250 | Branch(BGEZAL(rs,imm)) => op1rai 16 ("bgezal",(rs,imm)) 12251 | Branch(BLTZALL(rs,imm)) => op1rlai 16 ("bltzall",(rs,imm)) 12252 | Branch(BGEZALL(rs,imm)) => op1rlai 16 ("bgezall",(rs,imm)) 12253 | Branch(J imm) => op1ai 26 ("j",imm) 12254 | Branch(JAL imm) => op1ai 26 ("jal",imm) 12255 | CP(MFC0(rt,(rd,sel))) => op2roi 3 ("mfc0",(rt,(rd,sel))) 12256 | CP(DMFC0(rt,(rd,sel))) => op2roi 3 ("dmfc0",(rt,(rd,sel))) 12257 | CP(MTC0(rt,(rd,sel))) => op2roi 3 ("mtc0",(rt,(rd,sel))) 12258 | CP(DMTC0(rt,(rd,sel))) => op2roi 3 ("dmtc0",(rt,(rd,sel))) 12259 | Branch(BEQ(BitsN.B(0x0,5),(BitsN.B(0x0,5),imm))) => 12260 op1ai 16 ("b",imm) 12261 | Branch(BEQ(rs,(rt,imm))) => op2rai 16 ("beq",(rs,(rt,imm))) 12262 | Branch(BNE(rs,(rt,imm))) => op2rai 16 ("bne",(rs,(rt,imm))) 12263 | Branch(BLEZ(rs,imm)) => op1rai 16 ("blez",(rs,imm)) 12264 | Branch(BGTZ(rs,imm)) => op1rai 16 ("bgtz",(rs,imm)) 12265 | ArithI(ADDI(rs,(rt,imm))) => op2ri 16 ("addi",(rt,(rs,imm))) 12266 | ArithI(ADDIU(rs,(rt,imm))) => op2ri 16 ("addiu",(rt,(rs,imm))) 12267 | ArithI(SLTI(rs,(rt,imm))) => op2ri 16 ("slti",(rt,(rs,imm))) 12268 | ArithI(SLTIU(rs,(rt,imm))) => op2ri 16 ("sltiu",(rt,(rs,imm))) 12269 | ArithI(ANDI(rs,(rt,imm))) => op2ri 16 ("andi",(rt,(rs,imm))) 12270 | ArithI(ORI(rs,(rt,imm))) => op2ri 16 ("ori",(rt,(rs,imm))) 12271 | ArithI(XORI(rs,(rt,imm))) => op2ri 16 ("xori",(rt,(rs,imm))) 12272 | ArithI(LUI(rt,imm)) => op1ri 16 ("lui",(rt,imm)) 12273 | Branch(BEQL(rs,(rt,imm))) => op2rlai 16 ("beql",(rs,(rt,imm))) 12274 | Branch(BNEL(rs,(rt,imm))) => op2rlai 16 ("bnel",(rs,(rt,imm))) 12275 | Branch(BLEZL(rs,imm)) => op1rlai 16 ("blezl",(rs,imm)) 12276 | Branch(BGTZL(rs,imm)) => op1rlai 16 ("bgtzl",(rs,imm)) 12277 | ArithI(DADDI(rs,(rt,imm))) => op2ri 16 ("daddi",(rt,(rs,imm))) 12278 | ArithI(DADDIU(rs,(rt,imm))) => op2ri 16 ("daddiu",(rt,(rs,imm))) 12279 | Load(LDL(rs,(rt,imm))) => opmem 16 ("ldl",(rt,(rs,imm))) 12280 | Load(LDR(rs,(rt,imm))) => opmem 16 ("ldr",(rt,(rs,imm))) 12281 | Load(LB(rs,(rt,imm))) => opmem 16 ("lb",(rt,(rs,imm))) 12282 | Load(LH(rs,(rt,imm))) => opmem 16 ("lh",(rt,(rs,imm))) 12283 | Load(LWL(rs,(rt,imm))) => opmem 16 ("lwl",(rt,(rs,imm))) 12284 | Load(LW(rs,(rt,imm))) => opmem 16 ("lw",(rt,(rs,imm))) 12285 | Load(LBU(rs,(rt,imm))) => opmem 16 ("lbu",(rt,(rs,imm))) 12286 | Load(LHU(rs,(rt,imm))) => opmem 16 ("lhu",(rt,(rs,imm))) 12287 | Load(LWR(rs,(rt,imm))) => opmem 16 ("lwr",(rt,(rs,imm))) 12288 | Load(LWU(rs,(rt,imm))) => opmem 16 ("lwu",(rt,(rs,imm))) 12289 | Store(SB(rs,(rt,imm))) => opmem 16 ("sb",(rt,(rs,imm))) 12290 | Store(SH(rs,(rt,imm))) => opmem 16 ("sh",(rt,(rs,imm))) 12291 | Store(SWL(rs,(rt,imm))) => opmem 16 ("swl",(rt,(rs,imm))) 12292 | Store(SW(rs,(rt,imm))) => opmem 16 ("sw",(rt,(rs,imm))) 12293 | Store(SDL(rs,(rt,imm))) => opmem 16 ("sdl",(rt,(rs,imm))) 12294 | Store(SDR(rs,(rt,imm))) => opmem 16 ("sdr",(rt,(rs,imm))) 12295 | Store(SWR(rs,(rt,imm))) => opmem 16 ("swr",(rt,(rs,imm))) 12296 | Load(LL(rs,(rt,imm))) => opmem 16 ("ll",(rt,(rs,imm))) 12297 | Load(LLD(rs,(rt,imm))) => opmem 16 ("lld",(rt,(rs,imm))) 12298 | Load(LD(rs,(rt,imm))) => opmem 16 ("ld",(rt,(rs,imm))) 12299 | Store(SC(rs,(rt,imm))) => opmem 16 ("sc",(rt,(rs,imm))) 12300 | Store(SCD(rs,(rt,imm))) => opmem 16 ("scd",(rt,(rs,imm))) 12301 | Store(SD(rs,(rt,imm))) => opmem 16 ("sd",(rt,(rs,imm))) 12302 | CACHE(rs,(opn,imm)) => 12303 String.concat 12304 ["cache ", 12305 (if BitsN.<+(opn,BitsN.B(0xA,5)) then "" else "0x") 12306 ^ 12307 (BitsN.toHexString opn),", ", 12308 (if BitsN.<+(imm,BitsN.B(0xA,16)) then "" else "0x") 12309 ^ 12310 (BitsN.toHexString imm),"(",reg_name rs,")"] 12311 | COP1 x => COP1InstructionToString x 12312 | SYSCALL => "syscall" 12313 | BREAK => "break" 12314 | SYNC imm5 => 12315 String.concat 12316 ["sync ",if BitsN.<+(imm5,BitsN.B(0xA,5)) then "" else "0x", 12317 BitsN.toHexString imm5] 12318 | TLBR => "tlbr" 12319 | TLBWI => "tlbwi" 12320 | TLBWR => "tlbwr" 12321 | TLBP => "tlbp" 12322 | ERET => "eret" 12323 | RDHWR(rt,rd) => op2r("rdhwr",(rt,rd)) 12324 | WAIT => "wait" 12325 | Unpredictable => "???" 12326 | ReservedInstruction => "???"; 12327 12328fun skipSpaces s = L3.snd(L3.splitl(fn c => Char.isSpace c,s)); 12329 12330fun stripSpaces s = 12331 L3.fst(L3.splitr(fn c => Char.isSpace c,skipSpaces s)); 12332 12333fun p_number s = 12334 case String.explode(stripSpaces s) of 12335 #"0" :: (#"b" :: t) => Nat.fromBinString(String.implode t) 12336 | #"0" :: (#"x" :: t) => Nat.fromHexString(String.implode t) 12337 | _ => Nat.fromString s; 12338 12339fun p_tokens s = 12340 let 12341 val (l,r) = 12342 L3.splitl 12343 (fn c => not(Char.isSpace c), 12344 L3.lowercase(L3.snd(L3.splitl(fn c => Char.isSpace c,s)))) 12345 val r = L3.uncurry String.fields (fn c => c = #",",r) 12346 val r = 12347 if ((L3.length r) = 1) andalso ((stripSpaces(List.hd r)) = "") 12348 then [] 12349 else r 12350 in 12351 l :: r 12352 end; 12353 12354fun p_fp_cc s = 12355 case String.explode(stripSpaces s) of 12356 #"$" :: (#"f" :: (#"c" :: (#"c" :: r))) => 12357 (case Nat.fromString(String.implode r) of 12358 Option.SOME n => 12359 (if Nat.<(n,8) then Option.SOME(BitsN.fromNat(n,3)) else NONE) 12360 | NONE => NONE) 12361 | _ => NONE; 12362 12363fun p_fp_reg s = 12364 case String.explode(stripSpaces s) of 12365 #"$" :: (#"f" :: r) => 12366 (case Nat.fromString(String.implode r) of 12367 Option.SOME n => 12368 (if Nat.<(n,32) 12369 then Option.SOME(BitsN.fromNat(n,5)) 12370 else NONE) 12371 | NONE => NONE) 12372 | _ => NONE; 12373 12374fun p_cfp_reg s = 12375 case String.explode(stripSpaces s) of 12376 #"$" :: r => 12377 (case Nat.fromString(String.implode r) of 12378 Option.SOME n => 12379 (if Nat.<(n,32) 12380 then Option.SOME(BitsN.fromNat(n,5)) 12381 else NONE) 12382 | NONE => NONE) 12383 | _ => NONE; 12384 12385fun p_reg s = 12386 case String.explode(stripSpaces s) of 12387 #"$" :: n => 12388 (case String.explode(String.implode n) of 12389 [#"z",#"e",#"r",#"o"] => Option.SOME(BitsN.B(0x0,5)) 12390 | [#"a",#"t"] => Option.SOME(BitsN.B(0x1,5)) 12391 | [#"v",#"0"] => Option.SOME(BitsN.B(0x2,5)) 12392 | [#"v",#"1"] => Option.SOME(BitsN.B(0x3,5)) 12393 | [#"a",#"0"] => Option.SOME(BitsN.B(0x4,5)) 12394 | [#"a",#"1"] => Option.SOME(BitsN.B(0x5,5)) 12395 | [#"a",#"2"] => Option.SOME(BitsN.B(0x6,5)) 12396 | [#"a",#"3"] => Option.SOME(BitsN.B(0x7,5)) 12397 | [#"t",#"0"] => Option.SOME(BitsN.B(0x8,5)) 12398 | [#"t",#"1"] => Option.SOME(BitsN.B(0x9,5)) 12399 | [#"t",#"2"] => Option.SOME(BitsN.B(0xA,5)) 12400 | [#"t",#"3"] => Option.SOME(BitsN.B(0xB,5)) 12401 | [#"t",#"4"] => Option.SOME(BitsN.B(0xC,5)) 12402 | [#"t",#"5"] => Option.SOME(BitsN.B(0xD,5)) 12403 | [#"t",#"6"] => Option.SOME(BitsN.B(0xE,5)) 12404 | [#"t",#"7"] => Option.SOME(BitsN.B(0xF,5)) 12405 | [#"s",#"0"] => Option.SOME(BitsN.B(0x10,5)) 12406 | [#"s",#"1"] => Option.SOME(BitsN.B(0x11,5)) 12407 | [#"s",#"2"] => Option.SOME(BitsN.B(0x12,5)) 12408 | [#"s",#"3"] => Option.SOME(BitsN.B(0x13,5)) 12409 | [#"s",#"4"] => Option.SOME(BitsN.B(0x14,5)) 12410 | [#"s",#"5"] => Option.SOME(BitsN.B(0x15,5)) 12411 | [#"s",#"6"] => Option.SOME(BitsN.B(0x16,5)) 12412 | [#"s",#"7"] => Option.SOME(BitsN.B(0x17,5)) 12413 | [#"t",#"8"] => Option.SOME(BitsN.B(0x18,5)) 12414 | [#"t",#"9"] => Option.SOME(BitsN.B(0x19,5)) 12415 | [#"k",#"0"] => Option.SOME(BitsN.B(0x1A,5)) 12416 | [#"k",#"1"] => Option.SOME(BitsN.B(0x1B,5)) 12417 | [#"g",#"p"] => Option.SOME(BitsN.B(0x1C,5)) 12418 | [#"s",#"p"] => Option.SOME(BitsN.B(0x1D,5)) 12419 | [#"f",#"p"] => Option.SOME(BitsN.B(0x1E,5)) 12420 | [#"r",#"a"] => Option.SOME(BitsN.B(0x1F,5)) 12421 | #"r" :: r => 12422 (case Nat.fromString(String.implode r) of 12423 Option.SOME n => 12424 (if Nat.<(n,32) 12425 then Option.SOME(BitsN.fromNat(n,5)) 12426 else NONE) 12427 | NONE => NONE) 12428 | _ => NONE) 12429 | _ => NONE; 12430 12431fun p_reg2 l = 12432 case l of 12433 [r1,r2] => 12434 (case (p_reg r1,p_reg r2) of 12435 (Option.SOME a,Option.SOME b) => Option.SOME(a,b) 12436 | _ => NONE) 12437 | _ => NONE; 12438 12439fun p_address s = 12440 let 12441 val (l,r) = L3.splitl(fn c => not(c = #"("),stripSpaces s) 12442 in 12443 case (p_number l,String.explode r) of 12444 (Option.SOME n,#"(" :: r) => 12445 let 12446 val i = BitsN.fromNat(n,16) 12447 val (r,e) = L3.splitr(fn c => c = #")",String.implode r) 12448 in 12449 if (n = (BitsN.toNat i)) andalso (e = ")") 12450 then case p_reg r of 12451 Option.SOME x => Option.SOME(i,x) 12452 | NONE => NONE 12453 else NONE 12454 end 12455 | _ => NONE 12456 end; 12457 12458fun p_index_address s = 12459 let 12460 val (l,r) = L3.splitl(fn c => not(c = #"("),stripSpaces s) 12461 in 12462 case (p_reg l,String.explode r) of 12463 (Option.SOME r1,#"(" :: r) => 12464 let 12465 val (r,e) = L3.splitr(fn c => c = #")",String.implode r) 12466 in 12467 if e = ")" 12468 then case p_reg r of 12469 Option.SOME r2 => Option.SOME(r1,r2) 12470 | NONE => NONE 12471 else NONE 12472 end 12473 | _ => NONE 12474 end; 12475 12476fun p_arg0 s = 12477 case s of 12478 "nop" => 12479 OK(Shift(SLL(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x0,5))))) 12480 | "ssnop" => 12481 OK(Shift(SLL(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1,5))))) 12482 | "syscall" => OK SYSCALL 12483 | "break" => OK BREAK 12484 | "tlbr" => OK TLBR 12485 | "tlbwi" => OK TLBWI 12486 | "tlbwr" => OK TLBWR 12487 | "tlbp" => OK TLBP 12488 | "eret" => OK ERET 12489 | "wait" => OK WAIT 12490 | _ => FAIL("Unrecognised 0-arg mnemonic: " ^ s); 12491 12492fun p_r1 (x,(s,r)) = 12493 case x of 12494 "jr" => OK(Branch(JR r)) 12495 | "mfhi" => OK(MultDiv(MFHI r)) 12496 | "mthi" => OK(MultDiv(MTHI r)) 12497 | "mflo" => OK(MultDiv(MFLO r)) 12498 | "mtlo" => OK(MultDiv(MTLO r)) 12499 | _ => FAIL("Syntax error: " ^ s); 12500 12501fun p_r2 (x,(s,(rs,rt))) = 12502 case x of 12503 "jalr" => OK(Branch(JALR(rt,rs))) 12504 | "madd" => OK(MultDiv(MADD(rs,rt))) 12505 | "maddu" => OK(MultDiv(MADDU(rs,rt))) 12506 | "msub" => OK(MultDiv(MSUB(rs,rt))) 12507 | "msubu" => OK(MultDiv(MSUBU(rs,rt))) 12508 | "mult" => OK(MultDiv(MULT(rs,rt))) 12509 | "multu" => OK(MultDiv(MULTU(rs,rt))) 12510 | "div" => OK(MultDiv(DIV(rs,rt))) 12511 | "divu" => OK(MultDiv(DIVU(rs,rt))) 12512 | "dmult" => OK(MultDiv(DMULT(rs,rt))) 12513 | "dmultu" => OK(MultDiv(DMULTU(rs,rt))) 12514 | "ddiv" => OK(MultDiv(DDIV(rs,rt))) 12515 | "ddivu" => OK(MultDiv(DDIVU(rs,rt))) 12516 | "tge" => OK(Trap(TGE(rs,rt))) 12517 | "tgeu" => OK(Trap(TGEU(rs,rt))) 12518 | "tlt" => OK(Trap(TLT(rs,rt))) 12519 | "tltu" => OK(Trap(TLTU(rs,rt))) 12520 | "teq" => OK(Trap(TEQ(rs,rt))) 12521 | "tne" => OK(Trap(TNE(rs,rt))) 12522 | "rdhwr" => OK(RDHWR(rs,rt)) 12523 | _ => FAIL("Syntax error: " ^ s); 12524 12525fun p_rcfpr (x,(s,(rt,fs))) = 12526 case x of 12527 "cfc1" => OK(COP1(CFC1(rt,fs))) 12528 | "ctc1" => OK(COP1(CTC1(rt,fs))) 12529 | _ => FAIL("Syntax error: " ^ s); 12530 12531fun p_rfpr2 (x,(s,(rt,fs))) = 12532 case x of 12533 "mfc1" => OK(COP1(MFC1(rt,fs))) 12534 | "mtc1" => OK(COP1(MTC1(rt,fs))) 12535 | "dmfc1" => OK(COP1(DMFC1(rt,fs))) 12536 | "dmtc1" => OK(COP1(DMTC1(rt,fs))) 12537 | _ => FAIL("Syntax error: " ^ s); 12538 12539fun p_fpr2 (x,(s,(fd,fs))) = 12540 case x of 12541 "abs.d" => OK(COP1(ABS_D(fd,fs))) 12542 | "abs.s" => OK(COP1(ABS_S(fd,fs))) 12543 | "c.f.d" => 12544 OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x0,3),BitsN.B(0x0,3)))))) 12545 | "c.un.d" => 12546 OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x1,3),BitsN.B(0x0,3)))))) 12547 | "c.eq.d" => 12548 OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x2,3),BitsN.B(0x0,3)))))) 12549 | "c.ueq.d" => 12550 OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x3,3),BitsN.B(0x0,3)))))) 12551 | "c.olt.d" => 12552 OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x4,3),BitsN.B(0x0,3)))))) 12553 | "c.ult.d" => 12554 OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x5,3),BitsN.B(0x0,3)))))) 12555 | "c.ole.d" => 12556 OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x6,3),BitsN.B(0x0,3)))))) 12557 | "c.ule.d" => 12558 OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x7,3),BitsN.B(0x0,3)))))) 12559 | "c.f.s" => 12560 OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x0,3),BitsN.B(0x0,3)))))) 12561 | "c.un.s" => 12562 OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x1,3),BitsN.B(0x0,3)))))) 12563 | "c.eq.s" => 12564 OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x2,3),BitsN.B(0x0,3)))))) 12565 | "c.ueq.s" => 12566 OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x3,3),BitsN.B(0x0,3)))))) 12567 | "c.olt.s" => 12568 OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x4,3),BitsN.B(0x0,3)))))) 12569 | "c.ult.s" => 12570 OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x5,3),BitsN.B(0x0,3)))))) 12571 | "c.ole.s" => 12572 OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x6,3),BitsN.B(0x0,3)))))) 12573 | "c.ule.s" => 12574 OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x7,3),BitsN.B(0x0,3)))))) 12575 | "ceil.l.d" => OK(COP1(CEIL_L_D(fd,fs))) 12576 | "ceil.l.s" => OK(COP1(CEIL_L_S(fd,fs))) 12577 | "ceil.w.d" => OK(COP1(CEIL_W_D(fd,fs))) 12578 | "ceil.w.s" => OK(COP1(CEIL_W_S(fd,fs))) 12579 | "cvt.d.l" => OK(COP1(CVT_D_L(fd,fs))) 12580 | "cvt.d.s" => OK(COP1(CVT_D_S(fd,fs))) 12581 | "cvt.d.w" => OK(COP1(CVT_D_W(fd,fs))) 12582 | "cvt.l.d" => OK(COP1(CVT_L_D(fd,fs))) 12583 | "cvt.l.s" => OK(COP1(CVT_L_S(fd,fs))) 12584 | "cvt.s.l" => OK(COP1(CVT_S_L(fd,fs))) 12585 | "cvt.s.d" => OK(COP1(CVT_S_D(fd,fs))) 12586 | "cvt.s.w" => OK(COP1(CVT_S_W(fd,fs))) 12587 | "cvt.w.d" => OK(COP1(CVT_W_D(fd,fs))) 12588 | "cvt.w.s" => OK(COP1(CVT_W_S(fd,fs))) 12589 | "floor.l.d" => OK(COP1(FLOOR_L_D(fd,fs))) 12590 | "floor.l.s" => OK(COP1(FLOOR_L_S(fd,fs))) 12591 | "floor.w.d" => OK(COP1(FLOOR_W_D(fd,fs))) 12592 | "floor.w.s" => OK(COP1(FLOOR_W_S(fd,fs))) 12593 | "mov.d" => OK(COP1(MOV_D(fd,fs))) 12594 | "mov.s" => OK(COP1(MOV_S(fd,fs))) 12595 | "neg.d" => OK(COP1(NEG_D(fd,fs))) 12596 | "neg.s" => OK(COP1(NEG_S(fd,fs))) 12597 | "round.l.d" => OK(COP1(ROUND_L_D(fd,fs))) 12598 | "round.l.s" => OK(COP1(ROUND_L_S(fd,fs))) 12599 | "round.w.d" => OK(COP1(ROUND_W_D(fd,fs))) 12600 | "round.w.s" => OK(COP1(ROUND_W_S(fd,fs))) 12601 | "sqrt.d" => OK(COP1(SQRT_D(fd,fs))) 12602 | "sqrt.s" => OK(COP1(SQRT_S(fd,fs))) 12603 | "trunc.l.d" => OK(COP1(TRUNC_L_D(fd,fs))) 12604 | "trunc.l.s" => OK(COP1(TRUNC_L_S(fd,fs))) 12605 | "trunc.w.d" => OK(COP1(TRUNC_W_D(fd,fs))) 12606 | "trunc.w.s" => OK(COP1(TRUNC_W_S(fd,fs))) 12607 | _ => FAIL("Syntax error: " ^ s); 12608 12609fun p_ccfpr2 (x,(s,(cc,(fd,fs)))) = 12610 case x of 12611 "c.f.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x0,3),cc))))) 12612 | "c.un.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x1,3),cc))))) 12613 | "c.eq.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x2,3),cc))))) 12614 | "c.ueq.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x3,3),cc))))) 12615 | "c.olt.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x4,3),cc))))) 12616 | "c.ult.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x5,3),cc))))) 12617 | "c.ole.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x6,3),cc))))) 12618 | "c.ule.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x7,3),cc))))) 12619 | "c.f.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x0,3),cc))))) 12620 | "c.un.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x1,3),cc))))) 12621 | "c.eq.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x2,3),cc))))) 12622 | "c.ueq.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x3,3),cc))))) 12623 | "c.olt.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x4,3),cc))))) 12624 | "c.ult.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x5,3),cc))))) 12625 | "c.ole.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x6,3),cc))))) 12626 | "c.ule.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x7,3),cc))))) 12627 | _ => FAIL("Syntax error: " ^ s); 12628 12629fun p_r2cc (x,(s,(rd,(rs,cc)))) = 12630 case x of 12631 "movf" => OK(COP1(MOVF(rd,(rs,cc)))) 12632 | "movt" => OK(COP1(MOVT(rd,(rs,cc)))) 12633 | _ => FAIL("Syntax error: " ^ s); 12634 12635fun p_fpr2r (x,(s,(fd,(fs,rt)))) = 12636 case x of 12637 "movn.d" => OK(COP1(MOVN_D(fd,(fs,rt)))) 12638 | "movn.s" => OK(COP1(MOVN_S(fd,(fs,rt)))) 12639 | "movz.d" => OK(COP1(MOVZ_D(fd,(fs,rt)))) 12640 | "movz.s" => OK(COP1(MOVZ_S(fd,(fs,rt)))) 12641 | _ => FAIL("Syntax error: " ^ s); 12642 12643fun p_fpr2cc (x,(s,(fd,(fs,cc)))) = 12644 case x of 12645 "movf.d" => OK(COP1(MOVF_D(fd,(fs,cc)))) 12646 | "movf.s" => OK(COP1(MOVF_S(fd,(fs,cc)))) 12647 | "movt.d" => OK(COP1(MOVT_D(fd,(fs,cc)))) 12648 | "movt.s" => OK(COP1(MOVT_S(fd,(fs,cc)))) 12649 | _ => FAIL("Syntax error: " ^ s); 12650 12651fun p_r3 (x,(s,(rd,(rs,rt)))) = 12652 case x of 12653 "sllv" => OK(Shift(SLLV(rt,(rs,rd)))) 12654 | "srlv" => OK(Shift(SRLV(rt,(rs,rd)))) 12655 | "srav" => OK(Shift(SRAV(rt,(rs,rd)))) 12656 | "dsllv" => OK(Shift(DSLLV(rt,(rs,rd)))) 12657 | "dsrlv" => OK(Shift(DSRLV(rt,(rs,rd)))) 12658 | "dsrav" => OK(Shift(DSRAV(rt,(rs,rd)))) 12659 | "mul" => OK(MultDiv(MUL(rs,(rt,rd)))) 12660 | "movn" => OK(ArithR(MOVN(rs,(rt,rd)))) 12661 | "movz" => OK(ArithR(MOVZ(rs,(rt,rd)))) 12662 | "add" => OK(ArithR(ADD(rs,(rt,rd)))) 12663 | "addu" => OK(ArithR(ADDU(rs,(rt,rd)))) 12664 | "sub" => OK(ArithR(SUB(rs,(rt,rd)))) 12665 | "subu" => OK(ArithR(SUBU(rs,(rt,rd)))) 12666 | "and" => OK(ArithR(AND(rs,(rt,rd)))) 12667 | "or" => OK(ArithR(OR(rs,(rt,rd)))) 12668 | "xor" => OK(ArithR(XOR(rs,(rt,rd)))) 12669 | "nor" => OK(ArithR(NOR(rs,(rt,rd)))) 12670 | "slt" => OK(ArithR(SLT(rs,(rt,rd)))) 12671 | "sltu" => OK(ArithR(SLTU(rs,(rt,rd)))) 12672 | "dadd" => OK(ArithR(DADD(rs,(rt,rd)))) 12673 | "daddu" => OK(ArithR(DADDU(rs,(rt,rd)))) 12674 | "dsub" => OK(ArithR(DSUB(rs,(rt,rd)))) 12675 | "dsubu" => OK(ArithR(DSUBU(rs,(rt,rd)))) 12676 | _ => FAIL("Syntax error: " ^ s); 12677 12678fun p_fpr3 (x,(s,(fd,(fs,ft)))) = 12679 case x of 12680 "add.d" => OK(COP1(ADD_D(fd,(fs,ft)))) 12681 | "add.s" => OK(COP1(ADD_S(fd,(fs,ft)))) 12682 | "div.d" => OK(COP1(DIV_D(fd,(fs,ft)))) 12683 | "div.s" => OK(COP1(DIV_S(fd,(fs,ft)))) 12684 | "mul.d" => OK(COP1(MUL_D(fd,(fs,ft)))) 12685 | "mul.s" => OK(COP1(MUL_S(fd,(fs,ft)))) 12686 | "sub.d" => OK(COP1(SUB_D(fd,(fs,ft)))) 12687 | "sub.s" => OK(COP1(SUB_S(fd,(fs,ft)))) 12688 | _ => FAIL("Syntax error: " ^ s); 12689 12690fun p_fpr4 (x,(s,(fd,(fr,(fs,ft))))) = 12691 case x of 12692 "madd.d" => OK(COP1(MADD_D(fd,(fr,(fs,ft))))) 12693 | "madd.s" => OK(COP1(MADD_S(fd,(fr,(fs,ft))))) 12694 | "msub.d" => OK(COP1(MSUB_D(fd,(fr,(fs,ft))))) 12695 | "msub.s" => OK(COP1(MSUB_S(fd,(fr,(fs,ft))))) 12696 | _ => FAIL("Syntax error: " ^ s); 12697 12698fun imm_ok N (t,(n,s)) = 12699 let 12700 val (n,valid) = 12701 case t of 12702 NONE => (n,true) 12703 | Option.SOME false => (Nat.div(n,4),(Nat.mod(n,4)) = 0) 12704 | Option.SOME true => 12705 (Nat.-(Nat.div(n,4),1),((Nat.mod(n,4)) = 0) andalso (Nat.<=(4,n))) 12706 in 12707 if valid 12708 then let 12709 val imm = BitsN.fromNat(n,N) 12710 in 12711 if n = (BitsN.toNat imm) 12712 then (imm,"") 12713 else (BitsN.BV(0x0,N),"Immediate too large: " ^ s) 12714 end 12715 else (BitsN.BV(0x0,N),"Immediate not aligned or too small: " ^ s) 12716 end; 12717 12718fun p_1i (x,(s,n)) = 12719 case x of 12720 "j" => 12721 let 12722 val (i,e) = imm_ok 26 (Option.SOME false,(n,s)) 12723 in 12724 if e = "" then OK(Branch(J i)) else FAIL e 12725 end 12726 | "jal" => 12727 let 12728 val (i,e) = imm_ok 26 (Option.SOME false,(n,s)) 12729 in 12730 if e = "" then OK(Branch(JAL i)) else FAIL e 12731 end 12732 | "beq" => 12733 let 12734 val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) 12735 in 12736 if e = "" 12737 then OK(Branch(BEQ(BitsN.B(0x0,5),(BitsN.B(0x0,5),i)))) 12738 else FAIL e 12739 end 12740 | "bc1f" => 12741 let 12742 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12743 in 12744 if e = "" then OK(COP1(BC1F(i,BitsN.B(0x0,3)))) else FAIL e 12745 end 12746 | "bc1fl" => 12747 let 12748 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12749 in 12750 if e = "" then OK(COP1(BC1FL(i,BitsN.B(0x0,3)))) else FAIL e 12751 end 12752 | "bc1t" => 12753 let 12754 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12755 in 12756 if e = "" then OK(COP1(BC1T(i,BitsN.B(0x0,3)))) else FAIL e 12757 end 12758 | "bc1tl" => 12759 let 12760 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12761 in 12762 if e = "" then OK(COP1(BC1TL(i,BitsN.B(0x0,3)))) else FAIL e 12763 end 12764 | "word" => 12765 let 12766 val i = BitsN.fromNat(n,32) 12767 in 12768 if n = (BitsN.toNat i) 12769 then WORD32 i 12770 else FAIL("Immediate too large: " ^ s) 12771 end 12772 | _ => FAIL("Syntax error: " ^ s); 12773 12774fun p_cc1i (x,(s,(cc,n))) = 12775 case x of 12776 "bc1f" => 12777 let 12778 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12779 in 12780 if e = "" then OK(COP1(BC1F(i,cc))) else FAIL e 12781 end 12782 | "bc1fl" => 12783 let 12784 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12785 in 12786 if e = "" then OK(COP1(BC1FL(i,cc))) else FAIL e 12787 end 12788 | "bc1t" => 12789 let 12790 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12791 in 12792 if e = "" then OK(COP1(BC1T(i,cc))) else FAIL e 12793 end 12794 | "bc1tl" => 12795 let 12796 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12797 in 12798 if e = "" then OK(COP1(BC1TL(i,cc))) else FAIL e 12799 end 12800 | _ => FAIL("Syntax error: " ^ s); 12801 12802fun p_r1i (x,(s,(r,n))) = 12803 case x of 12804 "bltz" => 12805 let 12806 val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) 12807 in 12808 if e = "" then OK(Branch(BLTZ(r,i))) else FAIL e 12809 end 12810 | "bgez" => 12811 let 12812 val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) 12813 in 12814 if e = "" then OK(Branch(BGEZ(r,i))) else FAIL e 12815 end 12816 | "blez" => 12817 let 12818 val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) 12819 in 12820 if e = "" then OK(Branch(BLEZ(r,i))) else FAIL e 12821 end 12822 | "bgtz" => 12823 let 12824 val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) 12825 in 12826 if e = "" then OK(Branch(BGTZ(r,i))) else FAIL e 12827 end 12828 | "bltzl" => 12829 let 12830 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12831 in 12832 if e = "" then OK(Branch(BLTZL(r,i))) else FAIL e 12833 end 12834 | "bgezl" => 12835 let 12836 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12837 in 12838 if e = "" then OK(Branch(BGEZL(r,i))) else FAIL e 12839 end 12840 | "blezl" => 12841 let 12842 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12843 in 12844 if e = "" then OK(Branch(BLEZL(r,i))) else FAIL e 12845 end 12846 | "bgtzl" => 12847 let 12848 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12849 in 12850 if e = "" then OK(Branch(BGTZL(r,i))) else FAIL e 12851 end 12852 | "tgei" => 12853 let 12854 val (i,e) = imm_ok 16 (NONE,(n,s)) 12855 in 12856 if e = "" then OK(Trap(TGEI(r,i))) else FAIL e 12857 end 12858 | "tgeiu" => 12859 let 12860 val (i,e) = imm_ok 16 (NONE,(n,s)) 12861 in 12862 if e = "" then OK(Trap(TGEIU(r,i))) else FAIL e 12863 end 12864 | "tlti" => 12865 let 12866 val (i,e) = imm_ok 16 (NONE,(n,s)) 12867 in 12868 if e = "" then OK(Trap(TLTI(r,i))) else FAIL e 12869 end 12870 | "tltiu" => 12871 let 12872 val (i,e) = imm_ok 16 (NONE,(n,s)) 12873 in 12874 if e = "" then OK(Trap(TLTIU(r,i))) else FAIL e 12875 end 12876 | "teqi" => 12877 let 12878 val (i,e) = imm_ok 16 (NONE,(n,s)) 12879 in 12880 if e = "" then OK(Trap(TEQI(r,i))) else FAIL e 12881 end 12882 | "tnei" => 12883 let 12884 val (i,e) = imm_ok 16 (NONE,(n,s)) 12885 in 12886 if e = "" then OK(Trap(TNEI(r,i))) else FAIL e 12887 end 12888 | "bltzal" => 12889 let 12890 val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) 12891 in 12892 if e = "" then OK(Branch(BLTZAL(r,i))) else FAIL e 12893 end 12894 | "bgezal" => 12895 let 12896 val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) 12897 in 12898 if e = "" then OK(Branch(BGEZAL(r,i))) else FAIL e 12899 end 12900 | "bltzall" => 12901 let 12902 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12903 in 12904 if e = "" then OK(Branch(BLTZALL(r,i))) else FAIL e 12905 end 12906 | "bgezall" => 12907 let 12908 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12909 in 12910 if e = "" then OK(Branch(BGEZALL(r,i))) else FAIL e 12911 end 12912 | "lui" => 12913 let 12914 val (i,e) = imm_ok 16 (NONE,(n,s)) 12915 in 12916 if e = "" then OK(ArithI(LUI(r,i))) else FAIL e 12917 end 12918 | _ => FAIL("Syntax error: " ^ s); 12919 12920fun p_r2i (x,(s,(r1,(r2,n)))) = 12921 case x of 12922 "sll" => 12923 let 12924 val (i,e) = imm_ok 5 (NONE,(n,s)) 12925 in 12926 if e = "" then OK(Shift(SLL(r2,(r1,i)))) else FAIL e 12927 end 12928 | "srl" => 12929 let 12930 val (i,e) = imm_ok 5 (NONE,(n,s)) 12931 in 12932 if e = "" then OK(Shift(SRL(r2,(r1,i)))) else FAIL e 12933 end 12934 | "sra" => 12935 let 12936 val (i,e) = imm_ok 5 (NONE,(n,s)) 12937 in 12938 if e = "" then OK(Shift(SRA(r2,(r1,i)))) else FAIL e 12939 end 12940 | "dsll" => 12941 let 12942 val (i,e) = imm_ok 5 (NONE,(n,s)) 12943 in 12944 if e = "" then OK(Shift(DSLL(r2,(r1,i)))) else FAIL e 12945 end 12946 | "dsrl" => 12947 let 12948 val (i,e) = imm_ok 5 (NONE,(n,s)) 12949 in 12950 if e = "" then OK(Shift(DSRL(r2,(r1,i)))) else FAIL e 12951 end 12952 | "dsra" => 12953 let 12954 val (i,e) = imm_ok 5 (NONE,(n,s)) 12955 in 12956 if e = "" then OK(Shift(DSRA(r2,(r1,i)))) else FAIL e 12957 end 12958 | "dsll32" => 12959 let 12960 val (i,e) = imm_ok 5 (NONE,(n,s)) 12961 in 12962 if e = "" then OK(Shift(DSLL32(r2,(r1,i)))) else FAIL e 12963 end 12964 | "dsrl32" => 12965 let 12966 val (i,e) = imm_ok 5 (NONE,(n,s)) 12967 in 12968 if e = "" then OK(Shift(DSRL32(r2,(r1,i)))) else FAIL e 12969 end 12970 | "dsra32" => 12971 let 12972 val (i,e) = imm_ok 5 (NONE,(n,s)) 12973 in 12974 if e = "" then OK(Shift(DSRA32(r2,(r1,i)))) else FAIL e 12975 end 12976 | "beq" => 12977 let 12978 val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) 12979 in 12980 if e = "" then OK(Branch(BEQ(r1,(r2,i)))) else FAIL e 12981 end 12982 | "bne" => 12983 let 12984 val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) 12985 in 12986 if e = "" then OK(Branch(BNE(r1,(r2,i)))) else FAIL e 12987 end 12988 | "beql" => 12989 let 12990 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12991 in 12992 if e = "" then OK(Branch(BEQL(r1,(r2,i)))) else FAIL e 12993 end 12994 | "bnel" => 12995 let 12996 val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) 12997 in 12998 if e = "" then OK(Branch(BNEL(r1,(r2,i)))) else FAIL e 12999 end 13000 | "addi" => 13001 let 13002 val (i,e) = imm_ok 16 (NONE,(n,s)) 13003 in 13004 if e = "" then OK(ArithI(ADDI(r2,(r1,i)))) else FAIL e 13005 end 13006 | "addiu" => 13007 let 13008 val (i,e) = imm_ok 16 (NONE,(n,s)) 13009 in 13010 if e = "" then OK(ArithI(ADDIU(r2,(r1,i)))) else FAIL e 13011 end 13012 | "daddi" => 13013 let 13014 val (i,e) = imm_ok 16 (NONE,(n,s)) 13015 in 13016 if e = "" then OK(ArithI(DADDI(r2,(r1,i)))) else FAIL e 13017 end 13018 | "daddiu" => 13019 let 13020 val (i,e) = imm_ok 16 (NONE,(n,s)) 13021 in 13022 if e = "" then OK(ArithI(DADDIU(r2,(r1,i)))) else FAIL e 13023 end 13024 | "slti" => 13025 let 13026 val (i,e) = imm_ok 16 (NONE,(n,s)) 13027 in 13028 if e = "" then OK(ArithI(SLTI(r2,(r1,i)))) else FAIL e 13029 end 13030 | "sltiu" => 13031 let 13032 val (i,e) = imm_ok 16 (NONE,(n,s)) 13033 in 13034 if e = "" then OK(ArithI(SLTIU(r2,(r1,i)))) else FAIL e 13035 end 13036 | "andi" => 13037 let 13038 val (i,e) = imm_ok 16 (NONE,(n,s)) 13039 in 13040 if e = "" then OK(ArithI(ANDI(r2,(r1,i)))) else FAIL e 13041 end 13042 | "ori" => 13043 let 13044 val (i,e) = imm_ok 16 (NONE,(n,s)) 13045 in 13046 if e = "" then OK(ArithI(ORI(r2,(r1,i)))) else FAIL e 13047 end 13048 | "xori" => 13049 let 13050 val (i,e) = imm_ok 16 (NONE,(n,s)) 13051 in 13052 if e = "" then OK(ArithI(XORI(r2,(r1,i)))) else FAIL e 13053 end 13054 | _ => FAIL("Syntax error: " ^ s); 13055 13056fun p_opmem (x,(s,(rt,(rs,imm)))) = 13057 case x of 13058 "ldl" => OK(Load(LDL(rs,(rt,imm)))) 13059 | "ldr" => OK(Load(LDR(rs,(rt,imm)))) 13060 | "lb" => OK(Load(LB(rs,(rt,imm)))) 13061 | "lh" => OK(Load(LH(rs,(rt,imm)))) 13062 | "lwl" => OK(Load(LWL(rs,(rt,imm)))) 13063 | "lw" => OK(Load(LW(rs,(rt,imm)))) 13064 | "lbu" => OK(Load(LBU(rs,(rt,imm)))) 13065 | "lhu" => OK(Load(LHU(rs,(rt,imm)))) 13066 | "lwr" => OK(Load(LWR(rs,(rt,imm)))) 13067 | "lwu" => OK(Load(LWU(rs,(rt,imm)))) 13068 | "sb" => OK(Store(SB(rs,(rt,imm)))) 13069 | "sh" => OK(Store(SH(rs,(rt,imm)))) 13070 | "swl" => OK(Store(SWL(rs,(rt,imm)))) 13071 | "sw" => OK(Store(SW(rs,(rt,imm)))) 13072 | "sdl" => OK(Store(SDL(rs,(rt,imm)))) 13073 | "sdr" => OK(Store(SDR(rs,(rt,imm)))) 13074 | "swr" => OK(Store(SWR(rs,(rt,imm)))) 13075 | "ll" => OK(Load(LL(rs,(rt,imm)))) 13076 | "lld" => OK(Load(LLD(rs,(rt,imm)))) 13077 | "ld" => OK(Load(LD(rs,(rt,imm)))) 13078 | "sc" => OK(Store(SC(rs,(rt,imm)))) 13079 | "scd" => OK(Store(SCD(rs,(rt,imm)))) 13080 | "sd" => OK(Store(SD(rs,(rt,imm)))) 13081 | _ => FAIL("Syntax error: " ^ s); 13082 13083fun p_opfpmem (x,(s,(ft,(rs,imm)))) = 13084 case x of 13085 "ldc1" => OK(COP1(LDC1(ft,(imm,rs)))) 13086 | "lwc1" => OK(COP1(LWC1(ft,(imm,rs)))) 13087 | "sdc1" => OK(COP1(SDC1(ft,(imm,rs)))) 13088 | "swc1" => OK(COP1(SWC1(ft,(imm,rs)))) 13089 | _ => FAIL("Syntax error: " ^ s); 13090 13091fun p_opfpmem2 (x,(s,(ft,(rs,index)))) = 13092 case x of 13093 "ldxc1" => OK(COP1(LDXC1(ft,(index,rs)))) 13094 | "lwxc1" => OK(COP1(LWXC1(ft,(index,rs)))) 13095 | "sdxc1" => OK(COP1(SDXC1(ft,(index,rs)))) 13096 | "swxc1" => OK(COP1(SWXC1(ft,(index,rs)))) 13097 | _ => FAIL("Syntax error: " ^ s); 13098 13099fun instructionFromString s = 13100 case p_tokens s of 13101 [x] => p_arg0 x 13102 | [x,a] => 13103 (case p_reg a of 13104 Option.SOME r => p_r1(x,(s,r)) 13105 | NONE => 13106 (case p_number a of 13107 Option.SOME n => p_1i(x,(s,n)) 13108 | _ => FAIL("Syntax error: " ^ s))) 13109 | [x,a,b] => 13110 (case (p_reg a,p_reg b) of 13111 (Option.SOME r1,Option.SOME r2) => p_r2(x,(s,(r1,r2))) 13112 | (Option.SOME r1,NONE) => 13113 (case p_number b of 13114 Option.SOME n => p_r1i(x,(s,(r1,n))) 13115 | _ => 13116 (case p_address b of 13117 Option.SOME(i,r2) => p_opmem(x,(s,(r1,(r2,i)))) 13118 | NONE => 13119 (case p_fp_reg b of 13120 Option.SOME r2 => p_rfpr2(x,(s,(r1,r2))) 13121 | NONE => 13122 (case p_cfp_reg b of 13123 Option.SOME r2 => p_rcfpr(x,(s,(r1,r2))) 13124 | NONE => FAIL("Syntax error: " ^ s))))) 13125 | _ => 13126 (case (p_fp_reg a,p_fp_reg b) of 13127 (Option.SOME r1,Option.SOME r2) => p_fpr2(x,(s,(r1,r2))) 13128 | (Option.SOME r1,NONE) => 13129 (case p_address b of 13130 Option.SOME(i,r2) => p_opfpmem(x,(s,(r1,(r2,i)))) 13131 | NONE => 13132 (case p_index_address b of 13133 Option.SOME(r2,r3) => p_opfpmem2(x,(s,(r1,(r2,r3)))) 13134 | NONE => FAIL("Syntax error: " ^ s))) 13135 | _ => 13136 (case (p_fp_cc a,p_number b) of 13137 (Option.SOME cc,Option.SOME n) => p_cc1i(x,(s,(cc,n))) 13138 | _ => FAIL("Syntax error: " ^ s)))) 13139 | [x,a,b,c] => 13140 (case (p_reg2[a,b],p_reg c) of 13141 (Option.SOME(r1,r2),Option.SOME r3) => p_r3(x,(s,(r1,(r2,r3)))) 13142 | (Option.SOME(r1,r2),NONE) => 13143 (case p_number c of 13144 Option.SOME n => p_r2i(x,(s,(r1,(r2,n)))) 13145 | _ => 13146 (case p_fp_cc c of 13147 Option.SOME cc => p_r2cc(x,(s,(r1,(r2,cc)))) 13148 | NONE => FAIL("Syntax error: " ^ s))) 13149 | (NONE,Option.SOME r3) => 13150 (case (p_fp_reg a,p_fp_reg b) of 13151 (Option.SOME r1,Option.SOME r2) => 13152 p_fpr2r(x,(s,(r1,(r2,r3)))) 13153 | _ => FAIL("Syntax error: " ^ s)) 13154 | _ => 13155 (case (p_fp_reg a,(p_fp_reg b,p_fp_reg c)) of 13156 (Option.SOME r1,(Option.SOME r2,Option.SOME r3)) => 13157 p_fpr3(x,(s,(r1,(r2,r3)))) 13158 | (Option.SOME r1,(Option.SOME r2,NONE)) => 13159 (case p_fp_cc c of 13160 Option.SOME cc => p_fpr2cc(x,(s,(r1,(r2,cc)))) 13161 | NONE => FAIL("Syntax error: " ^ s)) 13162 | (NONE,(Option.SOME r1,Option.SOME r2)) => 13163 (case p_fp_cc a of 13164 Option.SOME cc => p_ccfpr2(x,(s,(cc,(r1,r2)))) 13165 | NONE => FAIL("Syntax error: " ^ s)) 13166 | _ => FAIL("Syntax error: " ^ s))) 13167 | [x,a,b,c,d] => 13168 (case (p_fp_reg a,(p_fp_reg b,(p_fp_reg c,p_fp_reg d))) of 13169 (Option.SOME r1,(Option.SOME r2,(Option.SOME r3,Option.SOME r4))) => 13170 p_fpr4(x,(s,(r1,(r2,(r3,r4))))) 13171 | _ => FAIL("Syntax error: " ^ s)) 13172 | _ => FAIL("Syntax error: " ^ s); 13173 13174fun encodeInstruction s = 13175 case instructionFromString s of 13176 OK i => L3.padLeftString(#"0",(8,BitsN.toHexString(Encode i))) 13177 | WORD32 w => L3.padLeftString(#"0",(8,BitsN.toHexString w)) 13178 | FAIL s => s; 13179 13180end