1/*
2 * Copyright 2017, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the GNU General Public License version 2. Note that NO WARRANTY is provided.
8 * See "LICENSE_GPLv2.txt" for details.
9 *
10 * @TAG(DATA61_GPL)
11 */
12
13#ifndef __ARCH_KERNEL_X2APIC_H_
14#define __ARCH_KERNEL_X2APIC_H_
15
16#include <config.h>
17#include <arch/machine.h>
18
19BOOT_CODE bool_t x2apic_is_enabled(void);
20
21#ifdef CONFIG_X2APIC
22typedef enum _apic_reg_t {
23    APIC_ID             = 0x802,
24    APIC_VERSION        = 0x803,
25    APIC_TASK_PRIO      = 0x808,
26    APIC_PROC_PRIO      = 0x80A,
27    APIC_EOI            = 0x80B,
28    APIC_LOGICAL_DEST   = 0x80D,
29    APIC_SVR            = 0x80F,
30    APIC_ISR_BASE       = 0x810,
31    APIC_TMR_BASE       = 0x818,
32    APIC_IRR_BASE       = 0x820,
33    APIC_ERR_STATUS     = 0x828,
34    APIC_ICR            = 0x830,
35    APIC_LVT_TIMER      = 0x832,
36    APIC_LVT_THERMAL    = 0x833,
37    APIC_LVT_PERF_CNTR  = 0x834,
38    APIC_LVT_LINT0      = 0x835,
39    APIC_LVT_LINT1      = 0x836,
40    APIC_LVT_ERROR      = 0x837,
41    APIC_TIMER_COUNT    = 0x838,
42    APIC_TIMER_CURRENT  = 0x839,
43    APIC_TIMER_DIVIDE   = 0x83E
44} apic_reg_t;
45
46#define X2APIC_LDR_CLUSTER_SHIFT   16
47#define X2APIC_LDR_ID_MASK         16
48
49static inline uint32_t
50apic_read_reg(apic_reg_t reg)
51{
52    return x86_rdmsr_low(reg);
53}
54
55static inline void
56apic_write_reg(apic_reg_t reg, uint32_t val)
57{
58    x86_wrmsr(reg, val);
59}
60
61static inline logical_id_t
62apic_get_logical_id(void)
63{
64    return apic_read_reg(APIC_LOGICAL_DEST);
65}
66
67static inline word_t
68apic_get_cluster(logical_id_t logical_id)
69{
70    return logical_id >> X2APIC_LDR_CLUSTER_SHIFT;
71}
72
73static inline void
74apic_write_icr(word_t high, word_t low)
75{
76    uint64_t icr = ((uint64_t)high << 32) | low;
77    x86_wrmsr(APIC_ICR, icr);
78}
79
80#define IPI_ICR_BARRIER  asm volatile("mfence" ::: "memory")
81#define IPI_MEM_BARRIER  IPI_ICR_BARRIER
82#endif /* CONFIG_X2APIC */
83#endif /* __ARCH_KERNEL_X2APIC_H_ */
84