1VeriLogger simulation log created at Sat Apr 19 18:46:03 2003 2Beginning Compile 3Beginning Phase I 4Compiling source file: test_c1.v 5Finished Phase I 6Entering Phase II... 7Finished Phase II 8Entering Phase III... 9Finished Phase III 10Highest level modules: test 11Compile Complete 12. 13Running... 14Checker1: state = 0 15Checker1: state = 1 16Checker1: state = 1 17Checker1: state = 1 18Checker1: state = 2 19Checker1: state = 2 20Checker1: state = 3 21Checker1: property violated! 22Exiting VeriLogger at simulation time 70000 230 Errors, 0 Warnings 24Compile time = 0.00000, Load time = 0.00000, Execution time = 0.00000 25 26Normal exit 27