1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12#include <stdbool.h> 13#include <assert.h> 14 15#include <platsupport/io.h> 16#include <platsupport/i2c.h> 17#include <platsupport/plat/i2c.h> 18 19#include <utils/arith.h> 20#include <utils/fence.h> 21#include <utils/attribute.h> 22#include "../../services.h" 23 24/** @file TK1 I2C driver. 25 * 26 * This driver only supports master mode. It doesn't support acting as a slave. 27 * It also doesn't support multi-master (masters other than itself connected 28 * to the same bus). 29 * 30 * We also don't support UF mode (ultra-fast mode). 31 * 32 * To use, just follow the API in `arch_include/arm/platsupport/i2c.h`. 33 * 34 * PREREQUISITES: 35 * This driver currently assumes that the MMIO registers it accesses are mapped 36 * as strongly ordered and uncached. The driver makes no attempts whatsoever at 37 * managing the write buffer or managing ordering of reads and writes. 38 * 39 * KNOWN BUGS: 40 * * Attempting to read or write more than 32bytes will cause the driver to 41 * freeze. Specifically, the first 32 or so will be transmitted, but then 42 * the IRQ to tell the controller that the TX FIFO is empty will fail to come 43 * in, so the driver will just sit there waiting for the next IRQ. 44 */ 45 46/* Notes from TK1 TRM: 47 * Section 33.0: 48 * "The host interface runs on the APB clock (pclk). The APB clock is derived 49 * from the system clock and can be 1.0, 1/2, 1/3 or 1/4 times the system clock 50 * (sclk)" 51 * "The I2C interface controller clock runs on a frequency up to 136 MHz." 52 * "The 136 MHz clock is derived from PLLP. Even though you can mux between 53 * PLLP, PLLC, PLLM and OSC clocks, PLLP is always selected and used in normal 54 * operation" 55 */ 56 57/* Notes from I2C specification rev 6: 58 * 59 * Section 5.1, "Fast mode": 60 * "If the power supply to a Fast-mode device is switched off, the SDA and SCL 61 * I/O pins must be floating so that they do not obstruct the bus lines." 62 * 63 * I.e, mux them off and leave them floating when they are not switched on. 64 */ 65#define CHECK_FOR_SDA_LOW 66 67#define PREFIX "I2C %p: " 68 69#define TK1I2C_DATA_MAX_NBYTES (4096) 70#define TK1I2C_NBYTES_PER_FIFO_WORD (4) 71 72#define TK1I2C_SLAVE_FLAGS_XFER_IN_PROGRESS_BIT (BIT(1)) 73 74#define TK1I2C_BUS_CLEAR_STATUS_SDA_NORMAL_BIT (BIT(0)) 75 76#define TK1I2C_BUS_CLEAR_CONFIG_IN_PROGRESS_BIT (BIT(0)) 77#define TK1I2C_BUS_CLEAR_CONFIG_TERMINATE_IMMEDIATE_BIT (BIT(1)) 78#define TK1I2C_BUS_CLEAR_CONFIG_SEND_STOP_BIT (BIT(2)) 79#define TK1I2C_BUS_CLEAR_CONFIG_THRESHOLD_SHIFT (16) 80#define TK1I2C_BUS_CLEAR_CONFIG_THRESHOLD_MASK (0xFF) 81 82#define TK1I2C_INTSTATUS_MMODE_RX_FIFO_DATA_REQ_BIT (BIT(0)) 83#define TK1I2C_INTSTATUS_MMODE_TX_FIFO_DATA_REQ_BIT (BIT(1)) 84#define TK1I2C_INTSTATUS_MMODE_ARBITRATION_LOST_BIT (BIT(2)) 85#define TK1I2C_INTSTATUS_MMODE_NO_ACK_BIT (BIT(3)) 86#define TK1I2C_INTSTATUS_MMODE_RX_FIFO_UNR_BIT (BIT(4)) 87#define TK1I2C_INTSTATUS_MMODE_TX_FIFO_OVF_BIT (BIT(5)) 88#define TK1I2C_INTSTATUS_MMODE_ALL_PACKETS_XFER_COMPLETE_BIT (BIT(6)) 89#define TK1I2C_INTSTATUS_MMODE_PACKET_XFER_COMPLETE_BIT (BIT(7)) 90 91#define TK1I2C_INTSTATUS_SMODE_RX_FIFO_DATA_REQ_BIT (BIT(16)) 92#define TK1I2C_INTSTATUS_SMODE_TX_FIFO_DATA_REQ_BIT (BIT(17)) 93#define TK1I2C_INTSTATUS_SMODE_RX_FIFO_UNR_BIT (BIT(20)) 94#define TK1I2C_INTSTATUS_SMODE_TX_FIFO_OVF_BIT (BIT(21)) 95#define TK1I2C_INTSTATUS_SMODE_PACKET_XFER_COMPLETE_BIT (BIT(22)) 96#define TK1I2C_INTSTATUS_SMODE_RX_BUFFER_FULL_BIT (BIT(23)) 97#define TK1I2C_INTSTATUS_SMODE_TX_BUFFER_REQ_BIT (BIT(24)) 98#define TK1I2C_INTSTATUS_SMODE_PACKET_XFER_ERROR_BIT (BIT(25)) 99#define TK1I2C_INTSTATUS_SMODE_SWITCHED_WRITE2READ_BIT (BIT(26)) 100#define TK1I2C_INTSTATUS_SMODE_SWITCHED_READ2WRITE_BIT (BIT(27)) 101#define TK1I2C_INTSTATUS_SMODE_ACK_WITHHELD_BIT (BIT(28)) 102 103#define TK1I2C_INTMASK_MMODE_RX_FIFO_DATA_REQ_BIT (BIT(0)) 104#define TK1I2C_INTMASK_MMODE_TX_FIFO_DATA_REQ_BIT (BIT(1)) 105#define TK1I2C_INTMASK_MMODE_ARBITRATION_LOST_BIT (BIT(2)) 106#define TK1I2C_INTMASK_MMODE_NO_ACK_BIT (BIT(3)) 107#define TK1I2C_INTMASK_MMODE_RX_FIFO_UNR_BIT (BIT(4)) 108#define TK1I2C_INTMASK_MMODE_TX_FIFO_OVF_BIT (BIT(5)) 109#define TK1I2C_INTMASK_MMODE_ALL_PACKETS_XFER_COMPLETE_BIT (BIT(6)) 110#define TK1I2C_INTMASK_MMODE_PACKET_XFER_COMPLETE_BIT (BIT(7)) 111#define TK1I2C_INTMASK_MMODE_BUS_CLEAR_DONE_BIT (BIT(11)) 112 113#define TK1I2C_INTMASK_SMODE_RX_FIFO_DATA_REQ_BIT (BIT(16)) 114#define TK1I2C_INTMASK_SMODE_TX_FIFO_DATA_REQ_BIT (BIT(17)) 115#define TK1I2C_INTMASK_SMODE_RX_FIFO_UNR_BIT (BIT(20)) 116#define TK1I2C_INTMASK_SMODE_TX_FIFO_OVF_BIT (BIT(21)) 117#define TK1I2C_INTMASK_SMODE_PACKET_XFER_COMPLETE_BIT (BIT(22)) 118#define TK1I2C_INTMASK_SMODE_RX_BUFFER_FULL_BIT (BIT(23)) 119#define TK1I2C_INTMASK_SMODE_TX_BUFFER_REQ_BIT (BIT(24)) 120#define TK1I2C_INTMASK_SMODE_PACKET_XFER_ERROR_BIT (BIT(25)) 121#define TK1I2C_INTMASK_SMODE_SWITCHED_WRITE2READ_BIT (BIT(26)) 122#define TK1I2C_INTMASK_SMODE_SWITCHED_READ2WRITE_BIT (BIT(27)) 123#define TK1I2C_INTMASK_SMODE_ACK_WITHHELD_BIT (BIT(28)) 124 125#define TK1I2C_CONFIG_LOAD_MASTER_BIT (BIT(0)) 126#define TK1I2C_CONFIG_LOAD_SLAVE_BIT (BIT(1)) 127#define TK1I2C_CONFIG_LOAD_TIMEOUT_BIT (BIT(2)) 128#define COMMIT_MASTER_BIT (TK1I2C_CONFIG_LOAD_MASTER_BIT) 129#define COMMIT_SLAVE_BIT (TK1I2C_CONFIG_LOAD_SLAVE_BIT) 130#define COMMIT_TIMEOUT_BIT (TK1I2C_CONFIG_LOAD_TIMEOUT_BIT) 131 132#define TK1I2C_FIFO_CONTROL_MMODE_TX_TRIG_SHIFT (5) 133#define TK1I2C_FIFO_CONTROL_MMODE_TX_TRIG_MASK (0x7) 134#define TK1I2C_FIFO_CONTROL_MMODE_RX_TRIG_SHIFT (2) 135#define TK1I2C_FIFO_CONTROL_MMODE_RX_TRIG_MASK (0x7) 136 137#define TK1I2C_FIFO_CONTROL_SMODE_TX_TRIG_SHIFT (13) 138#define TK1I2C_FIFO_CONTROL_SMODE_TX_TRIG_MASK (0x7) 139#define TK1I2C_FIFO_CONTROL_SMODE_RX_TRIG_SHIFT (10) 140#define TK1I2C_FIFO_CONTROL_SMODE_RX_TRIG_MASK (0x7) 141 142#define TK1I2C_FIFO_CONTROL_MMODE_FLUSH_TX_BIT (BIT(1)) 143#define TK1I2C_FIFO_CONTROL_MMODE_FLUSH_RX_BIT (BIT(0)) 144#define TK1I2C_FIFO_CONTROL_SMODE_FLUSH_TX_BIT (BIT(9)) 145#define TK1I2C_FIFO_CONTROL_SMODE_FLUSH_RX_BIT (BIT(8)) 146 147#define TK1I2C_CNFG_PACKET_MODE_EN_BIT (BIT(10)) 148#define TK1I2C_CNFG_ADDRESS_10BIT_EN_BIT (BIT(0)) 149#define TK1I2C_CNFG_2_SLAVE_BIT (BIT(4)) 150#define TK1I2C_CNFG_SEND_START_BIT (BIT(5)) 151#define TK1I2C_CNFG_NOACK_BIT (BIT(8)) 152#define TK1I2C_CNFG_BEGIN_XFER_BIT (BIT(9)) 153#define TK1I2C_CNFG_XFER_LENGTH_SHIFT (1) 154#define TK1I2C_CNFG_XFER_LENGTH_MASK (0x7) 155#define TK1I2C_CNFG_DEBOUNCE_COUNT_SHIFT (12) 156#define TK1I2C_CNFG_DEBOUNCE_COUNT_MASK (0x7) 157 158#define TK1I2C_SL_CNFG_SLAVE_EN_BIT (BIT(3)) 159#define TK1I2C_SL_CNFG_PACKET_MODE_EN_BIT (BIT(4)) 160#define TK1I2C_SL_CNFG_FIFO_XFER_EN_BIT (BIT(20)) 161 162#define TK1I2C_FIFO_STATUS_MMODE_TX_EMPTY_SHIFT (4) 163#define TK1I2C_FIFO_STATUS_MMODE_TX_EMPTY_MASK (0xF) 164#define TK1I2C_FIFO_STATUS_MMODE_RX_FULL_SHIFT (0) 165#define TK1I2C_FIFO_STATUS_MMODE_RX_FULL_MASK (0xF) 166#define TK1I2C_FIFO_STATUS_SMODE_TX_EMPTY_SHIFT (20) 167#define TK1I2C_FIFO_STATUS_SMODE_TX_EMPTY_MASK (0xF) 168#define TK1I2C_FIFO_STATUS_SMODE_RX_FULL_SHIFT (16) 169#define TK1I2C_FIFO_STATUS_SMODE_RX_FULL_MASK (0xF) 170 171#define TK1I2C_FIFO_DEPTH (8) 172 173/* These constants are used by tk1_i2c_prepare_mmode_xfer_headers(). 174 * They are the values for the bit positions in the header words used by the 175 * controller. 176 */ 177#define TK1I2C_TXPKT0_PKTTYPE_SHIFT (0) 178#define TK1I2C_TXPKT0_PKTTYPE_MASK (0x7) 179 180#define TK1I2C_TXPKT0_PROTOCOL_SHIFT (4) 181#define TK1I2C_TXPKT0_PROTOCOL_MASK (0xF) 182#define TK1I2C_TXPKT0_PROTOCOL_I2C (1) 183 184#define TK1I2C_TXPKT0_CONTROLLER_ID_SHIFT (12) 185#define TK1I2C_TXPKT0_CONTROLLER_ID_MASK (0xF) 186 187#define TK1I2C_TXPKT0_PKTID_SHIFT (16) 188#define TK1I2C_TXPKT0_PKTID_MASK (0xFF) 189 190#define TK1I2C_TXPKT0_PROTHDR_SIZE_SHIFT (28) 191#define TK1I2C_TXPKT0_PROTHDR_SIZE_MASK (0x3) 192 193#define TK1I2C_TXPKT1_PAYLOAD_SIZE_SHIFT (0) 194#define TK1I2C_TXPKT1_PAYLOAD_SIZE_MASK (0xFFF) 195 196#define TK1I2C_I2CPKT_SLAVE_ADDR_10BIT_SHIFT (0) 197#define TK1I2C_I2CPKT_SLAVE_ADDR_10BIT_MASK (0x3FF) 198 199#define TK1I2C_I2CPKT_SLAVE_ADDR_7BIT_SHIFT (1) 200#define TK1I2C_I2CPKT_SLAVE_ADDR_7BIT_MASK (0x7F) 201 202#define TK1I2C_I2CPKT_HS_MASTER_ADDR_SHIFT (12) 203#define TK1I2C_I2CPKT_HS_MASTER_ADDR_MASK (0x7) 204 205#define TK1I2C_I2CPKT_CONTINUE_XFER_BIT (BIT(15)) 206#define TK1I2C_I2CPKT_SEND_REPEAT_START_NOT_STOP_BIT (BIT(16)) 207#define TK1I2C_I2CPKT_IRQ_ON_COMPLETION_BIT (BIT(17)) 208#define TK1I2C_I2CPKT_10_BIT_ADDRESS_BIT (BIT(18)) 209#define TK1I2C_I2CPKT_READ_XFER_BIT (BIT(19)) 210#define TK1I2C_I2CPKT_SEND_START_BYTE_BIT (BIT(20)) 211#define TK1I2C_I2CPKT_CONTINUE_ON_NACK_BIT (BIT(21)) 212#define TK1I2C_I2CPKT_HS_MODE_BIT (BIT(22)) 213#define TK1I2C_I2CPKT_RESPONSE_PKT_ENABLE_BIT (BIT(24)) 214#define TK1I2C_I2CPKT_RESPONSE_PKT_FREQ_BIT (BIT(25)) 215 216/* These next few #defines pertain to tk1_i2c_set_speed() and its helper 217 * functions tk1_i2c_calc_divisor_value_for() and 218 * tk1_i2c_calc_baud_resulting_from(). 219 */ 220#define TK1_CAR_PLLP_INPUT_FREQ_HZ (408000000) 221#define TK1_CAR_PLLP_DIVISOR (1) 222 223#define TK1I2C_IFACE_TIMING0_TLOW_SHIFT (0) 224#define TK1I2C_IFACE_TIMING0_TLOW_MASK (0x3F) 225#define TK1I2C_IFACE_TIMING0_THIGH_SHIFT (8) 226#define TK1I2C_IFACE_TIMING0_THIGH_MASK (0x3F) 227 228#define TK1I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT (16) 229#define TK1I2C_CLK_DIVISOR_STD_FAST_MODE_MASK (0xFFFF) 230 231#define TK1I2C_HS_IFACE_TIMING0_TLOW_SHIFT (0) 232#define TK1I2C_HS_IFACE_TIMING0_TLOW_MASK (0x3F) 233#define TK1I2C_HS_IFACE_TIMING0_THIGH_SHIFT (8) 234#define TK1I2C_HS_IFACE_TIMING0_THIGH_MASK (0x3F) 235 236#define TK1I2C_CLK_DIVISOR_HS_MODE_SHIFT (0) 237#define TK1I2C_CLK_DIVISOR_HS_MODE_MASK (0xFFFF) 238 239enum i2c_xfer_mode { 240 I2C_MODE_MASTER, 241 I2C_MODE_SLAVE 242}; 243 244typedef volatile struct tk1_i2c_regs_ { 245 uint32_t cnfg; 246 uint32_t cmd_addr0, cmd_addr1; 247 uint32_t cmd_data0, cmd_data1; 248 PAD_STRUCT_BETWEEN(0x10, 0x1c, uint32_t); 249 uint32_t status; 250 PAD_STRUCT_BETWEEN(0x1c, 0x20, uint32_t); 251 uint32_t sl_cnfg; 252 uint32_t sl_rcvd, sl_status; 253 uint32_t sl_addr0, sl_addr1; 254 uint32_t tlow_sext; 255 PAD_STRUCT_BETWEEN(0x34, 0x3c, uint32_t); 256 uint32_t sl_delay_count; 257 uint32_t sl_interrupt_mask, sl_interrupt_source, sl_interrupt_set; 258 PAD_STRUCT_BETWEEN(0x48, 0x50, uint32_t); 259 uint32_t tx_packet_fifo, rx_fifo, packet_transfer_status; 260 uint32_t fifo_control, fifo_status; 261 uint32_t interrupt_mask, interrupt_status; 262 uint32_t clk_divisor; 263 uint32_t interrupt_source, interrupt_set; 264 uint32_t sl_tx_packet_fifo, sl_rx_fifo, sl_packet_status; 265 uint32_t bus_clear_config, bus_clear_status; 266 uint32_t config_load; 267 PAD_STRUCT_BETWEEN(0x8c, 0x94, uint32_t); 268 uint32_t interface_timing0, interface_timing1; 269 uint32_t hs_interface_timing0, hs_interface_timing1; 270} tk1_i2c_regs_t; 271 272typedef struct tk1_i2c_state_ { 273 tk1_i2c_regs_t *regs; 274 int controller_id; 275 276 struct { 277 int hsmode_master_address; 278 int slave_id; 279 bool is_write; 280 uint8_t *buff; 281 size_t nbytes; 282 ssize_t xfer_cursor; 283 } master; 284 struct { 285 int self_id; 286 bool is_write; 287 uint8_t *buff; 288 size_t nbytes; 289 ssize_t xfer_cursor; 290 } slave; 291} tk1_i2c_state_t; 292 293static inline tk1_i2c_state_t * 294tk1_i2c_get_state(i2c_bus_t *ib) 295{ 296 assert(ib != NULL); 297 assert(ib->priv != NULL); 298 return (tk1_i2c_state_t *)ib->priv; 299} 300 301static inline tk1_i2c_regs_t * 302tk1_i2c_get_priv(i2c_bus_t *ib) 303{ 304 assert(tk1_i2c_get_state(ib)->regs != NULL); 305 return (tk1_i2c_regs_t *)tk1_i2c_get_state(ib)->regs; 306} 307 308typedef struct tk1_i2c_pktheaders_ { 309 uint32_t io0; 310 uint32_t io1; 311 uint32_t i2c; 312} tk1_i2c_pktheaders_t; 313 314static void 315tk1_i2c_set_packet_mode(i2c_bus_t *ib, bool enabled) 316{ 317 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 318 319 if (enabled) { 320 r->cnfg |= TK1I2C_CNFG_PACKET_MODE_EN_BIT; 321 } else { 322 r->cnfg &= ~TK1I2C_CNFG_PACKET_MODE_EN_BIT; 323 } 324} 325 326static void 327tk1_i2c_config_commit(i2c_bus_t *ib, uint8_t which_configs) 328{ 329 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 330 uint32_t val = 0; 331 332 if (which_configs & COMMIT_MASTER_BIT) { 333 val |= TK1I2C_CONFIG_LOAD_MASTER_BIT; 334 } 335 if (which_configs & COMMIT_SLAVE_BIT) { 336 val |= TK1I2C_CONFIG_LOAD_SLAVE_BIT; 337 } 338 if (which_configs & COMMIT_TIMEOUT_BIT) { 339 val |= TK1I2C_CONFIG_LOAD_TIMEOUT_BIT; 340 } 341 342 r->config_load = val; 343 344 /* The commit bits are hardware auto-cleared when the hardware is done 345 * performing the operation. 346 */ 347 while (r->config_load != 0) { 348 /* Do nothing */ 349 } 350} 351 352static void 353tk1_i2c_flush_fifos(i2c_bus_t *ib, enum i2c_xfer_mode mode) 354{ 355 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 356 uint32_t mask; 357 358 if (mode == I2C_MODE_MASTER) { 359 mask = TK1I2C_FIFO_CONTROL_MMODE_FLUSH_RX_BIT 360 | TK1I2C_FIFO_CONTROL_MMODE_FLUSH_TX_BIT; 361 } else { 362 mask = TK1I2C_FIFO_CONTROL_SMODE_FLUSH_RX_BIT 363 | TK1I2C_FIFO_CONTROL_SMODE_FLUSH_TX_BIT; 364 } 365 366 r->fifo_control |= mask; 367 while ((r->fifo_control & mask) != 0) { 368 /* Poll bits waiting for them to be auto-cleared by hardware. */ 369 } 370} 371 372static void 373tk1_i2c_set_mode(i2c_bus_t *ib, enum i2c_xfer_mode mode) 374{ 375 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 376 377 if (mode == I2C_MODE_SLAVE) { 378 r->sl_cnfg |= TK1I2C_SL_CNFG_SLAVE_EN_BIT; 379 } else { 380 r->sl_cnfg &= ~TK1I2C_SL_CNFG_SLAVE_EN_BIT; 381 } 382 383 tk1_i2c_config_commit(ib, COMMIT_MASTER_BIT); 384} 385 386static int 387tk1_i2c_handle_arbitration_loss(i2c_bus_t *ib) 388{ 389 UNUSED tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 390 391 /* I2C Reference rev6, 3.1.8: "Arbitration": 392 * "If a master also incorporates a slave function and it loses arbitration 393 * during the addressing stage, it is possible that the winning master is 394 * trying to address it. The losing master must therefore switch over 395 * immediately to its slave mode" 396 */ 397 tk1_i2c_set_mode(ib, I2C_MODE_SLAVE); 398 return 0; 399} 400 401static int 402tk1_i2c_handle_nack(i2c_bus_t *ib) 403{ 404 /* I2C Reference rev6, 33.4.4: "Error Handling": 405 * "When an error occurs due to NACK, a stop condition is put on the bus 406 * and an interrupt is generated. 407 * The status register is updated with the current error packet ID at which 408 * the error occured. 409 * Software should reset the controller. 410 * In case of a DMA transfer, DMA needs to be restarted." 411 * 412 * ^ This handling makes sense, but only if we are the master-sender. 413 * If we are the slave-sender, we should not be sending a STOP signal. 414 * 415 * "In packet mode ... if an error occurs during packet transfer then the 416 * controller should be reset ... and the entire packet needs to be resent 417 * since there is no accurate way of knowing how many bytes made it to the 418 * I2C slave." 419 * 420 * I believe that the controller which must be reset is the receiver and 421 * not the transmitter, in this case, because the receiver may be held in 422 * limbo expecting a resend. There is no reason to think the transmitter 423 * needs to be reset. 424 */ 425 UNUSED tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 426 return 0; 427} 428 429static bool 430tk1_i2c_bus_is_locked_up(i2c_bus_t *ib) 431{ 432 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 433 434 return !(r->bus_clear_status & TK1I2C_BUS_CLEAR_STATUS_SDA_NORMAL_BIT); 435} 436 437/** Forces CLK pulses down the CLK line to trick a slave device that is holding 438 * SDA low, to release SDA eventually. The slave is expected to release SDA 439 * within 9 CLK pulses. 440 * 441 * Reasons for an arbitration failure for the SDA line: 442 * * Line isn't muxed 443 * * High-Z is asserted 444 * * Actual bus lockup caused by slave holding SDA low. 445 * 446 * @param[in] send_stop_afterward Whether or not to automatically append a 447 * STOP signal after the bus clear operation. 448 * @return true if the bus clear operation was successful. 449 */ 450static bool 451tk1_i2c_bus_clear(i2c_bus_t *ib, bool send_stop_afterward) 452{ 453 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 454 455 ZF_LOGW(PREFIX"Performing bus clear operation.", r); 456 457 while (r->bus_clear_config & TK1I2C_BUS_CLEAR_CONFIG_IN_PROGRESS_BIT) { 458 /* Just in case the bit was set before we began. */ 459 } 460 461 r->bus_clear_config = 9 << TK1I2C_BUS_CLEAR_CONFIG_THRESHOLD_SHIFT 462 | (send_stop_afterward 463 ? TK1I2C_BUS_CLEAR_CONFIG_SEND_STOP_BIT : 0); 464 465 tk1_i2c_config_commit(ib, COMMIT_MASTER_BIT); 466 467 r->bus_clear_config |= TK1I2C_BUS_CLEAR_CONFIG_IN_PROGRESS_BIT; 468 while (r->bus_clear_config & TK1I2C_BUS_CLEAR_CONFIG_IN_PROGRESS_BIT) { 469 /* Do nothing until the device clears the bit to signal that it's done. 470 */ 471 }; 472 473 return !tk1_i2c_bus_is_locked_up(ib); 474} 475 476static const uint32_t i2c_speed_freqs[] = { 477 [I2C_SLAVE_SPEED_STANDARD] = 100000, 478 [I2C_SLAVE_SPEED_FAST] = 400000, 479 [I2C_SLAVE_SPEED_FASTPLUS] = 1000000, 480 [I2C_SLAVE_SPEED_HIGHSPEED] = 3400000 481}; 482 483static const char *i2c_speed_names[] = { 484 [I2C_SLAVE_SPEED_STANDARD] = "standard", 485 [I2C_SLAVE_SPEED_FAST] = "fast", 486 [I2C_SLAVE_SPEED_FASTPLUS] = "fast+", 487 [I2C_SLAVE_SPEED_HIGHSPEED] = "high-speed" 488}; 489 490static int32_t 491tk1_i2c_calc_divisor_value_for(i2c_bus_t *bus, 492 enum i2c_slave_speed speed, 493 uint32_t variant_constant) 494{ 495 tk1_i2c_regs_t *r = tk1_i2c_get_priv(bus); 496 uint32_t tlow, thigh; 497 uint32_t target_scl_freq_hz; 498 499 assert(variant_constant == 2 || variant_constant == 3); 500 501 /* Section 33.1.2.1 has the instructions for setting the bus speed based 502 * on the CAR controller's divisors. 503 * 504 * See also 33.3.1. 505 * 506 * FIXME: 507 * 508 * This driver works with the assumption that the input clock source is 509 * PLLP, and furthermore that the PLLP divisor value is 0. 510 * 511 * This will have to be the case until we have a proper driver API. 512 * 513 * EXPLANATION: 514 * 515 * The SCL line's frequency is set according to the following equation: 516 * SCL = 408000000 / ((TLOW+THIGH+VC) * (CLK_DIVISOR + 1) * TK1_CAR_PLLP_DIVISOR) 517 * 518 * VC = variant_constant, either 2 or 3. This is just a magic number that 519 * is given in the TK1 manual with no explanation. 520 * TLOW = the value in I2C_I2C_INTERFACE_TIMING_0_0. 521 * THIGH = the value in I2C_I2C_INTERFACE_TIMING_0_0. 522 * CLK_DIVISOR = the value in I2C_I2C_CLK_DIVISOR_REGISTER_0. 523 * TK1_CAR_PLLP_DIVISOR = the divisor value in the clock and reset 524 * controller's PLLP clock source. Specifically, the resultant value that 525 * the divider will divide the input frequency by. I.e, N+1, not N. 526 * So for example, right now, this driver depends on us using '0' as the 527 * literal divisor value, and a value of '0' in the divisor register will 528 * cause the divider to divide the input frequency by 1 (N+1). 529 * So I2C_FREQENCY_DIVISOR in this equation should be 1, not 0. 530 * 531 * But we need to derive CLK_DIVISOR. So we rearrange that (algebra!) to 532 * solve for CLK_DIVISOR, and get: 533 * CLK_DIVISOR = (408000000 / (SCL * TK1_CAR_PLLP_DIVISOR * (TLOW+THIGH+VC))) - 1 534 */ 535 switch (speed) { 536 case I2C_SLAVE_SPEED_HIGHSPEED: 537 tlow = read_masked(&r->hs_interface_timing0, 538 (TK1I2C_HS_IFACE_TIMING0_TLOW_MASK << TK1I2C_HS_IFACE_TIMING0_TLOW_SHIFT)) 539 >> TK1I2C_HS_IFACE_TIMING0_TLOW_SHIFT; 540 thigh = read_masked(&r->hs_interface_timing0, 541 (TK1I2C_HS_IFACE_TIMING0_THIGH_MASK << TK1I2C_HS_IFACE_TIMING0_THIGH_SHIFT)) 542 >> TK1I2C_HS_IFACE_TIMING0_THIGH_SHIFT; 543 544 ZF_LOGD("Reading highspeed tlow/high: tLOW %d, tHIGH %d.", 545 tlow, thigh); 546 break; 547 548 case I2C_SLAVE_SPEED_STANDARD: 549 case I2C_SLAVE_SPEED_FAST: 550 case I2C_SLAVE_SPEED_FASTPLUS: 551 tlow = read_masked(&r->interface_timing0, 552 (TK1I2C_IFACE_TIMING0_TLOW_MASK << TK1I2C_IFACE_TIMING0_TLOW_SHIFT)) 553 >> TK1I2C_IFACE_TIMING0_TLOW_SHIFT; 554 thigh = read_masked(&r->interface_timing0, 555 (TK1I2C_IFACE_TIMING0_THIGH_MASK << TK1I2C_IFACE_TIMING0_THIGH_SHIFT)) 556 >> TK1I2C_IFACE_TIMING0_THIGH_SHIFT; 557 558 ZF_LOGD("Reading std/fast/f+ tlow/high: tLOW %d, tHIGH %d.", 559 tlow, thigh); 560 break; 561 562 default: 563 return -1; 564 } 565 566 ZF_LOGD("tLOW is %d, tHIGH is %d.", tlow, thigh); 567 target_scl_freq_hz = i2c_speed_freqs[speed]; 568 return ((TK1_CAR_PLLP_INPUT_FREQ_HZ / target_scl_freq_hz) 569 / (tlow+thigh+variant_constant)) - 1; 570} 571 572static uint32_t 573tk1_i2c_calc_baud_resulting_from(i2c_bus_t *ib, 574 uint32_t divisor, 575 enum i2c_slave_speed speed, 576 uint32_t vc) 577{ 578 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 579 uint32_t tlow, thigh; 580 581 switch (speed) { 582 case I2C_SLAVE_SPEED_HIGHSPEED: 583 tlow = read_masked(&r->hs_interface_timing0, 584 (TK1I2C_HS_IFACE_TIMING0_TLOW_MASK << TK1I2C_HS_IFACE_TIMING0_TLOW_SHIFT)) 585 >> TK1I2C_HS_IFACE_TIMING0_TLOW_SHIFT; 586 thigh = read_masked(&r->hs_interface_timing0, 587 (TK1I2C_HS_IFACE_TIMING0_THIGH_MASK << TK1I2C_HS_IFACE_TIMING0_THIGH_SHIFT)) 588 >> TK1I2C_HS_IFACE_TIMING0_THIGH_SHIFT; 589 break; 590 591 case I2C_SLAVE_SPEED_STANDARD: 592 case I2C_SLAVE_SPEED_FAST: 593 case I2C_SLAVE_SPEED_FASTPLUS: 594 tlow = read_masked(&r->interface_timing0, 595 (TK1I2C_IFACE_TIMING0_TLOW_MASK << TK1I2C_IFACE_TIMING0_TLOW_SHIFT)) 596 >> TK1I2C_IFACE_TIMING0_TLOW_SHIFT; 597 thigh = read_masked(&r->interface_timing0, 598 (TK1I2C_IFACE_TIMING0_THIGH_MASK << TK1I2C_IFACE_TIMING0_THIGH_SHIFT)) 599 >> TK1I2C_IFACE_TIMING0_THIGH_SHIFT; 600 break; 601 602 default: 603 return -1; 604 } 605 606 return TK1_CAR_PLLP_INPUT_FREQ_HZ / ((tlow+thigh+vc) * (divisor)); 607} 608 609static long 610tk1_i2c_set_speed(i2c_bus_t* bus, enum i2c_slave_speed speed) 611{ 612 int32_t divisor; 613 tk1_i2c_regs_t *r = tk1_i2c_get_priv(bus); 614 uint8_t variant_constant = 3; 615 616 divisor = tk1_i2c_calc_divisor_value_for(bus, speed, variant_constant); 617 if (divisor < 0 || divisor > UINT16_MAX) { 618 return -1; 619 } 620 621 if (divisor > 3) { 622 variant_constant = 2; 623 divisor = tk1_i2c_calc_divisor_value_for(bus, speed, variant_constant); 624 if (divisor < 0 || divisor > UINT16_MAX) { 625 return -1; 626 } 627 } 628 629 while (tk1_i2c_calc_baud_resulting_from(bus, divisor, 630 speed, variant_constant) 631 > i2c_speed_freqs[speed]) { 632 ZF_LOGV(PREFIX"Resulting baud is %d. Recalculating divisor up from %d to %d.", 633 r, tk1_i2c_calc_baud_resulting_from(bus, divisor, speed, variant_constant), 634 divisor, divisor+1); 635 divisor++; 636 } 637 ZF_LOGV(PREFIX"Calculated I2C divisor at %d. Effective baud is %d. Previous values: std %d, hs %d.", 638 r, divisor, 639 tk1_i2c_calc_baud_resulting_from(bus, divisor, speed, variant_constant), 640 (r->clk_divisor >> 16 & 0xFFFF), 641 (r->clk_divisor & 0xFFFF)); 642 643 switch (speed) { 644 case I2C_SLAVE_SPEED_HIGHSPEED: 645 write_masked(&r->clk_divisor, 646 0xFFFF, 647 ((divisor & TK1I2C_CLK_DIVISOR_HS_MODE_MASK) 648 << TK1I2C_CLK_DIVISOR_HS_MODE_SHIFT)); 649 break; 650 651 case I2C_SLAVE_SPEED_STANDARD: 652 case I2C_SLAVE_SPEED_FAST: 653 case I2C_SLAVE_SPEED_FASTPLUS: 654 write_masked(&r->clk_divisor, 655 0xFFFF0000, 656 ((divisor & TK1I2C_CLK_DIVISOR_STD_FAST_MODE_MASK) 657 << TK1I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT)); 658 break; 659 660 default: 661 return -1; 662 } 663 664 ZF_LOGD("For I2C speed %s, divisor was calculated to be %d.", 665 i2c_speed_names[speed], divisor); 666 667 tk1_i2c_config_commit(bus, COMMIT_MASTER_BIT); 668 return i2c_speed_freqs[speed]; 669} 670 671static inline void 672tk1_i2c_toggle_irq(i2c_bus_t *ib, bool enable, uint32_t irqs) 673{ 674 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 675 676 if (enable) { 677 r->interrupt_mask |= irqs; 678 } else { 679 r->interrupt_mask &= ~irqs; 680 } 681} 682 683static inline void 684tk1_i2c_acknowledge_irq(i2c_bus_t *ib, uint32_t irqs) 685{ 686 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 687 688 r->interrupt_status |= irqs; 689} 690 691static inline void 692tk1_i2c_callback(i2c_bus_t *ib, enum i2c_stat stat, size_t nbytes) 693{ 694 if (ib->cb != NULL) { 695 ib->cb(ib, stat, nbytes, ib->token); 696 } 697} 698 699static tk1_i2c_pktheaders_t 700tk1_i2c_prepare_mmode_xfer_headers(i2c_slave_t *sl, size_t nbytes, 701 bool is_write, 702 bool send_repeat_start_not_stop) 703{ 704 tk1_i2c_pktheaders_t headers; 705 tk1_i2c_state_t *state; 706 707 assert(sl != NULL); 708 assert(sl->bus != NULL); 709 assert(nbytes > 0); 710 711 state = tk1_i2c_get_state(sl->bus); 712 713 headers.io0 = headers.io1 = headers.i2c = 0; 714 715 headers.io0 = (0 << TK1I2C_TXPKT0_PKTTYPE_SHIFT) 716 | (TK1I2C_TXPKT0_PROTOCOL_I2C << TK1I2C_TXPKT0_PROTOCOL_SHIFT) 717 /* Linux uses a 0-based device index for the ID. */ 718 | (state->controller_id << TK1I2C_TXPKT0_CONTROLLER_ID_SHIFT) 719 /* The PktID is optional, AFAICT. Linux uses the value "1" always. */ 720 | (1 << TK1I2C_TXPKT0_PKTID_SHIFT) 721 /* TK1 TRM Section 33.2.2.1: Table 133: 722 * "For I2C, ProtHdrSize = 0 for request packets and 1 for response 723 * packets" 724 * 725 * Values: 726 * 0 = 1 word; 1 = 2 words; 3 = 4 words. 727 */ 728 | (0 << TK1I2C_TXPKT0_PROTHDR_SIZE_SHIFT); 729 730 headers.io1 = ((nbytes - 1) & TK1I2C_TXPKT1_PAYLOAD_SIZE_MASK) 731 << TK1I2C_TXPKT1_PAYLOAD_SIZE_SHIFT; 732 733 headers.i2c = TK1I2C_I2CPKT_IRQ_ON_COMPLETION_BIT 734 | (send_repeat_start_not_stop ? TK1I2C_I2CPKT_SEND_REPEAT_START_NOT_STOP_BIT : 0) 735 | (is_write ? 0 : TK1I2C_I2CPKT_READ_XFER_BIT) 736 | TK1I2C_I2CPKT_RESPONSE_PKT_ENABLE_BIT; 737 738 if (sl->address_size == I2C_SLAVE_ADDR_10BIT) { 739 headers.i2c |= TK1I2C_I2CPKT_10_BIT_ADDRESS_BIT; 740 headers.i2c |= (sl->address & TK1I2C_I2CPKT_SLAVE_ADDR_10BIT_MASK) 741 << TK1I2C_I2CPKT_SLAVE_ADDR_10BIT_SHIFT; 742 } else { 743 /* TK1 TRM Section 33.2.5, Table 135: 744 * "Slave Address. Bit 0 is ignored for 7-bit addressing, but should 745 * always match bit 19 (READ/WRITE)." 746 */ 747 headers.i2c |= (is_write ? 0 : 1); 748 headers.i2c |= (sl->address & TK1I2C_I2CPKT_SLAVE_ADDR_7BIT_MASK) 749 << TK1I2C_I2CPKT_SLAVE_ADDR_7BIT_SHIFT; 750 } 751 752 if (sl->max_speed == I2C_SLAVE_SPEED_HIGHSPEED) { 753 /* Enable HS mode bit and set HS master mode address. */ 754 headers.i2c |= TK1I2C_I2CPKT_HS_MODE_BIT; 755 /* Shouldn't need to mask it because we masked it in 756 * set_hsmode_master_addr. 757 */ 758 headers.i2c |= state->master.hsmode_master_address 759 << TK1I2C_I2CPKT_HS_MASTER_ADDR_SHIFT; 760 } 761 762 if (sl->i2c_opts & I2C_SLAVE_OPTS_DEVICE_DOES_NOT_ACK) { 763 /* Enable handling of NACK when ACK is expected. */ 764 headers.i2c |= TK1I2C_I2CPKT_CONTINUE_ON_NACK_BIT; 765 } 766 767 if (sl->i2c_opts & TK1I2C_SLAVE_FLAGS_XFER_IN_PROGRESS_BIT) { 768 headers.i2c |= TK1I2C_I2CPKT_CONTINUE_XFER_BIT; 769 } 770 771 return headers; 772} 773 774/** Takes a buffer and attempts to write as much of it as it can to the master 775 * or slave mode TX FIFO. 776 * 777 * Always begins reading the data from index 0 in the buffer. 778 * 779 * @return number of bytes that were written out to the FIFO from the buffer. 780 */ 781static size_t 782tk1_i2c_fill_tx_fifo(i2c_bus_t *ib, enum i2c_xfer_mode mode, 783 const void *const _data, size_t buffsize) 784{ 785 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 786 volatile uint32_t *tx_fifo_reg; 787 size_t i, empty_fifo_words, buff_remaining; 788 uint32_t *data = (uint32_t *)_data; 789 790 if (mode == I2C_MODE_MASTER) { 791 tx_fifo_reg = &r->tx_packet_fifo; 792 empty_fifo_words = r->fifo_status >> TK1I2C_FIFO_STATUS_MMODE_TX_EMPTY_SHIFT 793 & TK1I2C_FIFO_STATUS_MMODE_TX_EMPTY_MASK; 794 } else { 795 tx_fifo_reg = &r->tx_packet_fifo; 796 empty_fifo_words = r->fifo_status >> TK1I2C_FIFO_STATUS_SMODE_TX_EMPTY_SHIFT 797 & TK1I2C_FIFO_STATUS_SMODE_TX_EMPTY_MASK; 798 } 799 800 buff_remaining = buffsize; 801 for (i = 0; i < empty_fifo_words && buff_remaining >= TK1I2C_NBYTES_PER_FIFO_WORD; i++) { 802 *tx_fifo_reg = data[i]; 803 buff_remaining -= TK1I2C_NBYTES_PER_FIFO_WORD; 804 } 805 806 if (i < empty_fifo_words && buff_remaining > 0) { 807 uint8_t *last_word_data = (uint8_t *)&data[i]; 808 uint32_t last_word = 0; 809 810 if (buff_remaining >= TK1I2C_NBYTES_PER_FIFO_WORD) { 811 ZF_LOGF("Bug: shifting last word with %d bytes remaining in buffer.", 812 buff_remaining); 813 } 814 815 for (int j = 0; j < buff_remaining; j++) { 816 last_word |= last_word_data[j] << (8 * j); 817 } 818 *tx_fifo_reg = last_word; 819 buff_remaining -= buff_remaining; 820 } 821 822 return buffsize - buff_remaining; 823} 824 825/** Takes a buffer and attempts to read as much data from the master or slave 826 * mode RX FIFO into that buffer. 827 * 828 * Always begins writing into the buffer at index 0. 829 * 830 * @return number of bytes read from the FIFO into the buffer. 831 */ 832static size_t 833tk1_i2c_drain_rx_fifo(i2c_bus_t *ib, enum i2c_xfer_mode mode, 834 void *const _data, size_t buffsize) 835{ 836 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 837 volatile uint32_t *rx_fifo_reg; 838 size_t i, avail_fifo_words, buff_remaining; 839 uint32_t *data32 = (uint32_t *)_data; 840 841 if (mode == I2C_MODE_MASTER) { 842 rx_fifo_reg = &r->rx_fifo; 843 avail_fifo_words = r->fifo_status >> TK1I2C_FIFO_STATUS_MMODE_RX_FULL_SHIFT 844 & TK1I2C_FIFO_STATUS_MMODE_RX_FULL_MASK; 845 } else { 846 rx_fifo_reg = &r->rx_fifo; 847 avail_fifo_words = r->fifo_status >> TK1I2C_FIFO_STATUS_SMODE_RX_FULL_SHIFT 848 & TK1I2C_FIFO_STATUS_SMODE_RX_FULL_MASK; 849 } 850 851 buff_remaining = buffsize; 852 for (i = 0; i < avail_fifo_words && buff_remaining >= TK1I2C_NBYTES_PER_FIFO_WORD; i++) { 853 data32[i] = *rx_fifo_reg; 854 buff_remaining -= TK1I2C_NBYTES_PER_FIFO_WORD; 855 } 856 857 if (i < avail_fifo_words && buff_remaining > 0) { 858 uint8_t *last_word_data = (uint8_t *)&data32[i]; 859 uint32_t last_word = *rx_fifo_reg; 860 861 if (buff_remaining >= TK1I2C_NBYTES_PER_FIFO_WORD) { 862 ZF_LOGF("Bug: shifting last word out of RX fifo when it's not the " 863 "last word."); 864 } 865 866 for (int j = 0; j < buff_remaining; j++) { 867 last_word_data[j] = last_word & 0xFF; 868 last_word >>= 8; 869 } 870 buff_remaining -= buff_remaining; 871 /* Increment i for the case where there were more words in the FIFO. 872 * This case will be picked up below. 873 */ 874 i++; 875 } 876 877 /* Handle the case where the user provided a buffer that is smaller than the 878 * amount of data that the device will actually send. We flush the FIFOS 879 * here to deal with this case. 880 * 881 * There is always 1 extra word in the RX FIFO at the end, so ignore it. 882 */ 883 if (i < avail_fifo_words - 1 && buff_remaining == 0) { 884 ZF_LOGW("Bug: usermode buffer is too small for received data. %d of %d words read from fifo.\n" 885 "\tOther word was 0x%x. pkt trans status 0x%x. After reading, fifo status is %d", 886 i, avail_fifo_words, *rx_fifo_reg, r->packet_transfer_status, 887 (r->fifo_status >> TK1I2C_FIFO_STATUS_MMODE_RX_FULL_SHIFT 888 & TK1I2C_FIFO_STATUS_MMODE_RX_FULL_MASK)); 889 tk1_i2c_flush_fifos(ib, mode); 890 } 891 892 return buffsize - buff_remaining; 893} 894 895/** Handle a master-mode IRQ. 896 * 897 * Basically either fill the Tx fifo for an ongoing send operation, or empty the 898 * RX fifo for an ongoing receive operation. 899 */ 900#define IRQPREFIX "I2C %p: IRQ: " 901static void 902tk1_i2c_mmode_handle_irq(i2c_bus_t* ib) 903{ 904 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 905 tk1_i2c_state_t *s = tk1_i2c_get_state(ib); 906 UNUSED uint32_t int_status; 907 int err, do_callback=0, callback_status, callback_nbytes=0, reason_known=0; 908 909 const uint32_t error_int_statuses_mask = 910 TK1I2C_INTSTATUS_MMODE_TX_FIFO_OVF_BIT 911 | TK1I2C_INTSTATUS_MMODE_RX_FIFO_UNR_BIT 912 | TK1I2C_INTSTATUS_MMODE_NO_ACK_BIT 913 | TK1I2C_INTSTATUS_MMODE_ARBITRATION_LOST_BIT; 914 915 const uint32_t data_available_int_statuses_mask = 916 TK1I2C_INTSTATUS_MMODE_TX_FIFO_DATA_REQ_BIT 917 | TK1I2C_INTSTATUS_MMODE_RX_FIFO_DATA_REQ_BIT; 918 919 const uint32_t xfer_successful_completion_statuses_mask = 920 TK1I2C_INTSTATUS_MMODE_PACKET_XFER_COMPLETE_BIT 921 | TK1I2C_INTSTATUS_MMODE_ALL_PACKETS_XFER_COMPLETE_BIT; 922 923 int_status = r->interrupt_status; 924 925 /* Regardless of whether or not an error occured on the line, we should 926 * unconditionally read the data that did get transferred before the error 927 * occured, if any such data exists. 928 */ 929 if (int_status & data_available_int_statuses_mask) { 930 reason_known = 1; 931 932 if (int_status & TK1I2C_INTSTATUS_MMODE_TX_FIFO_DATA_REQ_BIT 933 && s->master.is_write) { 934 935 /* Refill TX fifo. */ 936 if (s->master.xfer_cursor <= s->master.nbytes) { 937 err = tk1_i2c_fill_tx_fifo(ib, I2C_MODE_MASTER, 938 &s->master.buff[s->master.xfer_cursor], 939 s->master.nbytes - s->master.xfer_cursor); 940 941 if (err < 0) { 942 ZF_LOGF(IRQPREFIX "TX FIFO trigger IRQ came in, but " 943 "TX FIFO is full.", r); 944 } 945 946 s->master.xfer_cursor += err; 947 if (s->master.xfer_cursor > s->master.nbytes) { 948 ZF_LOGF("Bug: TX userspace buffer has been overshot by driver!"); 949 } 950 951 if (s->master.xfer_cursor == s->master.nbytes) { 952 /* Disable TX FIFO trigger IRQ and then when the XFER_COMPLETE 953 * IRQ comes in, callback. 954 */ 955 tk1_i2c_toggle_irq(ib, false, TK1I2C_INTMASK_MMODE_TX_FIFO_DATA_REQ_BIT); 956 } 957 } else { 958 ZF_LOGF(IRQPREFIX "TX FIFO data req IRQ has read beyond " 959 "userspace buffer!\n" 960 "\txfer_cursor %d, nbytes %d.", 961 r, s->master.xfer_cursor, s->master.nbytes); 962 } 963 } 964 965 if (int_status & TK1I2C_INTSTATUS_MMODE_RX_FIFO_DATA_REQ_BIT 966 && !s->master.is_write) { 967 968 /* Drain RX fifo. */ 969 if (s->master.xfer_cursor <= s->master.nbytes) { 970 err = tk1_i2c_drain_rx_fifo(ib, I2C_MODE_MASTER, 971 &s->master.buff[s->master.xfer_cursor], 972 s->master.nbytes - s->master.xfer_cursor); 973 974 if (err < 0) { 975 ZF_LOGF(IRQPREFIX "RX FIFO trigger IRQ came in, but " 976 "RX FIFO is empty.", r); 977 } 978 979 s->master.xfer_cursor += err; 980 if (s->master.xfer_cursor > s->master.nbytes) { 981 ZF_LOGF("Bug: RX userspace buffer has been overshot by driver!"); 982 } 983 984 if (s->master.xfer_cursor == s->master.nbytes) { 985 /* Disable RX FIFO trigger IRQ and then when the XFER_COMPLETE 986 * IRQ comes in, callback. 987 */ 988 tk1_i2c_toggle_irq(ib, false, TK1I2C_INTMASK_MMODE_RX_FIFO_DATA_REQ_BIT); 989 } 990 } else { 991 ZF_LOGF(IRQPREFIX "RX FIFO data req IRQ has overrun userspace " 992 "buffer.\n" 993 "\txfer_cursor %d, nbytes %d.", 994 r, s->master.xfer_cursor, s->master.nbytes); 995 } 996 } 997 } 998 999 /* If an error did occur, we need to decide what error condition to return. 1000 * We want error conditions to take precedence over the completion 1001 * condition. 1002 */ 1003 if (int_status & error_int_statuses_mask) { 1004 reason_known = 1; 1005 do_callback = 1; 1006 callback_status = I2CSTAT_ERROR; 1007 callback_nbytes = s->master.xfer_cursor; 1008 1009 /* We would ideally like to return a bitfield with all the errors that 1010 * occured, but since the API doesn't allow this, we arbitrarily 1011 * choose the first one that we come across and return that one. 1012 */ 1013 if (int_status & TK1I2C_INTSTATUS_MMODE_TX_FIFO_OVF_BIT) { 1014 ZF_LOGF(IRQPREFIX "TX FIFO has been overflowed.", r); 1015 // Use I2CSTAT_ERROR. 1016 } else if (int_status & TK1I2C_INTSTATUS_MMODE_RX_FIFO_UNR_BIT) { 1017 ZF_LOGF(IRQPREFIX "RX FIFO has been underrun.", r); 1018 // Use I2CSTAT_ERROR. 1019 } else if (int_status & TK1I2C_INTSTATUS_MMODE_NO_ACK_BIT) { 1020 ZF_LOGE(IRQPREFIX "Slave failed to send ACK. Does this slave " 1021 "require continue_on_nack?", r); 1022 tk1_i2c_handle_nack(ib); 1023 callback_status = I2CSTAT_NACK; 1024 } else if (int_status & TK1I2C_INTSTATUS_MMODE_ARBITRATION_LOST_BIT) { 1025 ZF_LOGW(IRQPREFIX "Lost arbitration.", r); 1026 tk1_i2c_handle_arbitration_loss(ib); 1027 callback_status = I2CSTAT_ARBITRATION_LOST; 1028 } 1029 } 1030 1031 if (int_status & xfer_successful_completion_statuses_mask) { 1032 reason_known = 1; 1033 do_callback = 1; 1034 callback_nbytes = s->master.xfer_cursor; 1035 1036 if (s->master.xfer_cursor < s->master.nbytes) { 1037 ZF_LOGF(IRQPREFIX"Bug: Got \"PKT_XFER_COMPLETE\" IRQ when there " 1038 "were bytes remaining to be xmitted.", r); 1039 } 1040 1041 if (int_status & TK1I2C_INTSTATUS_MMODE_PACKET_XFER_COMPLETE_BIT) { 1042 ZF_LOGD(IRQPREFIX"Xfer complete, pktstatus is 0x%x, i2cstatus is 0x%x.", r, 1043 r->packet_transfer_status, r->status); 1044 /* XFER_COMPLETE IRQ has occured: callback into userspace. 1045 * Keep in mind that the controller can set both the RX/TX trigger 1046 * IRQ status bits and the XFER_COMPLETE IRQ status bit, 1047 * so the XFER_COMPLETE IRQ doesn't actually have to be a separate 1048 * IRQ. 1049 */ 1050 callback_status = I2CSTAT_COMPLETE; 1051 } 1052 if (int_status & TK1I2C_INTSTATUS_MMODE_ALL_PACKETS_XFER_COMPLETE_BIT) { 1053 ZF_LOGD(IRQPREFIX"Got an \"ALL_PKTS_XFER_COMPLETE\" IRQ.", r); 1054 } 1055 } 1056 1057 if (!reason_known) { 1058 ZF_LOGE(IRQPREFIX"IRQ occurred for unknown reason.", r); 1059 } 1060 1061 /* TK1 TRM Section 33.5.23: 1062 * "This register indicates the status bit for which the interrupt is 1063 * set. If the interrupt is set, write a 1 to clear it." 1064 */ 1065 if (do_callback == 1) { 1066 tk1_i2c_callback(ib, callback_status, callback_nbytes); 1067 } 1068 tk1_i2c_acknowledge_irq(ib, int_status); 1069 return; 1070} 1071 1072UNUSED static int 1073tk1_i2c_mmode_xfer(i2c_slave_t *sl, void *data, size_t nbytes, bool is_write) 1074{ 1075 return 0; 1076} 1077 1078UNUSED static int 1079tk1_i2c_smode_xfer(void *data, size_t nbytes, bool is_write) 1080{ 1081 return 0; 1082} 1083 1084static int 1085tk1_i2c_mmode_read(i2c_slave_t* slave, void* buf, size_t size, 1086 bool end_with_repeat_start, 1087 i2c_callback_fn cb, void* token) 1088{ 1089 assert(slave != NULL); 1090 assert(slave->bus != NULL); 1091 int error; 1092 1093 tk1_i2c_state_t *s = tk1_i2c_get_state(slave->bus); 1094 tk1_i2c_regs_t *r = tk1_i2c_get_priv(slave->bus); 1095 tk1_i2c_pktheaders_t headers; 1096 1097 if (size == 0) { 1098 tk1_i2c_callback(slave->bus, I2CSTAT_COMPLETE, 0); 1099 return 0; 1100 } 1101 1102 error = tk1_i2c_set_speed(slave->bus, slave->max_speed); 1103 if (error < 0) { 1104 ZF_LOGE(PREFIX"Failed to set speed to %d for slave 0x%x.", 1105 r, i2c_speed_freqs[slave->max_speed], slave->address); 1106 return -1; 1107 } 1108 1109 tk1_i2c_flush_fifos(slave->bus, I2C_MODE_MASTER); 1110 1111 if (tk1_i2c_bus_is_locked_up(slave->bus)) { 1112 if (!tk1_i2c_bus_clear(slave->bus, true)) { 1113 ZF_LOGE(PREFIX"slave is holding SDA line low, and bus clear " 1114 "failed.", r); 1115 return -1; 1116 } 1117 } 1118 1119 s->master.slave_id = slave->address; 1120 s->master.is_write = false; 1121 s->master.buff = buf; 1122 s->master.nbytes = size; 1123 s->master.xfer_cursor = 0; 1124 1125 slave->bus->cb = cb; 1126 slave->bus->token = token; 1127 1128 tk1_i2c_set_mode(slave->bus, I2C_MODE_MASTER); 1129 tk1_i2c_config_commit(slave->bus, COMMIT_MASTER_BIT); 1130 1131 headers = tk1_i2c_prepare_mmode_xfer_headers(slave, size, false, 1132 end_with_repeat_start); 1133 r->tx_packet_fifo = headers.io0; 1134 r->tx_packet_fifo = headers.io1; 1135 r->tx_packet_fifo = headers.i2c; 1136 1137 /* Enable RX FIFO trigger IRQ. */ 1138 tk1_i2c_toggle_irq(slave->bus, true, TK1I2C_INTMASK_SMODE_RX_FIFO_DATA_REQ_BIT); 1139 1140 return 0; 1141} 1142 1143static int 1144tk1_i2c_mmode_write(i2c_slave_t *slave, const void* buf, size_t size, 1145 bool end_with_repeat_start, 1146 i2c_callback_fn cb, void* token) 1147{ 1148 assert(slave != NULL); 1149 assert(slave->bus != NULL); 1150 int error; 1151 1152 size_t ret; 1153 tk1_i2c_regs_t *r = tk1_i2c_get_priv(slave->bus); 1154 tk1_i2c_state_t *s = tk1_i2c_get_state(slave->bus); 1155 tk1_i2c_pktheaders_t headers; 1156 1157 if (size == 0) { 1158 tk1_i2c_callback(slave->bus, I2CSTAT_COMPLETE, 0); 1159 return 0; 1160 } 1161 1162 if (size > TK1I2C_DATA_MAX_NBYTES) { 1163 ZF_LOGE(PREFIX"Write: xfer sizes > %d not supported.", 1164 r, TK1I2C_DATA_MAX_NBYTES); 1165 return -1; 1166 } 1167 1168 error = tk1_i2c_set_speed(slave->bus, slave->max_speed); 1169 if (error < 0) { 1170 ZF_LOGE(PREFIX"Failed to set speed to %d for slave 0x%x.", 1171 r, i2c_speed_freqs[slave->max_speed], slave->address); 1172 return -1; 1173 } 1174 1175 tk1_i2c_flush_fifos(slave->bus, I2C_MODE_MASTER); 1176 1177 if (tk1_i2c_bus_is_locked_up(slave->bus)) { 1178 if (!tk1_i2c_bus_clear(slave->bus, true)) { 1179 ZF_LOGE(PREFIX"slave is holding SDA line low, and bus clear " 1180 "failed.", r); 1181 return -1; 1182 } 1183 } 1184 1185 s->master.slave_id = slave->address; 1186 s->master.is_write = true; 1187 s->master.buff = (uint8_t *)buf; 1188 s->master.nbytes = size; 1189 s->master.xfer_cursor = 0; 1190 1191 slave->bus->cb = cb; 1192 slave->bus->token = token; 1193 1194 tk1_i2c_set_mode(slave->bus, I2C_MODE_MASTER); 1195 tk1_i2c_config_commit(slave->bus, COMMIT_MASTER_BIT); 1196 1197 headers = tk1_i2c_prepare_mmode_xfer_headers(slave, size, true, 1198 end_with_repeat_start); 1199 r->tx_packet_fifo = headers.io0; 1200 r->tx_packet_fifo = headers.io1; 1201 r->tx_packet_fifo = headers.i2c; 1202 ret = tk1_i2c_fill_tx_fifo(slave->bus, I2C_MODE_MASTER, buf, size); 1203 if (ret < 1) { 1204 /* Keep in mind that not being able to write bytes out to the FIFO 1205 * doesn't mean an error occured. 1206 */ 1207 ZF_LOGE(PREFIX"Failed to write out bytes to line.", r); 1208 return -1; 1209 } else { 1210 s->master.xfer_cursor = ret; 1211 } 1212 1213 /* Enable TX FIFO trigger IRQ */ 1214 tk1_i2c_toggle_irq(slave->bus, true, TK1I2C_INTMASK_MMODE_TX_FIFO_DATA_REQ_BIT); 1215 1216 return s->master.xfer_cursor; 1217} 1218 1219static void 1220tk1_i2c_set_hsmode_master_address(i2c_bus_t* ib, int addr) 1221{ 1222 tk1_i2c_state_t *s = tk1_i2c_get_state(ib); 1223 1224 s->master.hsmode_master_address = addr & TK1I2C_I2CPKT_HS_MASTER_ADDR_MASK; 1225} 1226 1227static void 1228tk1_i2c_register_slave_event_handler(i2c_bus_t* ib, 1229 i2c_aas_callback_fn aas_cb, void *token) 1230{ 1231 ib->aas_cb = aas_cb; 1232 ib->aas_token = token; 1233} 1234 1235static int 1236tk1_i2c_slave_init(i2c_bus_t* ib, int address, 1237 enum i2c_slave_address_size address_size, 1238 enum i2c_slave_speed max_speed, 1239 uint32_t flags, i2c_slave_t* sl) 1240{ 1241 assert(sl != NULL); 1242 1243 if (address_size == I2C_SLAVE_ADDR_7BIT) { 1244 address = i2c_extract_address(address); 1245 } 1246 1247 /* Internally in this driver, we discard the RW bit */ 1248 sl->address = address; 1249 sl->address_size = address_size; 1250 sl->max_speed = max_speed; 1251 sl->i2c_opts = flags; 1252 sl->bus = ib; 1253 1254 sl->slave_read = &tk1_i2c_mmode_read; 1255 sl->slave_write = &tk1_i2c_mmode_write; 1256 1257 return 0; 1258} 1259 1260static void 1261tk1_i2c_set_mmode_trigger_levels(i2c_bus_t *ib, 1262 uint8_t tx_trig, uint8_t rx_trig) 1263{ 1264 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 1265 1266 r->fifo_control &= ~((TK1I2C_FIFO_CONTROL_MMODE_TX_TRIG_MASK << TK1I2C_FIFO_CONTROL_MMODE_TX_TRIG_SHIFT) 1267 | (TK1I2C_FIFO_CONTROL_MMODE_RX_TRIG_MASK << TK1I2C_FIFO_CONTROL_MMODE_RX_TRIG_SHIFT)); 1268 1269 r->fifo_control |= ((tx_trig & TK1I2C_FIFO_CONTROL_MMODE_TX_TRIG_MASK) 1270 << TK1I2C_FIFO_CONTROL_MMODE_TX_TRIG_SHIFT) 1271 | ((rx_trig & TK1I2C_FIFO_CONTROL_MMODE_RX_TRIG_MASK) 1272 << TK1I2C_FIFO_CONTROL_MMODE_RX_TRIG_SHIFT); 1273} 1274 1275UNUSED static void 1276tk1_i2c_set_smode_trigger_levels(i2c_bus_t *ib, 1277 uint8_t tx_trig, uint8_t rx_trig) 1278{ 1279 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 1280 1281 r->fifo_control &= ~((TK1I2C_FIFO_CONTROL_SMODE_TX_TRIG_MASK << TK1I2C_FIFO_CONTROL_SMODE_TX_TRIG_SHIFT) 1282 | (TK1I2C_FIFO_CONTROL_SMODE_RX_TRIG_MASK << TK1I2C_FIFO_CONTROL_SMODE_RX_TRIG_SHIFT)); 1283 1284 r->fifo_control |= ((tx_trig & TK1I2C_FIFO_CONTROL_SMODE_TX_TRIG_MASK) 1285 << TK1I2C_FIFO_CONTROL_SMODE_TX_TRIG_SHIFT) 1286 | ((rx_trig & TK1I2C_FIFO_CONTROL_SMODE_RX_TRIG_MASK) 1287 << TK1I2C_FIFO_CONTROL_SMODE_RX_TRIG_SHIFT); 1288} 1289 1290static int 1291tk1_i2c_master_stop(i2c_bus_t *ib) 1292{ 1293 return tk1_i2c_bus_clear(ib, true); 1294} 1295 1296static int 1297tk1_i2c_initialize_controller(i2c_bus_t *ib) 1298{ 1299 tk1_i2c_regs_t *r = tk1_i2c_get_priv(ib); 1300 1301 tk1_i2c_set_packet_mode(ib, true); 1302 1303 if (tk1_i2c_bus_is_locked_up(ib)) { 1304 if (!tk1_i2c_bus_clear(ib, true)) { 1305 ZF_LOGE(PREFIX"slave is holding SDA line low, and bus clear " 1306 "failed.", r); 1307 return -1; 1308 } 1309 } 1310 1311 tk1_i2c_set_mmode_trigger_levels(ib, 7, 0); 1312 tk1_i2c_flush_fifos(ib, I2C_MODE_MASTER); 1313 tk1_i2c_flush_fifos(ib, I2C_MODE_SLAVE); 1314 1315 /* ACK all IRQs that the chip currently has active, in case one was 1316 * asserted. Perhaps the driver is being restarted, for example. 1317 */ 1318 tk1_i2c_acknowledge_irq(ib, r->interrupt_status); 1319 1320 /* Disable those IRQs we either will never want, or will conditionally need 1321 * to enable later. 1322 * 1323 * Master mode IRQs. 1324 */ 1325 tk1_i2c_toggle_irq(ib, false, 1326 TK1I2C_INTMASK_MMODE_TX_FIFO_DATA_REQ_BIT 1327 | TK1I2C_INTMASK_MMODE_RX_FIFO_DATA_REQ_BIT 1328 | TK1I2C_INTMASK_MMODE_BUS_CLEAR_DONE_BIT 1329 | TK1I2C_INTMASK_MMODE_ALL_PACKETS_XFER_COMPLETE_BIT); 1330 1331 tk1_i2c_toggle_irq(ib, true, 1332 TK1I2C_INTMASK_MMODE_ARBITRATION_LOST_BIT 1333 | TK1I2C_INTMASK_MMODE_NO_ACK_BIT 1334 | TK1I2C_INTMASK_MMODE_TX_FIFO_OVF_BIT 1335 | TK1I2C_INTMASK_MMODE_RX_FIFO_UNR_BIT 1336 | TK1I2C_INTMASK_MMODE_PACKET_XFER_COMPLETE_BIT); 1337 1338 /* Slave mode IRQs. */ 1339 tk1_i2c_toggle_irq(ib, false, 1340 TK1I2C_INTMASK_SMODE_TX_FIFO_DATA_REQ_BIT 1341 | TK1I2C_INTMASK_SMODE_RX_FIFO_DATA_REQ_BIT 1342 | TK1I2C_INTMASK_SMODE_TX_BUFFER_REQ_BIT 1343 | TK1I2C_INTMASK_SMODE_RX_BUFFER_FULL_BIT); 1344 1345 tk1_i2c_toggle_irq(ib, true, 1346 TK1I2C_INTMASK_SMODE_TX_FIFO_OVF_BIT 1347 | TK1I2C_INTMASK_SMODE_RX_FIFO_UNR_BIT 1348 | TK1I2C_INTMASK_SMODE_PACKET_XFER_COMPLETE_BIT 1349 | TK1I2C_INTMASK_SMODE_PACKET_XFER_ERROR_BIT 1350 | TK1I2C_INTMASK_SMODE_SWITCHED_READ2WRITE_BIT 1351 | TK1I2C_INTMASK_SMODE_SWITCHED_WRITE2READ_BIT 1352 | TK1I2C_INTMASK_SMODE_ACK_WITHHELD_BIT); 1353 1354 tk1_i2c_config_commit(ib, COMMIT_MASTER_BIT | COMMIT_SLAVE_BIT); 1355 return 0; 1356} 1357 1358int 1359tegra_i2c_init(int controller_id, void *vaddr, ps_io_ops_t *io_ops, 1360 i2c_bus_t *ib) 1361{ 1362 tk1_i2c_state_t *s; 1363 int error; 1364 1365 error = ps_malloc(&io_ops->malloc_ops, sizeof(*s), (void **)&s); 1366 if (error != 0 || s == NULL) { 1367 ZF_LOGE(PREFIX"Failed to malloc internal state.", vaddr); 1368 return -1; 1369 }; 1370 1371 s->regs = vaddr; 1372 s->controller_id = controller_id; 1373 ib->priv = s; 1374 1375 ib->cb = NULL; 1376 ib->token = NULL; 1377 ib->aas_cb = NULL; 1378 ib->aas_token = NULL; 1379 1380 ib->slave_init = &tk1_i2c_slave_init; 1381 ib->handle_irq = &tk1_i2c_mmode_handle_irq; 1382 ib->set_speed = &tk1_i2c_set_speed; 1383 ib->set_self_slave_address = NULL; 1384 ib->register_slave_event_handler= &tk1_i2c_register_slave_event_handler; 1385 ib->set_hsmode_master_address = &tk1_i2c_set_hsmode_master_address; 1386 /* Bus clear */ 1387 ib->master_stop = &tk1_i2c_master_stop; 1388 1389 error = tk1_i2c_initialize_controller(ib); 1390 if (error != 0) { 1391 ZF_LOGE(PREFIX"Failed to initialize I2C controller.", vaddr); 1392 ib->priv = NULL; 1393 ps_free(&io_ops->malloc_ops, sizeof(*s), s); 1394 return -1; 1395 } 1396 return 0; 1397} 1398 1399int 1400i2c_init(enum i2c_id id, ps_io_ops_t* io_ops, i2c_bus_t* i2c_bus) 1401{ 1402 void *vaddr; 1403 1404 assert(io_ops != NULL); 1405 assert(i2c_bus != NULL); 1406 1407 switch (id) { 1408 case TK1_I2C0: 1409 vaddr = RESOURCE(io_ops, TK1_I2C0); 1410 break; 1411 1412 case TK1_I2C1: 1413 vaddr = RESOURCE(io_ops, TK1_I2C1); 1414 break; 1415 1416 case TK1_I2C2: 1417 vaddr = RESOURCE(io_ops, TK1_I2C2); 1418 break; 1419 1420 case TK1_I2C3: 1421 vaddr = RESOURCE(io_ops, TK1_I2C3); 1422 break; 1423 1424 case TK1_I2C4: 1425 vaddr = RESOURCE(io_ops, TK1_I2C4); 1426 break; 1427 1428 case TK1_I2C5: 1429 vaddr = RESOURCE(io_ops, TK1_I2C5); 1430 break; 1431 1432 default: 1433 ZF_LOGE("Unknown I2C controller %d.", id); 1434 return -1; 1435 } 1436 1437 if (vaddr == NULL) { 1438 ZF_LOGE("Failed to map in TK1 I2C controller %d.", id); 1439 return -1; 1440 } 1441 1442 return tegra_i2c_init(id, vaddr, io_ops, i2c_bus); 1443} 1444