1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12#include <stddef.h> 13 14#include <utils/arith.h> 15#include <utils/fence.h> 16#include <utils/attribute.h> 17#include <platsupport/gpio.h> 18#include <platsupport/plat/gpio.h> 19 20#include "mux_gpio_priv.h" 21#include "../../services.h" 22 23/** @file GPIO driver for the TK1. 24 * 25 * Contains routines for manipulating GPIO pins on the TK1. 26 * 27 * PREREQUISITES: 28 * This driver currently assumes that the MMIO registers it accesses are mapped 29 * as strongly ordered and uncached. The driver makes no attempts whatsoever at 30 * managing the write buffer or managing ordering of reads and writes. 31 */ 32 33#define GPIO_CONTROLLER1_ADDR_OFFSET 0 34#define GPIO_CONTROLLER2_ADDR_OFFSET 0x100 35#define GPIO_CONTROLLER3_ADDR_OFFSET 0x200 36#define GPIO_CONTROLLER4_ADDR_OFFSET 0x300 37#define GPIO_CONTROLLER5_ADDR_OFFSET 0x400 38#define GPIO_CONTROLLER6_ADDR_OFFSET 0x500 39#define GPIO_CONTROLLER7_ADDR_OFFSET 0x600 40#define GPIO_CONTROLLER8_ADDR_OFFSET 0x700 41 42#define PORT_NBITS (8) 43#define REG_VALID_BITS_MASK (0xFF) 44#define CNFREG_VALID_BITS_MASK (0xFFFF) 45 46enum tk1_gpio_bank_regs { 47 GPIO_CNF = 0, 48 GPIO_OE, 49 GPIO_OUT, 50 GPIO_IN, 51 GPIO_INT_STA, 52 GPIO_INT_ENB, 53 GPIO_INT_LVL, 54 GPIO_INT_CLR, 55 GPIO_MSK_CNF, 56 GPIO_MSK_OE, 57 GPIO_MSK_OUT, 58 /* 0xB is invalid - no register exists there */ 59 GPIO_REG_INVALID = 0xB, 60 GPIO_MSK_INT_STA, 61 GPIO_MSK_INT_ENB, 62 GPIO_MSK_INT_LVL, 63 64 TEGRA_GPIO_REGS 65}; 66 67#define GPIO_PORT1 0x0 68#define GPIO_PORT2 0x4 69#define GPIO_PORT3 0x8 70#define GPIO_PORT4 0xC 71 72#define TEGRA_GPIO_PORTS 4 73#define TEGRA_GPIO_BANKS 8 74 75#define GPIO_BANK(x) ((x) >> 5) 76#define GPIO_PORT(x) (((x) >> 3) & 0x3) 77#define GPIO_BIT(x) ((x) & 0x7) 78 79#define GPIO_INT_LVL_MASK 0x010101 80#define GPIO_INT_LVL_EDGE_RISING 0x000101 81#define GPIO_INT_LVL_EDGE_FALLING 0x000100 82#define GPIO_INT_LVL_EDGE_BOTH 0x010100 83#define GPIO_INT_LVL_LEVEL_HIGH 0x000001 84#define GPIO_INT_LVL_LEVEL_LOW 0x000000 85 86/* Used for debug output */ 87static uint32_t tegra_gpio_controller[] = { GPIO_CONTROLLER1_ADDR_OFFSET, 88 GPIO_CONTROLLER2_ADDR_OFFSET, 89 GPIO_CONTROLLER3_ADDR_OFFSET, 90 GPIO_CONTROLLER4_ADDR_OFFSET, 91 GPIO_CONTROLLER5_ADDR_OFFSET, 92 GPIO_CONTROLLER6_ADDR_OFFSET, 93 GPIO_CONTROLLER7_ADDR_OFFSET, 94 GPIO_CONTROLLER8_ADDR_OFFSET 95 }; 96 97static uint32_t tegra_gpio_port[] = { GPIO_PORT1, 98 GPIO_PORT2, 99 GPIO_PORT3, 100 GPIO_PORT4 101 }; 102 103typedef struct tk1_gpio_ { 104 volatile uint32_t ports[TEGRA_GPIO_PORTS]; 105} tk1_gpio_ports_t; 106static_assert(sizeof(tk1_gpio_ports_t) == 16, "Ports struct should be 16 bytes"); 107 108typedef struct tk1_gpio_bank_ { 109 tk1_gpio_ports_t regs[TEGRA_GPIO_REGS]; 110 PAD_STRUCT_BETWEEN(0x0, 111 0x100, 112 tk1_gpio_ports_t[TEGRA_GPIO_REGS]); 113} tk1_gpio_bank_t; 114static_assert(sizeof(tk1_gpio_bank_t) == 256, "Banks should be 256 bytes each"); 115 116typedef struct tk1_gpio_regs_ { 117 tk1_gpio_bank_t bank[TEGRA_GPIO_BANKS]; 118} tk1_gpio_regs_t; 119static_assert(sizeof(tk1_gpio_regs_t) == 256 * 8, "There are only 8 banks"); 120 121static inline tk1_gpio_regs_t *tk1_gpio_get_priv(gpio_sys_t *sys) 122{ 123 ZF_LOGF_IF(sys == NULL, "Invalid controller handle!"); 124 return (tk1_gpio_regs_t *)sys->priv; 125} 126 127static inline tk1_gpio_regs_t *tk1_gpio_pin_get_priv(gpio_t *pin) 128{ 129 ZF_LOGF_IF(pin == NULL, "Invalid pin handle!"); 130 return tk1_gpio_get_priv(pin->gpio_sys); 131} 132 133static inline tk1_gpio_bank_t *tk1_gpio_get_bank_by_pin(gpio_sys_t *sys, int pin) 134{ 135 return &tk1_gpio_get_priv(sys)->bank[GPIO_BANK(pin)]; 136} 137 138static inline volatile uint32_t *get_controller_register(gpio_sys_t *gpio_sys, 139 enum gpio_pin gpio_num, 140 enum tk1_gpio_bank_regs gpio_register) 141{ 142 ZF_LOGF_IF(gpio_register == GPIO_REG_INVALID, "Invalid register index!"); 143 ZF_LOGF_IF(gpio_register < 0 || gpio_register > GPIO_MSK_INT_LVL, 144 "Invalid register index!"); 145 146 return &tk1_gpio_get_bank_by_pin(gpio_sys, gpio_num)->regs[gpio_register] 147 .ports[GPIO_PORT(gpio_num)]; 148} 149 150/** For debugging. 151 * 152 * The lock bit determines whether or not it's possible to reconfigure the 153 * GPIO pins. This function does a scan and prints all those pins that have 154 * their lock bits set. 155 */ 156UNUSED static void tk1_gpio_debug_print_locks(gpio_sys_t *gs) 157{ 158 volatile uint32_t *v_cnf; 159 int total = 0; 160 161 for (int i = 0; i <= GPIO_PFF7; i++) { 162 v_cnf = get_controller_register(gs, i, GPIO_CNF); 163 164 if (*v_cnf & BIT(GPIO_BIT(i))) { 165 total++; 166 ZF_LOGD("GPIO: Pin %d has its lock set: CNF lock: regval %x.\n", 167 i, *v_cnf); 168 } 169 } 170 ZF_LOGD("GPIO: lock scan: %d pins have their locks set.\n", total); 171} 172 173static int gpio_set_direction(gpio_sys_t *gpio_sys, 174 enum gpio_pin gpio, enum gpio_dir mode) 175{ 176 uint32_t val, cnf_val; 177 volatile uint32_t *cnf_vaddr = get_controller_register(gpio_sys, 178 gpio, GPIO_CNF);; 179 volatile uint32_t *reg_vaddr = get_controller_register(gpio_sys, 180 gpio, GPIO_OE); 181 182 val = *reg_vaddr & REG_VALID_BITS_MASK; 183 cnf_val = *cnf_vaddr & CNFREG_VALID_BITS_MASK; 184 185 /* There are lock bits in the CNF register (TK1 SoC manual, sec 8.11.1). 186 * These lock bits enable and disable access to the CNF and OE registers. 187 * 188 * The CNF register has the bit that sets the pins to be either GPIO or 189 * SFIO mode. 190 * The OE register has the bit that sets the pins to be input or output 191 * mode. 192 * 193 * Unfortunately, if the lock bit is set therefore, we will be unable to 194 * actually change the configuration of the pin, because the lock bits can 195 * only be set up once during boot, and they are sticky after that: 196 * 197 * Section 8.11.1: 198 * "Lock bits are used to control the access to the CNF and OE registers. 199 * When set, no one can write to the CNF and OE bits. They can be 200 * programmed ONLY during Boot and get reset by chip reset only." 201 * 202 * So we must first test to see if the pin is already configured the way the 203 * user wants it. If it is, then we don't have to do anything. 204 * 205 * If the bit is NOT already configured to act the way the user is 206 * requesting, then we have to check the "lock" bit. If the lock bit is 207 * UNSET, then we can reconfigure the pin. 208 * 209 * If the "lock" bit is SET, then we cannot reconfigure the pin and we 210 * must return an error to the user. 211 */ 212 switch (mode) { 213 case GPIO_DIR_OUT_DEFAULT_HIGH: 214 case GPIO_DIR_OUT_DEFAULT_LOW: 215 if (val & BIT(GPIO_BIT(gpio))) { 216 /* If it's already how we want it, return success immediately. */ 217 return 0; 218 } 219 if (cnf_val & BIT(GPIO_BIT(gpio) + PORT_NBITS)) { 220 /* If it's not how the user wants it already, and the lock bit is 221 * set, then we can't fulfill the user's request: return error 222 * immediately. 223 */ 224 ZF_LOGW("Bit %d: Unable to setup as output pin. Pin is locked.", 225 gpio); 226 return -1; 227 } 228 229 val |= BIT(GPIO_BIT(gpio)); 230 break; 231 232 case GPIO_DIR_IN: 233 if ((val & BIT(GPIO_BIT(gpio))) == 0) { 234 return 0; 235 } 236 if (cnf_val & BIT(GPIO_BIT(gpio) + PORT_NBITS)) { 237 ZF_LOGW("Bit %d: Unable to setup as input pin. Pin is locked.", 238 gpio); 239 return -1; 240 } 241 242 val &= ~(BIT(GPIO_BIT(gpio))); 243 break; 244 245 default: 246 ZF_LOGF("gpio: %d, invalid mode %d.", gpio, mode); 247 } 248 249 *reg_vaddr = val; 250 assert(*reg_vaddr == val); 251 return 0; 252} 253 254static void gpio_set_interrupt_type(gpio_sys_t *gpio_sys, 255 enum gpio_pin gpio, enum gpio_dir dir) 256{ 257 uint32_t val, lvl_type = 0; 258 volatile uint32_t *reg_vaddr = get_controller_register(gpio_sys, 259 gpio, GPIO_INT_LVL); 260 261 val = *reg_vaddr & REG_VALID_BITS_MASK; 262 switch (dir) { 263 case GPIO_DIR_IRQ_RISE: 264 lvl_type = GPIO_INT_LVL_EDGE_RISING; 265 break; 266 case GPIO_DIR_IRQ_FALL: 267 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 268 break; 269 case GPIO_DIR_IRQ_EDGE: 270 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 271 break; 272 case GPIO_DIR_IRQ_HIGH: 273 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 274 break; 275 case GPIO_DIR_IRQ_LOW: 276 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 277 break; 278 default: 279 ZF_LOGF("GPIO: %d, invalid pin direction/interrupt %d", gpio, dir); 280 } 281 282 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 283 val |= lvl_type << GPIO_BIT(gpio); 284 *reg_vaddr = val; 285 assert(*reg_vaddr == val); 286} 287 288static void gpio_interrupt_enable(gpio_sys_t *gpio_sys, 289 enum gpio_pin gpio, bool enable) 290{ 291 uint32_t val; 292 volatile uint32_t *reg_vaddr = get_controller_register(gpio_sys, 293 gpio, GPIO_INT_ENB); 294 295 val = *reg_vaddr & REG_VALID_BITS_MASK; 296 if (enable) { 297 val |= BIT(GPIO_BIT(gpio)); 298 } else { 299 val &= ~(BIT(GPIO_BIT(gpio))); 300 } 301 *reg_vaddr = val; 302 assert(*reg_vaddr == val); 303} 304 305static int tegra_set_level(gpio_t *gpio, enum gpio_level level) 306{ 307 gpio_sys_t *gpio_sys = gpio->gpio_sys; 308 enum gpio_pin pin = gpio->id; 309 uint32_t val; 310 volatile uint32_t *reg_vaddr = get_controller_register(gpio_sys, 311 pin, GPIO_OUT); 312 313 ZF_LOGV("Offset: 0x%x (vaddr %x), controller offset: 0x%x, port offset: 0x%x, " 314 "GPIO_IN: 0x%x, gpio: %d, bank: %d, port: %d, gpio_bit: %d", 315 tegra_gpio_controller[GPIO_BANK(pin)] 316 + tegra_gpio_port[GPIO_PORT(pin)] 317 + GPIO_OUT, 318 reg_vaddr, 319 tegra_gpio_controller[GPIO_BANK(pin)], 320 tegra_gpio_port[GPIO_PORT(pin)], 321 GPIO_OUT, pin, GPIO_BANK(pin), GPIO_PORT(pin), GPIO_BIT(pin)); 322 323 val = *reg_vaddr & REG_VALID_BITS_MASK; 324 if (level == GPIO_LEVEL_HIGH) { 325 val |= BIT(GPIO_BIT(pin)); 326 } else { 327 val &= ~(BIT(GPIO_BIT(pin))); 328 } 329 330 *reg_vaddr = val; 331 assert(*reg_vaddr == val); 332 return 0; 333} 334 335static int tegra_read_level(gpio_t *gpio) 336{ 337 gpio_sys_t *gpio_sys = gpio->gpio_sys; 338 enum gpio_pin pin = gpio->id; 339 uint32_t val; 340 volatile uint32_t *reg_vaddr = get_controller_register(gpio_sys, 341 pin, GPIO_IN); 342 343 ZF_LOGV("Offset: 0x%x, controller offset: 0x%x, port offset: 0x%x, " 344 "GPIO_IN: 0x%x, gpio: %d, bank: %d, port: %d, gpio_bit: %d", 345 tegra_gpio_controller[GPIO_BANK(pin)] 346 + tegra_gpio_port[GPIO_PORT(pin)] 347 + GPIO_IN, 348 tegra_gpio_controller[GPIO_BANK(pin)], 349 tegra_gpio_port[GPIO_PORT(pin)], 350 GPIO_OUT, pin, GPIO_BANK(pin), GPIO_PORT(pin), GPIO_BIT(pin)); 351 352 353 val = *reg_vaddr & REG_VALID_BITS_MASK; 354 ZF_LOGV("GPIO %d bit value: 0x%x\n", pin, val); 355 if (!!(val & BIT(GPIO_BIT(pin)))) { 356 return GPIO_LEVEL_HIGH; 357 } 358 return GPIO_LEVEL_LOW; 359} 360 361static void gpio_int_clear(gpio_sys_t *gpio_sys, enum gpio_pin gpio) 362{ 363 uint32_t val; 364 volatile uint32_t *reg_vaddr = get_controller_register(gpio_sys, 365 gpio, GPIO_INT_CLR); 366 367 ZF_LOGV("offset: 0x%x, controller offset: 0x%x, port offset: 0x%x, " 368 "GPIO_IN: 0x%x, gpio: %d, bank: %d, port: %d, gpio_bit: %d", 369 tegra_gpio_controller[GPIO_BANK(gpio)] 370 + tegra_gpio_port[GPIO_PORT(gpio)] 371 + GPIO_INT_CLR, 372 tegra_gpio_controller[GPIO_BANK(gpio)], 373 tegra_gpio_port[GPIO_PORT(gpio)], 374 GPIO_OUT, gpio, GPIO_BANK(gpio), GPIO_PORT(gpio), GPIO_BIT(gpio)); 375 376 val = *reg_vaddr & REG_VALID_BITS_MASK; 377 val |= BIT(GPIO_BIT(gpio)); 378 *reg_vaddr = val; 379} 380 381static bool gpio_check_pending(gpio_sys_t *gpio_sys, enum gpio_pin gpio) 382{ 383 uint32_t val; 384 volatile uint32_t *reg_vaddr = get_controller_register(gpio_sys, 385 gpio, GPIO_INT_STA); 386 387 val = *reg_vaddr & REG_VALID_BITS_MASK; 388 return !!(val & BIT(GPIO_BIT(gpio))); 389} 390 391static int tegra_pending_status(gpio_t *gpio, bool clear) 392{ 393 int pending; 394 395 if (gpio == NULL) { 396 return -ENOSYS; 397 } 398 if (gpio->gpio_sys == NULL) { 399 return -ENOSYS; 400 } 401 402 pending = gpio_check_pending(gpio->gpio_sys, gpio->id); 403 404 if (clear) { 405 gpio_int_clear(gpio->gpio_sys, gpio->id); 406 } 407 408 return pending; 409} 410 411static int tegra_gpio_init(gpio_sys_t *gpio_sys, int id, enum gpio_dir dir, gpio_t *gpio) 412{ 413 int error; 414 415 ZF_LOGV("Configuring GPIO pin %d", id); 416 417 gpio->id = id; 418 gpio->gpio_sys = gpio_sys; 419 420 error = gpio_set_pad_mode(gpio_sys, id, GPIO_MODE, dir); 421 if (error != 0) { 422 return error; 423 } 424 425 if (dir == GPIO_DIR_IN 426 || dir == GPIO_DIR_OUT_DEFAULT_HIGH || dir == GPIO_DIR_OUT_DEFAULT_LOW) { 427 error = gpio_set_direction(gpio_sys, id, dir); 428 if (error != 0) { 429 return error; 430 } 431 } else { 432 gpio_set_interrupt_type(gpio_sys, id, dir); 433 } 434 435 /* Default to disabled IRQ state. The caller should have to call 436 * gpio_int_enable() explicitly to enable the IRQ signal for the pin, if the 437 * pin is configured to be an IRQ pin. 438 * 439 * The caller should also explicitly set the default output value if the pin 440 * is an input/output pin. 441 */ 442 gpio_interrupt_enable(gpio_sys, id, 0); 443 return 0; 444} 445 446static int tegra_gpio_int_enable_disable(gpio_t *gpio, bool enable) 447{ 448 gpio_interrupt_enable(gpio->gpio_sys, gpio->id, enable); 449 return 0; 450} 451 452int gpio_init(volatile void *vaddr, gpio_sys_t *gpio_sys) 453{ 454 if (gpio_sys == NULL) { 455 return -ENOSYS; 456 } 457 if (vaddr == NULL) { 458 return -ENOSYS; 459 } 460 461 ZF_LOGV("vaddr: %p", vaddr); 462 463 gpio_sys->set_level = &tegra_set_level; 464 gpio_sys->read_level = &tegra_read_level; 465 gpio_sys->pending_status = &tegra_pending_status; 466 gpio_sys->irq_enable_disable = &tegra_gpio_int_enable_disable; 467 gpio_sys->init = &tegra_gpio_init; 468 469 gpio_sys->priv = (void *)vaddr; 470 return 0; 471} 472 473int gpio_sys_init(ps_io_ops_t *io_ops, gpio_sys_t *gpio_sys) 474{ 475 if (io_ops == NULL) { 476 return -ENOSYS; 477 } 478 if (gpio_sys == NULL) { 479 return -ENOSYS; 480 } 481 482 MAP_IF_NULL(io_ops, TK1_GPIO, gpio_sys->priv); 483 if (gpio_sys->priv == NULL) { 484 ZF_LOGE("Failed to map TK1 GPIO frame."); 485 return -1; 486 } 487 488 return gpio_init(gpio_sys->priv, gpio_sys); 489} 490 491int gpio_set_pad_mode(gpio_sys_t *gpio_sys, 492 enum gpio_pin gpio, enum gpio_pad_mode mode, enum gpio_dir dir) 493{ 494 uint32_t val, out_val; 495 volatile uint32_t *reg_vaddr = get_controller_register(gpio_sys, 496 gpio, GPIO_CNF); 497 volatile uint32_t *out_reg_vaddr = get_controller_register(gpio_sys, 498 gpio, GPIO_OUT); 499 500 ZF_LOGV("Offset: 0x%x, controller offset: 0x%x, port offset: 0x%x, " 501 "GPIO_CNF: 0x%x, gpio: %d, bank: %d, port: %d, gpio_bit: %d" 502 "Mode %d.\n", 503 tegra_gpio_controller[GPIO_BANK(gpio)] 504 + tegra_gpio_port[GPIO_PORT(gpio)] 505 + GPIO_CNF, 506 tegra_gpio_controller[GPIO_BANK(gpio)], 507 tegra_gpio_port[GPIO_PORT(gpio)], 508 GPIO_CNF, gpio, GPIO_BANK(gpio), GPIO_PORT(gpio), GPIO_BIT(gpio), 509 mode); 510 511 /* See the comment in gpio_set_direction() above: ability to change the 512 * mode of a pin from SFIO to GPIO mode requires us to change bits in the 513 * CNF register. But the CNF register is locked off if the "lock" bit is 514 * set. 515 * 516 * So we must first test the lock bit to know if we can fulfill the user's 517 * request at all. If we can't, we return early with an error. 518 */ 519 520 val = *reg_vaddr & CNFREG_VALID_BITS_MASK; 521 switch (mode) { 522 case GPIO_MODE: 523 /* We need to support a transition to GPIO mode while ensuring that 524 * the initialization preserves a certain output value (DEFAULT_HIGH vs 525 * DEFAULT_LOW). 526 */ 527 out_val = *out_reg_vaddr & REG_VALID_BITS_MASK; 528 switch (dir) { 529 case GPIO_DIR_OUT_DEFAULT_HIGH: 530 out_val |= BIT(GPIO_BIT(gpio)); 531 break; 532 case GPIO_DIR_OUT_DEFAULT_LOW: 533 out_val &= ~(BIT(GPIO_BIT(gpio))); 534 break; 535 default: 536 break; 537 } 538 *out_reg_vaddr = out_val; 539 540 if (val & BIT(GPIO_BIT(gpio))) { 541 /* If it's already setup the way the user requested, just return 542 * success early. 543 */ 544 return 0; 545 } 546 if (val & BIT(GPIO_BIT(gpio) + PORT_NBITS)) { 547 /* If it's not setup the way the user wants, but the lock bit is 548 * also set, then we cannot reconfigure the pin. Return error. 549 */ 550 ZF_LOGW("Pin %d: Failed to set to GPIO mode. Pin is locked.", gpio); 551 return -1; 552 } 553 554 val |= BIT(GPIO_BIT(gpio)); 555 break; 556 557 case SFIO_MODE: 558 if ((val & BIT(GPIO_BIT(gpio))) == 0) { 559 return 0; 560 } 561 if (val & BIT(GPIO_BIT(gpio) + PORT_NBITS)) { 562 ZF_LOGW("Pin %d: Failed to set to GPIO mode. Pin is locked.", gpio); 563 return -1; 564 } 565 566 val &= ~(BIT(GPIO_BIT(gpio))); 567 break; 568 569 default: 570 ZF_LOGF("GPIO: pin %d, invalid mode %d", gpio, mode); 571 } 572 573 ZF_LOGV("Reg value: 0x%x", val); 574 *reg_vaddr = val; 575 576 assert(*reg_vaddr == val); 577 return 0; 578} 579