1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12#include <stdint.h> 13#include <stdio.h> 14#include <platsupport/io.h> 15 16#define INTCTL0 0x12100000 17#define INTCTL1 0x12100800 18#define INTCTL2 0x12101000 19#define INTCTL3 0x12101800 20#define INTCTL4 0x12102000 21#define INTCTL5 0x12102800 22#define INTCTL6 0x12103000 23#define INTCTL7 0x12103800 24 25struct intctl { 26#define INTSELECT_IRQ 0x0 27#define INTSELECT_FIQ 0x1 28 uint32_t select[2]; /* +0x000 */ 29 uint32_t res0[2]; 30#define INTENABLE_ENABLE 0x1 31#define INTENABLE_DISABLE 0x0 32 uint32_t enable[2]; /* +0x010 */ 33 uint32_t res1[2]; 34 uint32_t enable_clear[2]; /* +0x020 */ 35 uint32_t res2[2]; 36 uint32_t enable_set[2]; /* +0x030 */ 37 uint32_t res3[2]; 38#define INTTYPE_EDGE 0x1 39#define INTTYPE_LEVEL 0x0 40 uint32_t type[2]; /* +0x040 */ 41 uint32_t res4[2]; 42#define INTPOL_NEG 0x1 43#define INTPOL_POS 0x0 44 uint32_t polariy[2]; /* +0x050 */ 45 uint32_t res5[2]; 46 uint32_t no_pend_val; /* +0x060 */ 47#define INTMASTER_IRQEN (BIT(0)) 48#define INTMASTER_FIQEN (BIT(1)) 49 uint32_t master_enable; /* +0x064 */ 50#define INTVIC_VECTOR_MODE 0x1 51 uint32_t vic_config; /* +0x068 */ 52#define INTSECURE 0x1 53 uint32_t security; /* +0x06C */ 54 uint32_t res6[4]; 55 uint32_t irq_status[2]; /* +0x080 */ 56 uint32_t res7[2]; 57 uint32_t fiq_status[2]; /* +0x090 */ 58 uint32_t res8[2]; 59 uint32_t raw_status[2]; /* +0x0A0 */ 60 uint32_t res9[2]; 61 uint32_t raw_clear[2]; /* +0x0B0 */ 62 uint32_t res10[2]; 63 uint32_t raw_soft_int[2]; /* +0x0C0 */ 64 uint32_t res11[2]; 65 uint32_t vec_rd; /* +0x0D0 */ 66 uint32_t pend_rd; /* +0x0D4 */ 67 uint32_t vec_wr; /* +0x0D8 */ 68 uint32_t res12; 69 uint32_t in_service; /* +0x0E0 */ 70 uint32_t in_stack; /* +0x0E4 */ 71 uint32_t test_bus_sel; /* +0x0E8 */ 72 uint32_t ctl_config; /* +0x0EC */ 73 uint32_t res13[4]; 74 uint32_t res14[64]; 75 uint32_t priority[64]; /* +0x200 */ 76 uint32_t res15[64]; 77 uint32_t vec_addr[64]; /* +0x400 */ 78 uint32_t res16[64]; 79}; 80typedef volatile struct intctl intctl_t; 81 82#define PPSS_INTC 0x12080000 83#define PPSSINTC_IRQ_OFFSET 0x000 84#define PPSSINTC_FIQ_OFFSET 0x100 85struct ppss_intc { 86 uint32_t stat; /* +0x00 */ 87 uint32_t rawstat; /* +0x04 */ 88 uint32_t seten; /* +0x08 */ 89 uint32_t clren; /* +0x0C */ 90 uint32_t soft; /* +0x10 */ 91}; 92typedef volatile struct ppss_intc ppss_intc_t; 93 94intctl_t* intctl[8]; 95ppss_intc_t* fiq; 96ppss_intc_t* irq; 97 98void 99test_intc(ps_io_ops_t* o) 100{ 101 void* vaddr[4]; 102 if (intctl[0] == NULL) { 103 /* intc */ 104 vaddr[0] = ps_io_map(&o->io_mapper, INTCTL0, 0x1000, 0, PS_MEM_NORMAL); 105 vaddr[1] = ps_io_map(&o->io_mapper, INTCTL2, 0x1000, 0, PS_MEM_NORMAL); 106 vaddr[2] = ps_io_map(&o->io_mapper, INTCTL3, 0x1000, 0, PS_MEM_NORMAL); 107 vaddr[3] = ps_io_map(&o->io_mapper, INTCTL4, 0x1000, 0, PS_MEM_NORMAL); 108 assert(vaddr[0]); 109 assert(vaddr[1]); 110 assert(vaddr[2]); 111 assert(vaddr[3]); 112 intctl[0] = (intctl_t*)((uintptr_t)vaddr[0] + 0x000); 113 intctl[1] = (intctl_t*)((uintptr_t)vaddr[0] + 0x800); 114 intctl[2] = (intctl_t*)((uintptr_t)vaddr[1] + 0x000); 115 intctl[3] = (intctl_t*)((uintptr_t)vaddr[1] + 0x800); 116 intctl[4] = (intctl_t*)((uintptr_t)vaddr[2] + 0x000); 117 intctl[5] = (intctl_t*)((uintptr_t)vaddr[2] + 0x800); 118 intctl[6] = (intctl_t*)((uintptr_t)vaddr[3] + 0x000); 119 intctl[7] = (intctl_t*)((uintptr_t)vaddr[3] + 0x800); 120 /* ppss intc */ 121 vaddr[0] = ps_io_map(&o->io_mapper, PPSS_INTC, 0x1000, 0, PS_MEM_NORMAL); 122 irq = (ppss_intc_t*)((uintptr_t)vaddr[0] + PPSSINTC_IRQ_OFFSET); 123 fiq = (ppss_intc_t*)((uintptr_t)vaddr[0] + PPSSINTC_FIQ_OFFSET); 124 printf("irq: 0x%x 0x%x 0x%x 0x%x 0x%x\n", irq->stat, irq->rawstat, irq->seten, irq->clren, irq->soft); 125 printf("fiq: 0x%x 0x%x 0x%x 0x%x 0x%x\n", fiq->stat, fiq->rawstat, fiq->seten, fiq->clren, fiq->soft); 126 irq->soft = 1; 127 irq->seten = 0xffff; 128 printf("irq: 0x%x 0x%x 0x%x 0x%x 0x%x\n", irq->stat, irq->rawstat, irq->seten, irq->clren, irq->soft); 129 } 130}; 131