1/* 2 * (C) Copyright 2008 3 * Benjamin Warren, biggerbadderben@gmail.com 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * netdev.h - definitions an prototypes for network devices 10 */ 11 12#ifndef _NETDEV_H_ 13#define _NETDEV_H_ 14 15#include <platsupport/io.h> 16#include "net.h" 17 18/* 19 * Board and CPU-specific initialization functions 20 * board_eth_init() has highest priority. cpu_eth_init() only 21 * gets called if board_eth_init() isn't instantiated or fails. 22 * Return values: 23 * 0: success 24 * -1: failure 25 */ 26 27int board_eth_init(void); 28int cpu_eth_init(void); 29 30/* Driver initialization prototypes */ 31int at91emac_register(bd_t *bis, unsigned long iobase); 32int au1x00_enet_initialize(bd_t*); 33int ax88180_initialize(bd_t *bis); 34int bcm_sf2_eth_register(bd_t *bis, u8 dev_num); 35int bfin_EMAC_initialize(bd_t *bis); 36int calxedaxgmac_initialize(u32 id, ulong base_addr); 37int cs8900_initialize(u8 dev_num, int base_addr); 38int davinci_emac_initialize(void); 39int dc21x4x_initialize(bd_t *bis); 40int designware_initialize(ulong base_addr, u32 interface); 41int dm9000_initialize(bd_t *bis); 42int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); 43int e1000_initialize(bd_t *bis); 44int eepro100_initialize(bd_t *bis); 45int enc28j60_initialize(unsigned int bus, unsigned int cs, 46 unsigned int max_hz, unsigned int mode); 47int ep93xx_eth_initialize(u8 dev_num, int base_addr); 48int eth_3com_initialize (bd_t * bis); 49int ethoc_initialize(u8 dev_num, int base_addr); 50int fec_initialize (bd_t *bis); 51int fecmxc_initialize(bd_t *bis); 52int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr); 53int ftgmac100_initialize(bd_t *bits); 54int ftmac100_initialize(bd_t *bits); 55int ftmac110_initialize(bd_t *bits); 56int greth_initialize(bd_t *bis); 57void gt6426x_eth_initialize(bd_t *bis); 58int ks8851_mll_initialize(u8 dev_num, int base_addr); 59int lan91c96_initialize(u8 dev_num, int base_addr); 60int lpc32xx_eth_initialize(bd_t *bis); 61int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); 62int mcdmafec_initialize(bd_t *bis); 63int mcffec_initialize(bd_t *bis); 64int mpc512x_fec_initialize(bd_t *bis); 65int mpc5xxx_fec_initialize(bd_t *bis); 66int mpc82xx_scc_enet_initialize(bd_t *bis); 67int mvgbe_initialize(bd_t *bis); 68int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr); 69int natsemi_initialize(bd_t *bis); 70int ne2k_register(void); 71int npe_initialize(bd_t *bis); 72int ns8382x_initialize(bd_t *bis); 73int pcnet_initialize(bd_t *bis); 74int ppc_4xx_eth_initialize (bd_t *bis); 75int rtl8139_initialize(bd_t *bis); 76int rtl8169_initialize(bd_t *bis); 77int scc_initialize(bd_t *bis); 78int sh_eth_initialize(bd_t *bis); 79int skge_initialize(bd_t *bis); 80int smc91111_initialize(u8 dev_num, int base_addr); 81int smc911x_initialize(u8 dev_num, int base_addr); 82int tsi108_eth_initialize(bd_t *bis); 83int uec_standard_init(bd_t *bis); 84int uli526x_initialize(bd_t *bis); 85int armada100_fec_register(unsigned long base_addr); 86int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, 87 unsigned long dma_addr); 88int xilinx_emaclite_of_init(const void *blob); 89int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, 90 int txpp, int rxpp); 91int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, 92 unsigned long ctrl_addr); 93int zynq_gem_of_init(const void *blob); 94int zynq_gem_initialize(phys_addr_t base_addr, 95 int phy_addr, u32 emio); 96void zynq_set_gem_ioops(ps_io_ops_t *io_ops); 97void zynq_gem_handle_irq(int irq); 98void zynq_set_gem_iobase(unsigned int base_addr); 99 100/* 101 * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface 102 * exported by a public hader file, we need a global definition at this point. 103 */ 104#if defined(CONFIG_XILINX_LL_TEMAC) 105#define XILINX_LL_TEMAC_M_FIFO 0 /* use FIFO Ctrl */ 106#define XILINX_LL_TEMAC_M_SDMA_PLB (1 << 0)/* use SDMA Ctrl via PLB */ 107#define XILINX_LL_TEMAC_M_SDMA_DCR (1 << 1)/* use SDMA Ctrl via DCR */ 108#endif 109 110/* Boards with PCI network controllers can call this from their board_eth_init() 111 * function to initialize whatever's on board. 112 * Return value is total # of devices found */ 113 114static inline int pci_eth_init(bd_t *bis) 115{ 116 int num = 0; 117 118#ifdef CONFIG_PCI 119 120#ifdef CONFIG_EEPRO100 121 num += eepro100_initialize(bis); 122#endif 123#ifdef CONFIG_TULIP 124 num += dc21x4x_initialize(bis); 125#endif 126#ifdef CONFIG_E1000 127 num += e1000_initialize(bis); 128#endif 129#ifdef CONFIG_PCNET 130 num += pcnet_initialize(bis); 131#endif 132#ifdef CONFIG_NATSEMI 133 num += natsemi_initialize(bis); 134#endif 135#ifdef CONFIG_NS8382X 136 num += ns8382x_initialize(bis); 137#endif 138#if defined(CONFIG_RTL8139) 139 num += rtl8139_initialize(bis); 140#endif 141#if defined(CONFIG_RTL8169) 142 num += rtl8169_initialize(bis); 143#endif 144#if defined(CONFIG_ULI526X) 145 num += uli526x_initialize(bis); 146#endif 147 148#endif /* CONFIG_PCI */ 149 return num; 150} 151 152/* 153 * Boards with mv88e61xx switch can use this by defining 154 * CONFIG_MV88E61XX_SWITCH in respective board configheader file 155 * the stuct and enums here are used to specify switch configuration params 156 */ 157#if defined(CONFIG_MV88E61XX_SWITCH) 158 159/* constants for any 88E61xx switch */ 160#define MV88E61XX_MAX_PORTS_NUM 6 161 162enum mv88e61xx_cfg_mdip { 163 MV88E61XX_MDIP_NOCHANGE, 164 MV88E61XX_MDIP_REVERSE 165}; 166 167enum mv88e61xx_cfg_ledinit { 168 MV88E61XX_LED_INIT_DIS, 169 MV88E61XX_LED_INIT_EN 170}; 171 172enum mv88e61xx_cfg_rgmiid { 173 MV88E61XX_RGMII_DELAY_DIS, 174 MV88E61XX_RGMII_DELAY_EN 175}; 176 177enum mv88e61xx_cfg_prtstt { 178 MV88E61XX_PORTSTT_DISABLED, 179 MV88E61XX_PORTSTT_BLOCKING, 180 MV88E61XX_PORTSTT_LEARNING, 181 MV88E61XX_PORTSTT_FORWARDING 182}; 183 184struct mv88e61xx_config { 185 char *name; 186 u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; 187 enum mv88e61xx_cfg_rgmiid rgmii_delay; 188 enum mv88e61xx_cfg_prtstt portstate; 189 enum mv88e61xx_cfg_ledinit led_init; 190 enum mv88e61xx_cfg_mdip mdip; 191 u32 ports_enabled; 192 u8 cpuport; 193}; 194 195/* 196 * Common mappings for Internal VLANs 197 * These mappings consider that all ports are useable; the driver 198 * will mask inexistent/unused ports. 199 */ 200 201/* Switch mode : routes any port to any port */ 202#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } 203 204/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ 205#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } 206 207int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); 208#endif /* CONFIG_MV88E61XX_SWITCH */ 209 210struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id); 211#ifdef CONFIG_PHYLIB 212struct phy_device; 213int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, 214 struct mii_dev *bus, struct phy_device *phydev); 215#else 216/* 217 * Allow FEC to fine-tune MII configuration on boards which require this. 218 */ 219int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); 220#endif 221 222#endif /* _NETDEV_H_ */ 223