1/* 2 * @TAG(OTHER_GPL) 3 */ 4// SPDX-License-Identifier: GPL-2.0 5/* 6 * Copyright (c) 2016, NVIDIA CORPORATION. 7 * 8 * Portions based on U-Boot's rtl8169.c. 9 */ 10 11/* 12 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of 13 * Service) IP block. The IP supports multiple options for bus type, clocking/ 14 * reset structure, and feature list. 15 * 16 * The driver is written such that generic core logic is kept separate from 17 * configuration-specific logic. Code that interacts with configuration- 18 * specific resources is split out into separate functions to avoid polluting 19 * common code. If/when this driver is enhanced to support multiple 20 * configurations, the core code should be adapted to call all configuration- 21 * specific functions through function pointers, with the definition of those 22 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data 23 * field. 24 * 25 * The following configurations are currently supported: 26 * tegra186: 27 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an 28 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and 29 * supports a single RGMII PHY. This configuration also has SW control over 30 * all clock and reset signals to the HW block. 31 */ 32 33#include "miiphy.h" 34#include "net.h" 35#include "phy.h" 36 37#include "wait_bit.h" 38 39#include <platsupport/clock.h> 40#include <platsupport/io.h> 41#include <platsupportports/plat/gpio.h> 42#include <platsupport/gpio.h> 43#include <platsupport/reset.h> 44 45#include "../tx2.h" 46#include "tx2_configs.h" 47 48#include <string.h> 49#include <ethdrivers/helpers.h> 50#define EQOS_MAC_REGS_BASE 0x000 51struct eqos_mac_regs { 52 uint32_t configuration; /* 0x000 */ 53 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */ 54 uint32_t q0_tx_flow_ctrl; /* 0x070 */ 55 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ 56 uint32_t rx_flow_ctrl; /* 0x090 */ 57 uint32_t unused_094; /* 0x094 */ 58 uint32_t txq_prty_map0; /* 0x098 */ 59 uint32_t unused_09c; /* 0x09c */ 60 uint32_t rxq_ctrl0; /* 0x0a0 */ 61 uint32_t rxq_ctrl1; /* 0x0a4 */ 62 uint32_t rxq_ctrl2; /* 0x0a8 */ 63 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ 64 uint32_t us_tic_counter; /* 0x0dc */ 65 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ 66 uint32_t hw_feature0; /* 0x11c */ 67 uint32_t hw_feature1; /* 0x120 */ 68 uint32_t hw_feature2; /* 0x124 */ 69 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */ 70 uint32_t mdio_address; /* 0x200 */ 71 uint32_t mdio_data; /* 0x204 */ 72 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */ 73 uint32_t address0_high; /* 0x300 */ 74 uint32_t address0_low; /* 0x304 */ 75}; 76 77#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23) 78#define EQOS_MAC_CONFIGURATION_CST BIT(21) 79#define EQOS_MAC_CONFIGURATION_ACS BIT(20) 80#define EQOS_MAC_CONFIGURATION_WD BIT(19) 81#define EQOS_MAC_CONFIGURATION_JD BIT(17) 82#define EQOS_MAC_CONFIGURATION_JE BIT(16) 83#define EQOS_MAC_CONFIGURATION_PS BIT(15) 84#define EQOS_MAC_CONFIGURATION_FES BIT(14) 85#define EQOS_MAC_CONFIGURATION_DM BIT(13) 86#define EQOS_MAC_CONFIGURATION_TE BIT(1) 87#define EQOS_MAC_CONFIGURATION_RE BIT(0) 88 89#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 90#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff 91#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) 92 93#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0) 94 95#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0 96#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff 97 98#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 99#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3 100#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 101#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 102#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 103 104#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 105#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff 106 107#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 108#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f 109#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 110#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f 111 112#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 113#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 114#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 115#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 116#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 117#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) 118#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2 119#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 120#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 121#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) 122#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) 123 124#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff 125 126#define EQOS_MTL_REGS_BASE 0xd00 127struct eqos_mtl_regs { 128 uint32_t txq0_operation_mode; /* 0xd00 */ 129 uint32_t unused_d04; /* 0xd04 */ 130 uint32_t txq0_debug; /* 0xd08 */ 131 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */ 132 uint32_t txq0_quantum_weight; /* 0xd18 */ 133 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */ 134 uint32_t rxq0_operation_mode; /* 0xd30 */ 135 uint32_t unused_d34; /* 0xd34 */ 136 uint32_t rxq0_debug; /* 0xd38 */ 137}; 138 139#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 140#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff 141#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 142#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3 143#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 144#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) 145#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) 146 147#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20 148#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff 149#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14 150#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f 151#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8 152#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f 153#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) 154#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) 155 156#define EQOS_DMA_REGS_BASE 0x1000 157struct eqos_dma_regs { 158 uint32_t mode; /* 0x1000 */ 159 uint32_t sysbus_mode; /* 0x1004 */ 160 uint32_t dma_control[(0x1100 - 0x1008) / 4]; /* 0x1008 */ 161 uint32_t ch0_control; /* 0x1100 */ 162 uint32_t ch0_tx_control; /* 0x1104 */ 163 uint32_t ch0_rx_control; /* 0x1108 */ 164 uint32_t unused_110c; /* 0x110c */ 165 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */ 166 uint32_t ch0_txdesc_list_address; /* 0x1114 */ 167 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */ 168 uint32_t ch0_rxdesc_list_address; /* 0x111c */ 169 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */ 170 uint32_t unused_1124; /* 0x1124 */ 171 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */ 172 uint32_t ch0_txdesc_ring_length; /* 0x112c */ 173 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */ 174 uint32_t ch0_dma_ie; /* 0x1134 */ 175 uint32_t ch0_dma_rx_int_wd_timer; /* 0x1138 */ 176}; 177 178#define EQOS_DMA_MODE_SWR BIT(0) 179 180#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 181#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf 182#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11) 183#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3) 184#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2) 185#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1) 186 187#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16) 188 189#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 190#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f 191#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4) 192#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0) 193 194#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 195#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f 196#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1 197#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff 198#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0) 199#define DWCEQOS_DMA_CH_CTRL_START BIT(0) 200/* These registers are Tegra186-specific */ 201#define EQOS_TEGRA186_REGS_BASE 0x8800 202struct eqos_tegra186_regs { 203 uint32_t sdmemcomppadctrl; /* 0x8800 */ 204 uint32_t auto_cal_config; /* 0x8804 */ 205 uint32_t unused_8808; /* 0x8808 */ 206 uint32_t auto_cal_status; /* 0x880c */ 207}; 208 209#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31) 210 211#define EQOS_AUTO_CAL_CONFIG_START BIT(31) 212#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29) 213#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31) 214 215#define EQOS_DESCRIPTOR_WORDS 4 216#define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4) 217/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */ 218#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN 219#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX) 220#define EQOS_DESCRIPTORS_SIZE EQOS_ALIGN(EQOS_DESCRIPTORS_NUM * \ 221 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN) 222#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN 223 224//from linux 225// #define EQOS_RX_BUFFER_SIZE 2048 226#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE) 227 228struct eqos_config { 229 bool reg_access_always_ok; 230 int mdio_wait; 231 int swr_wait; 232 int config_mac; 233 int config_mac_mdio; 234}; 235 236/* ARP hardware address length */ 237#define ARP_HLEN 6 238 239struct eqos_priv { 240 const struct eqos_config *config; 241 uintptr_t regs; 242 struct eqos_mac_regs *mac_regs; 243 struct eqos_mtl_regs *mtl_regs; 244 struct eqos_dma_regs *dma_regs; 245 struct eqos_tegra186_regs *tegra186_regs; 246 struct clock *clk_master_bus; 247 struct clock *clk_rx; 248 struct clock *clk_ptp_ref; 249 struct clock *clk_tx; 250 struct clock *clk_slave_bus; 251 struct mii_dev *mii; 252 struct phy_device *phy; 253 uintptr_t last_rx_desc; 254 uintptr_t last_tx_desc; 255 unsigned char enetaddr[ARP_HLEN]; 256 bool reg_access_ok; 257 ps_io_ops_t *tx2_io_ops; 258 gpio_sys_t *gpio_sys; 259 gpio_t gpio; 260 reset_sys_t *reset_sys; 261 clock_sys_t *clock_sys; 262}; 263 264#define REG_DWCEQOS_ETH_MMC_CONTROL 0x0700 265#define REG_DWCEQOS_MMC_CNTFREEZ BIT(3) 266 267#define REG_DWCEQOS_DMA_CH0_STA 0x1160 268#define DWCEQOS_DMA_IS_DC0IS BIT(0) 269#define DWCEQOS_DMA_IS_MTLIS BIT(16) 270#define DWCEQOS_DDWCEQOSMA_IS_MACIS BIT(17) 271#define DWCEQOS_DMA_CH0_IS_TI BIT(0) 272#define DWCEQOS_DMA_CH0_IS_RI BIT(6) 273#define DWCEQOS_MAC_IS_MMC_INT BIT(8) 274#define DWCEQOS_MAC_IS_LPI_INT BIT(5) 275 276#define DWCEQOS_DMA_CH0_IE_NIE BIT(15) 277#define DWCEQOS_DMA_CH0_IE_AIE BIT(14) 278#define DWCEQOS_DMA_CH0_IE_RIE BIT(6) 279#define DWCEQOS_DMA_CH0_IE_TIE BIT(0) 280#define DWCEQOS_DMA_CH0_IE_FBEE BIT(12) 281#define DWCEQOS_DMA_CH0_IE_RBUE BIT(7) 282#define DWCEQOS_DMA_CH0_IE_RWTE BIT(9) 283 284#define MAC_LPS_RES_WR_MASK_20 (uint32_t)(0xfffff) 285#define MAC_LPS_MASK_20 (uint32_t)(0xfff) 286#define MAC_LPS_MASK_10 (uint32_t)(0x3f) 287#define MAC_LPS_RES_WR_MASK_10 (uint32_t)(0xffff03ff) 288#define MAC_LPS_MASK_4 (uint32_t)(0xf) 289#define MAC_LPS_RES_WR_MASK_4 (uint32_t)(0xffffff0f) 290#define MAC_LPS_PLSEN_MASK (uint32_t)(0x1) 291#define MAC_LPS_PLSEN_WR_MASK (uint32_t)(0xfffbffff) 292 293#define DWCEQOS_MAC_CFG_ACS BIT(20) 294#define DWCEQOS_MAC_CFG_JD BIT(17) 295#define DWCEQOS_MAC_CFG_JE BIT(16) 296#define DWCEQOS_MAC_CFG_PS BIT(15) 297#define DWCEQOS_MAC_CFG_FES BIT(14) 298/* full duplex mode? */ 299#define DWCEQOS_MAC_CFG_DM BIT(13) 300#define DWCEQOS_MAC_CFG_DO BIT(10) 301#define DWCEQOS_MAC_CFG_TE BIT(1) 302/* Check sum bit */ 303#define DWCEQOS_MAC_CFG_IPC BIT(27) 304#define DWCEQOS_MAC_CFG_RE BIT(0) 305