1/* 2 * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7/* CPU model specific register (MSR) numbers. 8 * Authors: 9 * Qian Ge 10 */ 11 12#pragma once 13 14/* Intel MSRs. Some also available on other CPUs */ 15 16#define MSR_IA32_PERFCTR0 0x000000c1 17#define MSR_IA32_PERFCTR1 0x000000c2 18#define MSR_FSB_FREQ 0x000000cd 19#define MSR_NHM_PLATFORM_INFO 0x000000ce 20 21#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 22#define NHM_C3_AUTO_DEMOTE (1UL << 25) 23#define NHM_C1_AUTO_DEMOTE (1UL << 26) 24#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 25#define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 26#define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 27 28#define MSR_MTRRcap 0x000000fe 29#define MSR_IA32_BBL_CR_CTL 0x00000119 30#define MSR_IA32_BBL_CR_CTL3 0x0000011e 31 32#define MSR_IA32_SYSENTER_CS 0x00000174 33#define MSR_IA32_SYSENTER_ESP 0x00000175 34#define MSR_IA32_SYSENTER_EIP 0x00000176 35 36#define MSR_IA32_MCG_CAP 0x00000179 37#define MSR_IA32_MCG_STATUS 0x0000017a 38#define MSR_IA32_MCG_CTL 0x0000017b 39 40#define MSR_OFFCORE_RSP_0 0x000001a6 41#define MSR_OFFCORE_RSP_1 0x000001a7 42#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 43#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 44 45#define MSR_LBR_SELECT 0x000001c8 46#define MSR_LBR_TOS 0x000001c9 47#define MSR_LBR_NHM_FROM 0x00000680 48#define MSR_LBR_NHM_TO 0x000006c0 49#define MSR_LBR_CORE_FROM 0x00000040 50#define MSR_LBR_CORE_TO 0x00000060 51 52#define MSR_IA32_PEBS_ENABLE 0x000003f1 53#define MSR_IA32_DS_AREA 0x00000600 54#define MSR_IA32_PERF_CAPABILITIES 0x00000345 55 56#define MSR_MTRRfix64K_00000 0x00000250 57#define MSR_MTRRfix16K_80000 0x00000258 58#define MSR_MTRRfix16K_A0000 0x00000259 59#define MSR_MTRRfix4K_C0000 0x00000268 60#define MSR_MTRRfix4K_C8000 0x00000269 61#define MSR_MTRRfix4K_D0000 0x0000026a 62#define MSR_MTRRfix4K_D8000 0x0000026b 63#define MSR_MTRRfix4K_E0000 0x0000026c 64#define MSR_MTRRfix4K_E8000 0x0000026d 65#define MSR_MTRRfix4K_F0000 0x0000026e 66#define MSR_MTRRfix4K_F8000 0x0000026f 67#define MSR_MTRRdefType 0x000002ff 68 69#define MSR_IA32_CR_PAT 0x00000277 70 71#define MSR_IA32_DEBUGCTLMSR 0x000001d9 72#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 73#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 74#define MSR_IA32_LASTINTFROMIP 0x000001dd 75#define MSR_IA32_LASTINTTOIP 0x000001de 76 77/* DEBUGCTLMSR bits (others vary by model): */ 78#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 79#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 80#define DEBUGCTLMSR_TR (1UL << 6) 81#define DEBUGCTLMSR_BTS (1UL << 7) 82#define DEBUGCTLMSR_BTINT (1UL << 8) 83#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 84#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 85#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 86 87#define MSR_IA32_MC0_CTL 0x00000400 88#define MSR_IA32_MC0_STATUS 0x00000401 89#define MSR_IA32_MC0_ADDR 0x00000402 90#define MSR_IA32_MC0_MISC 0x00000403 91 92/* C-state Residency Counters */ 93#define MSR_PKG_C3_RESIDENCY 0x000003f8 94#define MSR_PKG_C6_RESIDENCY 0x000003f9 95#define MSR_PKG_C7_RESIDENCY 0x000003fa 96#define MSR_CORE_C3_RESIDENCY 0x000003fc 97#define MSR_CORE_C6_RESIDENCY 0x000003fd 98#define MSR_CORE_C7_RESIDENCY 0x000003fe 99#define MSR_PKG_C2_RESIDENCY 0x0000060d 100 101/* Run Time Average Power Limiting (RAPL) Interface */ 102 103#define MSR_RAPL_POWER_UNIT 0x00000606 104 105#define MSR_PKG_POWER_LIMIT 0x00000610 106#define MSR_PKG_ENERGY_STATUS 0x00000611 107#define MSR_PKG_PERF_STATUS 0x00000613 108#define MSR_PKG_POWER_INFO 0x00000614 109 110#define MSR_DRAM_POWER_LIMIT 0x00000618 111#define MSR_DRAM_ENERGY_STATUS 0x00000619 112#define MSR_DRAM_PERF_STATUS 0x0000061b 113#define MSR_DRAM_POWER_INFO 0x0000061c 114 115#define MSR_PP0_POWER_LIMIT 0x00000638 116#define MSR_PP0_ENERGY_STATUS 0x00000639 117#define MSR_PP0_POLICY 0x0000063a 118#define MSR_PP0_PERF_STATUS 0x0000063b 119 120#define MSR_PP1_POWER_LIMIT 0x00000640 121#define MSR_PP1_ENERGY_STATUS 0x00000641 122#define MSR_PP1_POLICY 0x00000642 123 124#define MSR_AMD64_MC0_MASK 0xc0010044 125 126#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 127#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 128#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 129#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 130 131#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 132 133/* These are consecutive and not in the normal 4er MCE bank block */ 134#define MSR_IA32_MC0_CTL2 0x00000280 135#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 136 137#define MSR_P6_PERFCTR0 0x000000c1 138#define MSR_P6_PERFCTR1 0x000000c2 139#define MSR_P6_EVNTSEL0 0x00000186 140#define MSR_P6_EVNTSEL1 0x00000187 141 142#define MSR_KNC_PERFCTR0 0x00000020 143#define MSR_KNC_PERFCTR1 0x00000021 144#define MSR_KNC_EVNTSEL0 0x00000028 145#define MSR_KNC_EVNTSEL1 0x00000029 146 147/* Intel VT MSRs */ 148#define MSR_IA32_VMX_BASIC 0x00000480 149#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 150#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 151#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 152#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 153#define MSR_IA32_VMX_MISC 0x00000485 154#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 155#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 156#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 157#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 158#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 159#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 160#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 161#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 162#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 163#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 164#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 165 166/* VMX_BASIC bits and bitmasks */ 167#define VMX_BASIC_VMCS_SIZE_SHIFT 32 168#define VMX_BASIC_64 0x0001000000000000LLU 169#define VMX_BASIC_MEM_TYPE_SHIFT 50 170#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 171#define VMX_BASIC_MEM_TYPE_WB 6LLU 172#define VMX_BASIC_INOUT 0x0040000000000000LLU 173 174/* Intel defined MSRs. */ 175#define MSR_IA32_P5_MC_ADDR 0x00000000 176#define MSR_IA32_P5_MC_TYPE 0x00000001 177#define MSR_IA32_TSC 0x00000010 178#define MSR_IA32_PLATFORM_ID 0x00000017 179#define MSR_IA32_EBL_CR_POWERON 0x0000002a 180#define MSR_EBC_FREQUENCY_ID 0x0000002c 181#define MSR_IA32_FEATURE_CONTROL 0x0000003a 182#define MSR_IA32_TSC_ADJUST 0x0000003b 183 184#define FEATURE_CONTROL_LOCKED (1<<0) 185#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 186#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 187 188#define MSR_IA32_APICBASE 0x0000001b 189#define MSR_IA32_APICBASE_BSP (1<<8) 190#define MSR_IA32_APICBASE_ENABLE (1<<11) 191#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 192 193#define MSR_IA32_TSCDEADLINE 0x000006e0 194 195#define MSR_IA32_UCODE_WRITE 0x00000079 196#define MSR_IA32_UCODE_REV 0x0000008b 197 198#define MSR_IA32_PERF_STATUS 0x00000198 199#define MSR_IA32_PERF_CTL 0x00000199 200#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 201#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 202#define MSR_AMD_PERF_STATUS 0xc0010063 203#define MSR_AMD_PERF_CTL 0xc0010062 204 205#define MSR_IA32_MPERF 0x000000e7 206#define MSR_IA32_APERF 0x000000e8 207 208#define MSR_IA32_THERM_CONTROL 0x0000019a 209#define MSR_IA32_THERM_INTERRUPT 0x0000019b 210 211#define THERM_INT_HIGH_ENABLE (BIT(0)) 212#define THERM_INT_LOW_ENABLE (BIT(1)) 213#define THERM_INT_PLN_ENABLE (BIT(24)) 214 215#define MSR_IA32_THERM_STATUS 0x0000019c 216 217#define THERM_STATUS_PROCHOT (BIT(0)) 218#define THERM_STATUS_POWER_LIMIT (BIT(10)) 219 220#define MSR_THERM2_CTL 0x0000019d 221 222#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 223 224#define MSR_IA32_MISC_ENABLE 0x000001a0 225 226#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 227 228#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 229#define ENERGY_PERF_BIAS_PERFORMANCE 0 230#define ENERGY_PERF_BIAS_NORMAL 6 231#define ENERGY_PERF_BIAS_POWERSAVE 15 232 233#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 234 235#define PACKAGE_THERM_STATUS_PROCHOT (BIT(0)) 236#define PACKAGE_THERM_STATUS_POWER_LIMIT (BIT(10)) 237 238#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 239 240#define PACKAGE_THERM_INT_HIGH_ENABLE (BIT(0)) 241#define PACKAGE_THERM_INT_LOW_ENABLE (BIT(1)) 242#define PACKAGE_THERM_INT_PLN_ENABLE (BIT(24)) 243 244/* Thermal Thresholds Support */ 245#define THERM_INT_THRESHOLD0_ENABLE (BIT(15)) 246#define THERM_SHIFT_THRESHOLD0 8 247#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 248#define THERM_INT_THRESHOLD1_ENABLE (BIT(23)) 249#define THERM_SHIFT_THRESHOLD1 16 250#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 251#define THERM_STATUS_THRESHOLD0 (BIT(6)) 252#define THERM_LOG_THRESHOLD0 (BIT(7)) 253#define THERM_STATUS_THRESHOLD1 (BIT(8)) 254#define THERM_LOG_THRESHOLD1 (BIT(9)) 255 256/* MISC_ENABLE bits: architectural */ 257#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 258#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 259#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 260#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 261#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 262#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 263#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 264#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 265#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 266#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 267 268/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 269#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 270#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 271#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 272#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 273#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 274#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 275#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 276#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 277#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 278#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 279#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 280#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 281#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 282#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 283#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 284 285#define MSR_IA32_TSC_DEADLINE 0x000006E0 286 287