1/*
2 * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230)
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 */
6
7#pragma once
8
9#include <sel4vm/guest_memory.h>
10
11enum vm_lapic_state {
12    LAPIC_STATE_NEW,
13    LAPIC_STATE_WAITSIPI,
14    LAPIC_STATE_RUN
15};
16
17#if 0
18struct vm_timer {
19    struct hrtimer timer;
20    int64_t period;                 /* unit: ns */
21    uint32_t timer_mode_mask;
22    uint64_t tscdeadline;
23    atomic_t pending;           /* accumulated triggered timers */
24};
25#endif
26
27typedef struct vm_lapic {
28    uint32_t apic_base; // BSP flag is ignored in this
29
30    //struct vm_timer lapic_timer;
31    uint32_t divide_count;
32
33    bool irr_pending;
34    /* Number of bits set in ISR. */
35    int16_t isr_count;
36    /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
37    int highest_isr_cache;
38    /**
39     * APIC register page.  The layout matches the register layout seen by
40     * the guest 1:1, because it is accessed by the vmx microcode. XXX ???
41     * Note: Only one register, the TPR, is used by the microcode.
42     */
43    void *regs;
44    unsigned int sipi_vector;
45
46    enum vm_lapic_state state;
47    int arb_prio;
48} vm_lapic_t;
49
50int vm_apic_enabled(vm_lapic_t *apic);
51
52int vm_create_lapic(vm_vcpu_t *vcpu, int enabled);
53void vm_free_lapic(vm_vcpu_t *vcpu);
54
55int vm_apic_has_interrupt(vm_vcpu_t *vcpu);
56int vm_apic_get_interrupt(vm_vcpu_t *vcpu);
57
58void vm_apic_consume_extints(vm_vcpu_t *vcpu, int (*get)(void));
59
60/* MSR functions */
61void vm_lapic_set_base_msr(vm_vcpu_t *vcpu, uint32_t value);
62uint32_t vm_lapic_get_base_msr(vm_vcpu_t *vcpu);
63
64int vm_apic_local_deliver(vm_vcpu_t *vcpu, int lvt_type);
65int vm_apic_accept_pic_intr(vm_vcpu_t *vcpu);
66
67memory_fault_result_t apic_fault_callback(vm_t *vm, vm_vcpu_t *vcpu, uintptr_t fault_addr,
68                                          size_t fault_length, void *cookie);
69
70uint64_t vm_get_lapic_tscdeadline_msr(vm_vcpu_t *vcpu);
71void vm_set_lapic_tscdeadline_msr(vm_vcpu_t *vcpu, uint64_t data);
72
73