1/* 2 * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7/* This file contains macros for CPU features defined in x86. 8 * Ported from arch/x86/include/asm/cpufeature.h Linux kernel source 3.8.8. 9 * Authors: 10 * Qian Ge 11 */ 12 13#pragma once 14 15/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ 16#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ 17#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ 18#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ 19#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ 20#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ 21#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */ 22#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ 23#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */ 24#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ 25#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ 26#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ 27#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ 28#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ 29#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ 30#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */ 31/* (plus FCMOVcc, FCOMI with FPU) */ 32#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ 33#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ 34#define X86_FEATURE_PN (0*32+18) /* Processor serial number */ 35#define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */ 36#define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */ 37#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ 38#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ 39#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ 40#define X86_FEATURE_XMM (0*32+25) /* "sse" */ 41#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */ 42#define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */ 43#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ 44#define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */ 45#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ 46#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */ 47 48/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ 49/* Don't duplicate feature flags which are redundant with Intel! */ 50#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ 51#define X86_FEATURE_MP (1*32+19) /* MP Capable. */ 52#define X86_FEATURE_NX (1*32+20) /* Execute Disable */ 53#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ 54#define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */ 55#define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */ 56#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ 57#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ 58#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ 59#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ 60 61/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ 62#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ 63#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ 64#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ 65 66/* Other features, Linux-defined mapping, word 3 */ 67/* This range is used for feature bits which conflict or are synthesized */ 68#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ 69#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ 70#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ 71#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ 72/* cpu types for specific tunings: */ 73#define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */ 74#define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */ 75#define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */ 76#define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */ 77#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ 78#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ 79#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ 80#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ 81#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ 82#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 83#define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ 84#define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */ 85#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */ 86#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */ 87#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ 88#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ 89#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ 90/* 21 available, was AMD_C1E */ 91#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ 92#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ 93#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ 94#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */ 95#define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */ 96#define X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */ 97#define X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */ 98#define X86_FEATURE_EAGER_FPU (3*32+29) /* "eagerfpu" Non lazy FPU restore */ 99 100/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 101#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ 102#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */ 103#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ 104#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */ 105#define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ 106#define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */ 107#define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */ 108#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ 109#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ 110#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ 111#define X86_FEATURE_CID (4*32+10) /* Context ID */ 112#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */ 113#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ 114#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ 115#define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */ 116#define X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */ 117#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ 118#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */ 119#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */ 120#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ 121#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ 122#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ 123#define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */ 124#define X86_FEATURE_AES (4*32+25) /* AES instructions */ 125#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ 126#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ 127#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ 128#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */ 129#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */ 130#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ 131 132/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ 133#define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ 134#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */ 135#define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ 136#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */ 137#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ 138#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ 139#define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */ 140#define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */ 141#define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */ 142#define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */ 143 144/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ 145#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ 146#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ 147#define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ 148#define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ 149#define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */ 150#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ 151#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ 152#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */ 153#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ 154#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ 155#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ 156#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */ 157#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ 158#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ 159#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ 160#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ 161#define X86_FEATURE_TCE (6*32+17) /* translation cache extension */ 162#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ 163#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ 164#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ 165#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */ 166 167/* 168 * Auxiliary flags: Linux defined - For features scattered in various 169 * CPUID levels like 0x6, 0xA etc, word 7 170 */ 171#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ 172#define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */ 173#define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */ 174#define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ 175#define X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */ 176#define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ 177#define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ 178#define X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */ 179#define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */ 180 181/* Virtualization flags: Linux defined, word 8 */ 182#define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ 183#define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */ 184#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */ 185#define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */ 186#define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */ 187#define X86_FEATURE_NPT (8*32+ 5) /* AMD Nested Page Table support */ 188#define X86_FEATURE_LBRV (8*32+ 6) /* AMD LBR Virtualization support */ 189#define X86_FEATURE_SVML (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ 190#define X86_FEATURE_NRIPS (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ 191#define X86_FEATURE_TSCRATEMSR (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ 192#define X86_FEATURE_VMCBCLEAN (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ 193#define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */ 194#define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */ 195#define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */ 196#define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */ 197 198/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ 199#define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ 200#define X86_FEATURE_TSC_ADJUST (9*32+ 1) /* TSC adjustment MSR 0x3b */ 201#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */ 202#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ 203#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ 204#define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ 205#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */ 206#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ 207#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ 208#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ 209#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ 210#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ 211#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ 212 213