1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#include "sdhc.h" 14 15#include <autoconf.h> 16#include <stdio.h> 17#include <string.h> 18#include <assert.h> 19#include "services.h" 20#include "mmc.h" 21 22#define DS_ADDR 0x00 //DMA System Address 23#define BLK_ATT 0x04 //Block Attributes 24#define CMD_ARG 0x08 //Command Argument 25#define CMD_XFR_TYP 0x0C //Command Transfer Type 26#define CMD_RSP0 0x10 //Command Response0 27#define CMD_RSP1 0x14 //Command Response1 28#define CMD_RSP2 0x18 //Command Response2 29#define CMD_RSP3 0x1C //Command Response3 30#define DATA_BUFF_ACC_PORT 0x20 //Data Buffer Access Port 31#define PRES_STATE 0x24 //Present State 32#define PROT_CTRL 0x28 //Protocol Control 33#define SYS_CTRL 0x2C //System Control 34#define INT_STATUS 0x30 //Interrupt Status 35#define INT_STATUS_EN 0x34 //Interrupt Status Enable 36#define INT_SIGNAL_EN 0x38 //Interrupt Signal Enable 37#define AUTOCMD12_ERR_STATUS 0x3C //Auto CMD12 Error Status 38#define HOST_CTRL_CAP 0x40 //Host Controller Capabilities 39#define WTMK_LVL 0x44 //Watermark Level 40#define MIX_CTRL 0x48 //Mixer Control 41#define FORCE_EVENT 0x50 //Force Event 42#define ADMA_ERR_STATUS 0x54 //ADMA Error Status Register 43#define ADMA_SYS_ADDR 0x58 //ADMA System Address 44#define DLL_CTRL 0x60 //DLL (Delay Line) Control 45#define DLL_STATUS 0x64 //DLL Status 46#define CLK_TUNE_CTRL_STATUS 0x68 //CLK Tuning Control and Status 47#define VEND_SPEC 0xC0 //Vendor Specific Register 48#define MMC_BOOT 0xC4 //MMC Boot Register 49#define VEND_SPEC2 0xC8 //Vendor Specific 2 Register 50#define HOST_VERSION 0xFC //Host Version (0xFE adjusted for alignment) 51 52 53/* Block Attributes Register */ 54#define BLK_ATT_BLKCNT_SHF 16 //Blocks Count For Current Transfer 55#define BLK_ATT_BLKCNT_MASK 0xFFFF //Blocks Count For Current Transfer 56#define BLK_ATT_BLKSIZE_SHF 0 //Transfer Block Size 57#define BLK_ATT_BLKSIZE_MASK 0xFFF //Transfer Block Size 58 59/* Command Transfer Type Register */ 60#define CMD_XFR_TYP_CMDINX_SHF 24 //Command Index 61#define CMD_XFR_TYP_CMDINX_MASK 0x3F //Command Index 62#define CMD_XFR_TYP_CMDTYP_SHF 22 //Command Type 63#define CMD_XFR_TYP_CMDTYP_MASK 0x3 //Command Type 64#define CMD_XFR_TYP_DPSEL (1 << 21) //Data Present Select 65#define CMD_XFR_TYP_CICEN (1 << 20) //Command Index Check Enable 66#define CMD_XFR_TYP_CCCEN (1 << 19) //Command CRC Check Enable 67#define CMD_XFR_TYP_RSPTYP_SHF 16 //Response Type Select 68#define CMD_XFR_TYP_RSPTYP_MASK 0x3 //Response Type Select 69 70/* System Control Register */ 71#define SYS_CTRL_INITA (1 << 27) //Initialization Active 72#define SYS_CTRL_RSTD (1 << 26) //Software Reset for DAT Line 73#define SYS_CTRL_RSTC (1 << 25) //Software Reset for CMD Line 74#define SYS_CTRL_RSTA (1 << 24) //Software Reset for ALL 75#define SYS_CTRL_DTOCV_SHF 16 //Data Timeout Counter Value 76#define SYS_CTRL_DTOCV_MASK 0xF //Data Timeout Counter Value 77#define SYS_CTRL_SDCLKS_SHF 8 //SDCLK Frequency Select 78#define SYS_CTRL_SDCLKS_MASK 0xFF //SDCLK Frequency Select 79#define SYS_CTRL_DVS_SHF 4 //Divisor 80#define SYS_CTRL_DVS_MASK 0xF //Divisor 81#define SYS_CTRL_CLK_INT_EN (1 << 0) //Internal clock enable (exl. IMX6) 82#define SYS_CTRL_CLK_INT_STABLE (1 << 1) //Internal clock stable (exl. IMX6) 83#define SYS_CTRL_CLK_CARD_EN (1 << 2) //SD clock enable (exl. IMX6) 84 85/* Interrupt Status Register */ 86#define INT_STATUS_DMAE (1 << 28) //DMA Error (only IMX6) 87#define INT_STATUS_TNE (1 << 26) //Tuning Error 88#define INT_STATUS_ADMAE (1 << 25) //ADMA error (exl. IMX6) 89#define INT_STATUS_AC12E (1 << 24) //Auto CMD12 Error 90#define INT_STATUS_OVRCURE (1 << 23) //Bus over current (exl. IMX6) 91#define INT_STATUS_DEBE (1 << 22) //Data End Bit Error 92#define INT_STATUS_DCE (1 << 21) //Data CRC Error 93#define INT_STATUS_DTOE (1 << 20) //Data Timeout Error 94#define INT_STATUS_CIE (1 << 19) //Command Index Error 95#define INT_STATUS_CEBE (1 << 18) //Command End Bit Error 96#define INT_STATUS_CCE (1 << 17) //Command CRC Error 97#define INT_STATUS_CTOE (1 << 16) //Command Timeout Error 98#define INT_STATUS_ERR (1 << 15) //Error interrupt (exl. IMX6) 99#define INT_STATUS_TP (1 << 14) //Tuning Pass 100#define INT_STATUS_RTE (1 << 12) //Re-Tuning Event 101#define INT_STATUS_CINT (1 << 8) //Card Interrupt 102#define INT_STATUS_CRM (1 << 7) //Card Removal 103#define INT_STATUS_CINS (1 << 6) //Card Insertion 104#define INT_STATUS_BRR (1 << 5) //Buffer Read Ready 105#define INT_STATUS_BWR (1 << 4) //Buffer Write Ready 106#define INT_STATUS_DINT (1 << 3) //DMA Interrupt 107#define INT_STATUS_BGE (1 << 2) //Block Gap Event 108#define INT_STATUS_TC (1 << 1) //Transfer Complete 109#define INT_STATUS_CC (1 << 0) //Command Complete 110 111/* Host Controller Capabilities Register */ 112#define HOST_CTRL_CAP_VS18 (1 << 26) //Voltage Support 1.8V 113#define HOST_CTRL_CAP_VS30 (1 << 25) //Voltage Support 3.0V 114#define HOST_CTRL_CAP_VS33 (1 << 24) //Voltage Support 3.3V 115#define HOST_CTRL_CAP_SRS (1 << 23) //Suspend/Resume Support 116#define HOST_CTRL_CAP_DMAS (1 << 22) //DMA Support 117#define HOST_CTRL_CAP_HSS (1 << 21) //High Speed Support 118#define HOST_CTRL_CAP_ADMAS (1 << 20) //ADMA Support 119#define HOST_CTRL_CAP_MBL_SHF 16 //Max Block Length 120#define HOST_CTRL_CAP_MBL_MASK 0x3 //Max Block Length 121 122/* Mixer Control Register */ 123#define MIX_CTRL_MSBSEL (1 << 5) //Multi/Single Block Select. 124#define MIX_CTRL_DTDSEL (1 << 4) //Data Transfer Direction Select. 125#define MIX_CTRL_DDR_EN (1 << 3) //Dual Data Rate mode selection 126#define MIX_CTRL_AC12EN (1 << 2) //Auto CMD12 Enable 127#define MIX_CTRL_BCEN (1 << 1) //Block Count Enable 128#define MIX_CTRL_DMAEN (1 << 0) //DMA Enable 129 130/* Watermark Level register */ 131#define WTMK_LVL_WR_WML_SHF 16 //Write Watermark Level 132#define WTMK_LVL_RD_WML_SHF 0 //Read Watermark Level 133 134#define writel(v, a) (*(volatile uint32_t*)(a) = (v)) 135#define readl(a) (*(volatile uint32_t*)(a)) 136 137enum dma_mode { 138 DMA_MODE_NONE = 0, 139 DMA_MODE_SDMA, 140 DMA_MODE_ADMA 141}; 142 143typedef enum { 144 DIV_1 = 0x0, 145 DIV_2 = 0x1, 146 DIV_3 = 0x2, 147 DIV_4 = 0x3, 148 DIV_5 = 0x4, 149 DIV_6 = 0x5, 150 DIV_7 = 0x6, 151 DIV_8 = 0x7, 152 DIV_9 = 0x8, 153 DIV_10 = 0x9, 154 DIV_11 = 0xa, 155 DIV_12 = 0xb, 156 DIV_13 = 0xc, 157 DIV_14 = 0xd, 158 DIV_15 = 0xe, 159 DIV_16 = 0xf, 160} divisor; 161 162/* Selecting the prescaler value varies between SDR and DDR mode. When the 163 * value is set, this is accounted for with a bitshift (PRESCALER_X >> 1) */ 164typedef enum { 165 PRESCALER_1 = 0x0, //Only available in SDR mode 166 PRESCALER_2 = 0x1, 167 PRESCALER_4 = 0x2, 168 PRESCALER_8 = 0x4, 169 PRESCALER_16 = 0x8, 170 PRESCALER_32 = 0x10, 171 PRESCALER_64 = 0x20, 172 PRESCALER_128 = 0x40, 173 PRESCALER_256 = 0x80, 174 PRESCALER_512 = 0x100, //Only available in DDR mode 175} sdclk_frequency_select; 176 177typedef enum { 178 CLOCK_INITIAL = 0, 179 CLOCK_OPERATIONAL 180} clock_mode; 181 182typedef enum { 183 SDCLK_TIMES_2_POW_29 = 0xf, 184 SDCLK_TIMES_2_POW_28 = 0xe, 185 SDCLK_TIMES_2_POW_14 = 0x0, 186} data_timeout_counter_val; 187 188static inline sdhc_dev_t sdio_get_sdhc(sdio_host_dev_t *sdio) 189{ 190 return (sdhc_dev_t)sdio->priv; 191} 192 193/** Print uSDHC registers. */ 194UNUSED static void print_sdhc_regs(struct sdhc *host) 195{ 196 int i; 197 for (i = DS_ADDR; i <= HOST_VERSION; i += 0x4) { 198 ZF_LOGD("%x: %X", i, readl(host->base + i)); 199 } 200} 201 202static inline enum dma_mode get_dma_mode(struct sdhc *host, struct mmc_cmd *cmd) 203{ 204 if (cmd->data == NULL) { 205 return DMA_MODE_NONE; 206 } 207 if (cmd->data->pbuf == 0) { 208 return DMA_MODE_NONE; 209 } 210 /* Currently only SDMA supported */ 211 return DMA_MODE_SDMA; 212} 213 214static inline int cap_sdma_supported(struct sdhc *host) 215{ 216 uint32_t v; 217 v = readl(host->base + HOST_CTRL_CAP); 218 return !!(v & HOST_CTRL_CAP_DMAS); 219} 220 221static inline int cap_max_buffer_size(struct sdhc *host) 222{ 223 uint32_t v; 224 v = readl(host->base + HOST_CTRL_CAP); 225 v = ((v >> HOST_CTRL_CAP_MBL_SHF) & HOST_CTRL_CAP_MBL_MASK); 226 return 512 << v; 227} 228 229static int sdhc_next_cmd(sdhc_dev_t host) 230{ 231 struct mmc_cmd *cmd = host->cmd_list_head; 232 uint32_t val; 233 uint32_t mix_ctrl; 234 235 /* Enable IRQs */ 236 val = (INT_STATUS_ADMAE | INT_STATUS_OVRCURE | INT_STATUS_DEBE 237 | INT_STATUS_DCE | INT_STATUS_DTOE | INT_STATUS_CRM 238 | INT_STATUS_CINS | INT_STATUS_CIE | INT_STATUS_CEBE 239 | INT_STATUS_CCE | INT_STATUS_CTOE | INT_STATUS_TC 240 | INT_STATUS_CC); 241 if (get_dma_mode(host, cmd) == DMA_MODE_NONE) { 242 val |= INT_STATUS_BRR | INT_STATUS_BWR; 243 } 244 writel(val, host->base + INT_STATUS_EN); 245 246 /* Check if the Host is ready for transit. */ 247 while (readl(host->base + PRES_STATE) & (SDHC_PRES_STATE_CIHB | SDHC_PRES_STATE_CDIHB)); 248 while (readl(host->base + PRES_STATE) & SDHC_PRES_STATE_DLA); 249 250 /* Two commands need to have at least 8 clock cycles in between. 251 * Lets assume that the hcd will enforce this. */ 252 //udelay(1000); 253 254 /* Write to the argument register. */ 255 ZF_LOGD("CMD: %d with arg %x ", cmd->index, cmd->arg); 256 writel(cmd->arg, host->base + CMD_ARG); 257 258 if (cmd->data) { 259 /* Use the default timeout. */ 260 val = readl(host->base + SYS_CTRL); 261 val &= ~(0xffUL << 16); 262 val |= 0xE << 16; 263 writel(val, host->base + SYS_CTRL); 264 265 /* Set the DMA boundary. */ 266 val = (cmd->data->block_size & BLK_ATT_BLKSIZE_MASK); 267 val |= (cmd->data->blocks << BLK_ATT_BLKCNT_SHF); 268 writel(val, host->base + BLK_ATT); 269 270 /* Set watermark level */ 271 val = cmd->data->block_size / 4; 272 if (val > 0x80) { 273 val = 0x80; 274 } 275 if (cmd->index == MMC_READ_SINGLE_BLOCK) { 276 val = (val << WTMK_LVL_RD_WML_SHF); 277 } else { 278 val = (val << WTMK_LVL_WR_WML_SHF); 279 } 280 writel(val, host->base + WTMK_LVL); 281 282 /* Set Mixer Control */ 283 mix_ctrl = MIX_CTRL_BCEN; 284 if (cmd->data->blocks > 1) { 285 mix_ctrl |= MIX_CTRL_MSBSEL; 286 } 287 if (cmd->index == MMC_READ_SINGLE_BLOCK) { 288 mix_ctrl |= MIX_CTRL_DTDSEL; 289 } 290 291 /* Configure DMA */ 292 if (get_dma_mode(host, cmd) != DMA_MODE_NONE) { 293 /* Enable DMA */ 294 mix_ctrl |= MIX_CTRL_DMAEN; 295 /* Set DMA address */ 296 writel(cmd->data->pbuf, host->base + DS_ADDR); 297 } 298 /* Record the number of blocks to be sent */ 299 host->blocks_remaining = cmd->data->blocks; 300 } 301 302 /* The command should be MSB and the first two bits should be '00' */ 303 val = (cmd->index & CMD_XFR_TYP_CMDINX_MASK) << CMD_XFR_TYP_CMDINX_SHF; 304 val &= ~(CMD_XFR_TYP_CMDTYP_MASK << CMD_XFR_TYP_CMDTYP_SHF); 305 if (cmd->data) { 306 if (host->version == 2) { 307 /* Some controllers implement MIX_CTRL as part of the XFR_TYP */ 308 val |= mix_ctrl; 309 } else { 310 writel(mix_ctrl, host->base + MIX_CTRL); 311 } 312 } 313 314 /* Set response type */ 315 val &= ~CMD_XFR_TYP_CICEN; 316 val &= ~CMD_XFR_TYP_CCCEN; 317 val &= ~(CMD_XFR_TYP_RSPTYP_MASK << CMD_XFR_TYP_RSPTYP_SHF); 318 switch (cmd->rsp_type) { 319 case MMC_RSP_TYPE_R2: 320 val |= (0x1 << CMD_XFR_TYP_RSPTYP_SHF); 321 val |= CMD_XFR_TYP_CCCEN; 322 break; 323 case MMC_RSP_TYPE_R3: 324 case MMC_RSP_TYPE_R4: 325 val |= (0x2 << CMD_XFR_TYP_RSPTYP_SHF); 326 break; 327 case MMC_RSP_TYPE_R1: 328 case MMC_RSP_TYPE_R5: 329 case MMC_RSP_TYPE_R6: 330 val |= (0x2 << CMD_XFR_TYP_RSPTYP_SHF); 331 val |= CMD_XFR_TYP_CICEN; 332 val |= CMD_XFR_TYP_CCCEN; 333 break; 334 case MMC_RSP_TYPE_R1b: 335 case MMC_RSP_TYPE_R5b: 336 val |= (0x3 << CMD_XFR_TYP_RSPTYP_SHF); 337 val |= CMD_XFR_TYP_CICEN; 338 val |= CMD_XFR_TYP_CCCEN; 339 break; 340 default: 341 break; 342 } 343 344 if (cmd->data) { 345 val |= CMD_XFR_TYP_DPSEL; 346 } 347 348 /* Issue the command. */ 349 writel(val, host->base + CMD_XFR_TYP); 350 return 0; 351} 352 353 354 355/** Pass control to the devices IRQ handler 356 * @param[in] sd_dev The sdhc interface device that triggered 357 * the interrupt event. 358 */ 359static int sdhc_handle_irq(sdio_host_dev_t *sdio, int irq UNUSED) 360{ 361 sdhc_dev_t host = sdio_get_sdhc(sdio); 362 struct mmc_cmd *cmd = host->cmd_list_head; 363 uint32_t int_status; 364 365 int_status = readl(host->base + INT_STATUS); 366 if (!cmd) { 367 /* Clear flags */ 368 writel(int_status, host->base + INT_STATUS); 369 return 0; 370 } 371 /** Handle errors **/ 372 if (int_status & INT_STATUS_TNE) { 373 ZF_LOGE("Tuning error"); 374 } 375 if (int_status & INT_STATUS_OVRCURE) { 376 ZF_LOGE("Bus overcurrent"); /* (exl. IMX6) */ 377 } 378 if (int_status & INT_STATUS_ERR) { 379 ZF_LOGE("CMD/DATA transfer error"); /* (exl. IMX6) */ 380 cmd->complete = -1; 381 } 382 if (int_status & INT_STATUS_AC12E) { 383 ZF_LOGE("Auto CMD12 Error"); 384 cmd->complete = -1; 385 } 386 /** DMA errors **/ 387 if (int_status & INT_STATUS_DMAE) { 388 ZF_LOGE("DMA Error"); 389 cmd->complete = -1; 390 } 391 if (int_status & INT_STATUS_ADMAE) { 392 ZF_LOGE("ADMA error"); /* (exl. IMX6) */ 393 cmd->complete = -1; 394 } 395 /** DATA errors **/ 396 if (int_status & INT_STATUS_DEBE) { 397 ZF_LOGE("Data end bit error"); 398 cmd->complete = -1; 399 } 400 if (int_status & INT_STATUS_DCE) { 401 ZF_LOGE("Data CRC error"); 402 cmd->complete = -1; 403 } 404 if (int_status & INT_STATUS_DTOE) { 405 ZF_LOGE("Data transfer error"); 406 cmd->complete = -1; 407 } 408 /** CMD errors **/ 409 if (int_status & INT_STATUS_CIE) { 410 ZF_LOGE("Command index error"); 411 cmd->complete = -1; 412 } 413 if (int_status & INT_STATUS_CEBE) { 414 ZF_LOGE("Command end bit error"); 415 cmd->complete = -1; 416 } 417 if (int_status & INT_STATUS_CCE) { 418 ZF_LOGE("Command CRC error"); 419 cmd->complete = -1; 420 } 421 if (int_status & INT_STATUS_CTOE) { 422 ZF_LOGE("CMD Timeout..."); 423 cmd->complete = -1; 424 } 425 426 if (int_status & INT_STATUS_TP) { 427 ZF_LOGD("Tuning pass"); 428 } 429 if (int_status & INT_STATUS_RTE) { 430 ZF_LOGD("Retuning event"); 431 } 432 if (int_status & INT_STATUS_CINT) { 433 ZF_LOGD("Card interrupt"); 434 } 435 if (int_status & INT_STATUS_CRM) { 436 ZF_LOGD("Card removal"); 437 cmd->complete = -1; 438 } 439 if (int_status & INT_STATUS_CINS) { 440 ZF_LOGD("Card insertion"); 441 } 442 if (int_status & INT_STATUS_DINT) { 443 ZF_LOGD("DMA interrupt"); 444 } 445 if (int_status & INT_STATUS_BGE) { 446 ZF_LOGD("Block gap event"); 447 } 448 449 /* Command complete */ 450 if (int_status & INT_STATUS_CC) { 451 /* Command complete */ 452 switch (cmd->rsp_type) { 453 case MMC_RSP_TYPE_R2: 454 cmd->response[0] = readl(host->base + CMD_RSP0); 455 cmd->response[1] = readl(host->base + CMD_RSP1); 456 cmd->response[2] = readl(host->base + CMD_RSP2); 457 cmd->response[3] = readl(host->base + CMD_RSP3); 458 break; 459 case MMC_RSP_TYPE_R1b: 460 if (cmd->index == MMC_STOP_TRANSMISSION) { 461 cmd->response[3] = readl(host->base + CMD_RSP3); 462 } else { 463 cmd->response[0] = readl(host->base + CMD_RSP0); 464 } 465 break; 466 case MMC_RSP_TYPE_NONE: 467 break; 468 default: 469 cmd->response[0] = readl(host->base + CMD_RSP0); 470 } 471 472 /* If there is no data segment, the transfer is complete */ 473 if (cmd->data == NULL) { 474 assert(cmd->complete == 0); 475 cmd->complete = 1; 476 } 477 } 478 /* DATA: Programmed IO handling */ 479 if (int_status & (INT_STATUS_BRR | INT_STATUS_BWR)) { 480 volatile uint32_t *io_buf; 481 uint32_t *usr_buf; 482 assert(cmd->data); 483 assert(cmd->data->vbuf); 484 assert(cmd->complete == 0); 485 if (host->blocks_remaining) { 486 io_buf = (volatile uint32_t *)((void *)host->base + DATA_BUFF_ACC_PORT); 487 usr_buf = (uint32_t *)cmd->data->vbuf; 488 if (int_status & INT_STATUS_BRR) { 489 /* Buffer Read Ready */ 490 int i; 491 for (i = 0; i < cmd->data->block_size; i += sizeof(*usr_buf)) { 492 *usr_buf++ = *io_buf; 493 } 494 } else { 495 /* Buffer Write Ready */ 496 int i; 497 for (i = 0; i < cmd->data->block_size; i += sizeof(*usr_buf)) { 498 *io_buf = *usr_buf++; 499 } 500 } 501 host->blocks_remaining--; 502 } 503 } 504 /* Data complete */ 505 if (int_status & INT_STATUS_TC) { 506 assert(cmd->complete == 0); 507 cmd->complete = 1; 508 } 509 /* Clear flags */ 510 writel(int_status, host->base + INT_STATUS); 511 512 /* If the transaction has finished */ 513 if (cmd != NULL && cmd->complete != 0) { 514 if (cmd->next == NULL) { 515 /* Shutdown */ 516 host->cmd_list_head = NULL; 517 host->cmd_list_tail = &host->cmd_list_head; 518 } else { 519 /* Next */ 520 host->cmd_list_head = cmd->next; 521 sdhc_next_cmd(host); 522 } 523 cmd->next = NULL; 524 /* Send callback if required */ 525 if (cmd->cb) { 526 cmd->cb(sdio, 0, cmd, cmd->token); 527 } 528 } 529 530 return 0; 531} 532 533static int sdhc_is_voltage_compatible(sdio_host_dev_t *sdio, int mv) 534{ 535 uint32_t val; 536 sdhc_dev_t host = sdio_get_sdhc(sdio); 537 val = readl(host->base + HOST_CTRL_CAP); 538 if (mv == 3300 && (val & HOST_CTRL_CAP_VS33)) { 539 return 1; 540 } else { 541 return 0; 542 } 543} 544 545static int sdhc_send_cmd(sdio_host_dev_t *sdio, struct mmc_cmd *cmd, sdio_cb cb, void *token) 546{ 547 sdhc_dev_t host = sdio_get_sdhc(sdio); 548 int ret; 549 550 /* Initialise callbacks */ 551 cmd->complete = 0; 552 cmd->next = NULL; 553 cmd->cb = cb; 554 cmd->token = token; 555 /* Append to list */ 556 *host->cmd_list_tail = cmd; 557 host->cmd_list_tail = &cmd->next; 558 559 /* If idle, bump */ 560 if (host->cmd_list_head == cmd) { 561 ret = sdhc_next_cmd(host); 562 if (ret) { 563 return ret; 564 } 565 } 566 567 /* finalise the transacton */ 568 if (cb == NULL) { 569 /* Wait for completion */ 570 while (!cmd->complete) { 571 sdhc_handle_irq(sdio, 0); 572 } 573 /* Return result */ 574 if (cmd->complete < 0) { 575 return cmd->complete; 576 } else { 577 return 0; 578 } 579 } else { 580 /* Defer to IRQ handler */ 581 return 0; 582 } 583} 584 585static void sdhc_enable_clock(volatile void *base_addr) 586{ 587 uint32_t val; 588 589 val = readl(base_addr + SYS_CTRL); 590 val |= SYS_CTRL_CLK_INT_EN; 591 writel(val, base_addr + SYS_CTRL); 592 593 do { 594 val = readl(base_addr + SYS_CTRL); 595 } while (!(val & SYS_CTRL_CLK_INT_STABLE)); 596 597 val |= SYS_CTRL_CLK_CARD_EN; 598 writel(val, base_addr + SYS_CTRL); 599 600 return; 601} 602 603/* Set the clock divider and timeout */ 604static int sdhc_set_clock_div( 605 volatile void *base_addr, 606 divisor dvs_div, 607 sdclk_frequency_select sdclks_div, 608 data_timeout_counter_val dtocv) 609{ 610 /* make sure the clock state is stable. */ 611 if (readl(base_addr + PRES_STATE) & SDHC_PRES_STATE_SDSTB) { 612 uint32_t val = readl(base_addr + SYS_CTRL); 613 614 /* The SDCLK bit varies with Data Rate Mode. */ 615 if (readl(base_addr + MIX_CTRL) & MIX_CTRL_DDR_EN) { 616 val &= ~(SYS_CTRL_SDCLKS_MASK << SYS_CTRL_SDCLKS_SHF); 617 val |= ((sdclks_div >> 1) << SYS_CTRL_SDCLKS_SHF); 618 619 } else { 620 val &= ~(SYS_CTRL_SDCLKS_MASK << SYS_CTRL_SDCLKS_SHF); 621 val |= (sdclks_div << SYS_CTRL_SDCLKS_SHF); 622 } 623 val &= ~(SYS_CTRL_DVS_MASK << SYS_CTRL_DVS_SHF); 624 val |= (dvs_div << SYS_CTRL_DVS_SHF); 625 626 /* Set data timeout value */ 627 val |= (dtocv << SYS_CTRL_DTOCV_SHF); 628 writel(val, base_addr + SYS_CTRL); 629 } else { 630 ZF_LOGE("The clock is unstable, unable to change it!"); 631 return -1; 632 } 633 634 return 0; 635} 636 637static int sdhc_set_clock(volatile void *base_addr, clock_mode clk_mode) 638{ 639 int rslt = -1; 640 641 const bool isClkEnabled = readl(base_addr + SYS_CTRL) & SYS_CTRL_CLK_INT_EN; 642 if (!isClkEnabled) { 643 sdhc_enable_clock(base_addr); 644 } 645 646 /* TODO: Relate the clock rate settings to the actual capabilities of the 647 * card and the host controller. The conservative settings chosen should 648 * work with most setups, but this is not an ideal solution. According to 649 * the RM, the default freq. of the base clock should be at around 200MHz. 650 */ 651 switch (clk_mode) { 652 case CLOCK_INITIAL: 653 /* Divide the base clock by 512 */ 654 rslt = sdhc_set_clock_div(base_addr, DIV_16, PRESCALER_32, SDCLK_TIMES_2_POW_14); 655 break; 656 case CLOCK_OPERATIONAL: 657 /* Divide the base clock by 8 */ 658 rslt = sdhc_set_clock_div(base_addr, DIV_4, PRESCALER_2, SDCLK_TIMES_2_POW_29); 659 break; 660 default: 661 ZF_LOGE("Unsupported clock mode setting"); 662 rslt = -1; 663 break; 664 } 665 666 if (rslt < 0) { 667 ZF_LOGE("Failed to change the clock settings"); 668 } 669 670 return rslt; 671} 672 673/** Software Reset */ 674static int sdhc_reset(sdio_host_dev_t *sdio) 675{ 676 sdhc_dev_t host = sdio_get_sdhc(sdio); 677 uint32_t val; 678 679 /* Reset the host */ 680 val = readl(host->base + SYS_CTRL); 681 val |= SYS_CTRL_RSTA; 682 /* Wait until the controller is ready */ 683 writel(val, host->base + SYS_CTRL); 684 do { 685 val = readl(host->base + SYS_CTRL); 686 } while (val & SYS_CTRL_RSTA); 687 688 /* Enable IRQs */ 689 val = (INT_STATUS_ADMAE | INT_STATUS_OVRCURE | INT_STATUS_DEBE 690 | INT_STATUS_DCE | INT_STATUS_DTOE | INT_STATUS_CRM 691 | INT_STATUS_CINS | INT_STATUS_BRR | INT_STATUS_BWR 692 | INT_STATUS_CIE | INT_STATUS_CEBE | INT_STATUS_CCE 693 | INT_STATUS_CTOE | INT_STATUS_TC | INT_STATUS_CC); 694 writel(val, host->base + INT_STATUS_EN); 695 writel(val, host->base + INT_SIGNAL_EN); 696 697 /* Configure clock for initialization */ 698 sdhc_set_clock(host->base, CLOCK_INITIAL); 699 700 /* TODO: Select Voltage Level */ 701 702 /* Set bus width */ 703 val = readl(host->base + PROT_CTRL); 704 val |= MMC_MODE_4BIT; 705 writel(val, host->base + PROT_CTRL); 706 707 /* Wait until the Command and Data Lines are ready. */ 708 while ((readl(host->base + PRES_STATE) & SDHC_PRES_STATE_CDIHB) || 709 (readl(host->base + PRES_STATE) & SDHC_PRES_STATE_CIHB)); 710 711 /* Send 80 clock ticks to card to power up. */ 712 val = readl(host->base + SYS_CTRL); 713 val |= SYS_CTRL_INITA; 714 writel(val, host->base + SYS_CTRL); 715 while (readl(host->base + SYS_CTRL) & SYS_CTRL_INITA); 716 717 /* Check if a SD card is inserted. */ 718 val = readl(host->base + PRES_STATE); 719 if (val & SDHC_PRES_STATE_CINST) { 720 ZF_LOGD("Card Inserted"); 721 if (!(val & SDHC_PRES_STATE_WPSPL)) { 722 ZF_LOGD("(Read Only)"); 723 } 724 } else { 725 ZF_LOGE("Card Not Present..."); 726 } 727 728 return 0; 729} 730 731static int sdhc_get_nth_irq(sdio_host_dev_t *sdio, int n) 732{ 733 sdhc_dev_t host = sdio_get_sdhc(sdio); 734 if (n < 0 || n >= host->nirqs) { 735 return -1; 736 } else { 737 return host->irq_table[n]; 738 } 739} 740 741static uint32_t sdhc_get_present_state_register(sdio_host_dev_t *sdio) 742{ 743 return readl(sdio_get_sdhc(sdio)->base + PRES_STATE); 744} 745 746static int sdhc_set_operational(struct sdio_host_dev *sdio) 747{ 748 /* 749 * Set the clock to a higher frequency for the operational state. 750 * 751 * As of now, there are no further checks to validate if the card and the 752 * host controller could be driven with a higher rate, therefore the 753 * operational clock settings are chosen rather conservative. 754 */ 755 sdhc_dev_t host = sdio_get_sdhc(sdio); 756 return sdhc_set_clock(host->base, CLOCK_OPERATIONAL); 757} 758 759int sdhc_init(void *iobase, const int *irq_table, int nirqs, ps_io_ops_t *io_ops, 760 sdio_host_dev_t *dev) 761{ 762 sdhc_dev_t sdhc; 763 /* Allocate memory for SDHC structure */ 764 sdhc = (sdhc_dev_t)malloc(sizeof(*sdhc)); 765 if (!sdhc) { 766 ZF_LOGE("Not enough memory!"); 767 return -1; 768 } 769 /* Complete the initialisation of the SDHC structure */ 770 sdhc->base = iobase; 771 sdhc->nirqs = nirqs; 772 sdhc->irq_table = irq_table; 773 sdhc->dalloc = &io_ops->dma_manager; 774 sdhc->cmd_list_head = NULL; 775 sdhc->cmd_list_tail = &sdhc->cmd_list_head; 776 sdhc->version = ((readl(sdhc->base + HOST_VERSION) >> 16) & 0xff) + 1; 777 ZF_LOGD("SDHC version %d.00", sdhc->version); 778 /* Initialise SDIO structure */ 779 dev->handle_irq = &sdhc_handle_irq; 780 dev->nth_irq = &sdhc_get_nth_irq; 781 dev->send_command = &sdhc_send_cmd; 782 dev->is_voltage_compatible = &sdhc_is_voltage_compatible; 783 dev->reset = &sdhc_reset; 784 dev->set_operational = &sdhc_set_operational; 785 dev->get_present_state = &sdhc_get_present_state_register; 786 dev->priv = sdhc; 787 /* Clear IRQs */ 788 writel(0, sdhc->base + INT_STATUS_EN); 789 writel(0, sdhc->base + INT_SIGNAL_EN); 790 writel(readl(sdhc->base + INT_STATUS), sdhc->base + INT_STATUS); 791 return 0; 792} 793 794 795