1289177Speter/*
2289177Speter * Copyright Linux Kernel Team
3289177Speter *
4289177Speter * SPDX-License-Identifier: GPL-2.0-only
5289177Speter *
6289177Speter * This file is derived from an intermediate build stage of the
7289177Speter * Linux kernel. The licenses of all input files to this process
8289177Speter * are compatible with GPL-2.0-only.
9289177Speter */
10289177Speter
11289177Speter/dts-v1/;
12289177Speter
13289177Speter/ {
14289177Speter	compatible = "hisilicon,hi6220-hikey\0hisilicon,hi6220";
15289177Speter	interrupt-parent = < 0x01 >;
16289177Speter	#address-cells = < 0x02 >;
17289177Speter	#size-cells = < 0x02 >;
18289177Speter	model = "HiKey Development Board";
19289177Speter
20289177Speter	psci {
21289177Speter		compatible = "arm,psci-0.2";
22289177Speter		method = "smc";
23289177Speter	};
24289177Speter
25289177Speter	cpus {
26289177Speter		#address-cells = < 0x02 >;
27289177Speter		#size-cells = < 0x00 >;
28289177Speter
29289177Speter		cpu-map {
30289177Speter
31289177Speter			cluster0 {
32289177Speter
33289177Speter				core0 {
34289177Speter					cpu = < 0x02 >;
35289177Speter				};
36289177Speter
37289177Speter				core1 {
38289177Speter					cpu = < 0x03 >;
39289177Speter				};
40289177Speter
41289177Speter				core2 {
42289177Speter					cpu = < 0x04 >;
43289177Speter				};
44289177Speter
45289177Speter				core3 {
46289177Speter					cpu = < 0x05 >;
47289177Speter				};
48289177Speter			};
49289177Speter
50289177Speter			cluster1 {
51289177Speter
52289177Speter				core0 {
53289177Speter					cpu = < 0x06 >;
54289177Speter				};
55289177Speter
56289177Speter				core1 {
57289177Speter					cpu = < 0x07 >;
58289177Speter				};
59289177Speter
60289177Speter				core2 {
61289177Speter					cpu = < 0x08 >;
62289177Speter				};
63289177Speter
64289177Speter				core3 {
65289177Speter					cpu = < 0x09 >;
66289177Speter				};
67289177Speter			};
68289177Speter		};
69289177Speter
70289177Speter		idle-states {
71289177Speter			entry-method = "psci";
72289177Speter
73289177Speter			cpu-sleep {
74289177Speter				compatible = "arm,idle-state";
75289177Speter				local-timer-stop;
76289177Speter				arm,psci-suspend-param = < 0x10000 >;
77289177Speter				entry-latency-us = < 0x2bc >;
78289177Speter				exit-latency-us = < 0xfa >;
79289177Speter				min-residency-us = < 0x3e8 >;
80289177Speter				phandle = < 0x0d >;
81289177Speter			};
82289177Speter
83289177Speter			cluster-sleep {
84289177Speter				compatible = "arm,idle-state";
85289177Speter				local-timer-stop;
86289177Speter				arm,psci-suspend-param = < 0x1010000 >;
87289177Speter				entry-latency-us = < 0x3e8 >;
88289177Speter				exit-latency-us = < 0x2bc >;
89289177Speter				min-residency-us = < 0xa8c >;
90289177Speter				wakeup-latency-us = < 0x5dc >;
91289177Speter				phandle = < 0x0e >;
92289177Speter			};
93289177Speter		};
94289177Speter
95289177Speter		cpu@0 {
96289177Speter			compatible = "arm,cortex-a53\0arm,armv8";
97289177Speter			device_type = "cpu";
98289177Speter			reg = < 0x00 0x00 >;
99289177Speter			enable-method = "psci";
100289177Speter			next-level-cache = < 0x0a >;
101289177Speter			clocks = < 0x0b 0x00 >;
102289177Speter			operating-points-v2 = < 0x0c >;
103289177Speter			cpu-idle-states = < 0x0d 0x0e >;
104289177Speter			#cooling-cells = < 0x02 >;
105289177Speter			dynamic-power-coefficient = < 0x137 >;
106289177Speter			phandle = < 0x02 >;
107289177Speter		};
108289177Speter
109289177Speter		cpu@1 {
110289177Speter			compatible = "arm,cortex-a53\0arm,armv8";
111289177Speter			device_type = "cpu";
112289177Speter			reg = < 0x00 0x01 >;
113			enable-method = "psci";
114			next-level-cache = < 0x0a >;
115			clocks = < 0x0b 0x00 >;
116			operating-points-v2 = < 0x0c >;
117			cpu-idle-states = < 0x0d 0x0e >;
118			#cooling-cells = < 0x02 >;
119			dynamic-power-coefficient = < 0x137 >;
120			phandle = < 0x03 >;
121		};
122
123		cpu@2 {
124			compatible = "arm,cortex-a53\0arm,armv8";
125			device_type = "cpu";
126			reg = < 0x00 0x02 >;
127			enable-method = "psci";
128			next-level-cache = < 0x0a >;
129			clocks = < 0x0b 0x00 >;
130			operating-points-v2 = < 0x0c >;
131			cpu-idle-states = < 0x0d 0x0e >;
132			#cooling-cells = < 0x02 >;
133			dynamic-power-coefficient = < 0x137 >;
134			phandle = < 0x04 >;
135		};
136
137		cpu@3 {
138			compatible = "arm,cortex-a53\0arm,armv8";
139			device_type = "cpu";
140			reg = < 0x00 0x03 >;
141			enable-method = "psci";
142			next-level-cache = < 0x0a >;
143			clocks = < 0x0b 0x00 >;
144			operating-points-v2 = < 0x0c >;
145			cpu-idle-states = < 0x0d 0x0e >;
146			#cooling-cells = < 0x02 >;
147			dynamic-power-coefficient = < 0x137 >;
148			phandle = < 0x05 >;
149		};
150
151		cpu@100 {
152			compatible = "arm,cortex-a53\0arm,armv8";
153			device_type = "cpu";
154			reg = < 0x00 0x100 >;
155			enable-method = "psci";
156			next-level-cache = < 0x0f >;
157			clocks = < 0x0b 0x00 >;
158			operating-points-v2 = < 0x0c >;
159			cpu-idle-states = < 0x0d 0x0e >;
160			#cooling-cells = < 0x02 >;
161			dynamic-power-coefficient = < 0x137 >;
162			phandle = < 0x06 >;
163		};
164
165		cpu@101 {
166			compatible = "arm,cortex-a53\0arm,armv8";
167			device_type = "cpu";
168			reg = < 0x00 0x101 >;
169			enable-method = "psci";
170			next-level-cache = < 0x0f >;
171			clocks = < 0x0b 0x00 >;
172			operating-points-v2 = < 0x0c >;
173			cpu-idle-states = < 0x0d 0x0e >;
174			#cooling-cells = < 0x02 >;
175			dynamic-power-coefficient = < 0x137 >;
176			phandle = < 0x07 >;
177		};
178
179		cpu@102 {
180			compatible = "arm,cortex-a53\0arm,armv8";
181			device_type = "cpu";
182			reg = < 0x00 0x102 >;
183			enable-method = "psci";
184			next-level-cache = < 0x0f >;
185			clocks = < 0x0b 0x00 >;
186			operating-points-v2 = < 0x0c >;
187			cpu-idle-states = < 0x0d 0x0e >;
188			#cooling-cells = < 0x02 >;
189			dynamic-power-coefficient = < 0x137 >;
190			phandle = < 0x08 >;
191		};
192
193		cpu@103 {
194			compatible = "arm,cortex-a53\0arm,armv8";
195			device_type = "cpu";
196			reg = < 0x00 0x103 >;
197			enable-method = "psci";
198			next-level-cache = < 0x0f >;
199			clocks = < 0x0b 0x00 >;
200			operating-points-v2 = < 0x0c >;
201			cpu-idle-states = < 0x0d 0x0e >;
202			#cooling-cells = < 0x02 >;
203			dynamic-power-coefficient = < 0x137 >;
204			phandle = < 0x09 >;
205		};
206
207		l2-cache0 {
208			compatible = "cache";
209			phandle = < 0x0a >;
210		};
211
212		l2-cache1 {
213			compatible = "cache";
214			phandle = < 0x0f >;
215		};
216	};
217
218	cpu_opp_table {
219		compatible = "operating-points-v2";
220		opp-shared;
221		phandle = < 0x0c >;
222
223		opp00 {
224			opp-hz = < 0x00 0xc65d400 >;
225			opp-microvolt = < 0xfde80 >;
226			clock-latency-ns = < 0x7a120 >;
227		};
228
229		opp01 {
230			opp-hz = < 0x00 0x19bfcc00 >;
231			opp-microvolt = < 0xfde80 >;
232			clock-latency-ns = < 0x7a120 >;
233		};
234
235		opp02 {
236			opp-hz = < 0x00 0x2b73a840 >;
237			opp-microvolt = < 0x10a1d0 >;
238			clock-latency-ns = < 0x7a120 >;
239		};
240
241		opp03 {
242			opp-hz = < 0x00 0x39387000 >;
243			opp-microvolt = < 0x120160 >;
244			clock-latency-ns = < 0x7a120 >;
245		};
246
247		opp04 {
248			opp-hz = < 0x00 0x47868c00 >;
249			opp-microvolt = < 0x144b50 >;
250			clock-latency-ns = < 0x7a120 >;
251		};
252	};
253
254	interrupt-controller@f6801000 {
255		compatible = "arm,gic-400";
256		reg = < 0x00 0xf6801000 0x00 0x1000 0x00 0xf6802000 0x00 0x2000 0x00 0xf6804000 0x00 0x2000 0x00 0xf6806000 0x00 0x2000 >;
257		#address-cells = < 0x00 >;
258		#interrupt-cells = < 0x03 >;
259		interrupt-controller;
260		interrupts = < 0x01 0x09 0xff04 >;
261		phandle = < 0x01 >;
262	};
263
264	timer {
265		compatible = "arm,armv8-timer";
266		interrupt-parent = < 0x01 >;
267		interrupts = < 0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0a 0xff08 >;
268	};
269
270	soc {
271		compatible = "simple-bus";
272		#address-cells = < 0x02 >;
273		#size-cells = < 0x02 >;
274		ranges;
275
276		sram@fff80000 {
277			compatible = "hisilicon,hi6220-sramctrl\0syscon";
278			reg = < 0x00 0xfff80000 0x00 0x12000 >;
279			phandle = < 0x10 >;
280		};
281
282		ao_ctrl@f7800000 {
283			compatible = "hisilicon,hi6220-aoctrl\0syscon";
284			reg = < 0x00 0xf7800000 0x00 0x2000 >;
285			#clock-cells = < 0x01 >;
286			phandle = < 0x12 >;
287		};
288
289		sys_ctrl@f7030000 {
290			compatible = "hisilicon,hi6220-sysctrl\0syscon";
291			reg = < 0x00 0xf7030000 0x00 0x2000 >;
292			#clock-cells = < 0x01 >;
293			#reset-cells = < 0x01 >;
294			phandle = < 0x13 >;
295		};
296
297		media_ctrl@f4410000 {
298			compatible = "hisilicon,hi6220-mediactrl\0syscon";
299			reg = < 0x00 0xf4410000 0x00 0x1000 >;
300			#clock-cells = < 0x01 >;
301			#reset-cells = < 0x01 >;
302			phandle = < 0x54 >;
303		};
304
305		pm_ctrl@f7032000 {
306			compatible = "hisilicon,hi6220-pmctrl\0syscon";
307			reg = < 0x00 0xf7032000 0x00 0x1000 >;
308			#clock-cells = < 0x01 >;
309		};
310
311		acpu_sctrl@f6504000 {
312			compatible = "hisilicon,hi6220-acpu-sctrl\0syscon";
313			reg = < 0x00 0xf6504000 0x00 0x1000 >;
314			#clock-cells = < 0x01 >;
315			phandle = < 0x58 >;
316		};
317
318		medianoc_ade@f4520000 {
319			compatible = "syscon";
320			reg = < 0x00 0xf4520000 0x00 0x4000 >;
321			phandle = < 0x53 >;
322		};
323
324		stub_clock {
325			compatible = "hisilicon,hi6220-stub-clk";
326			hisilicon,hi6220-clk-sram = < 0x10 >;
327			#clock-cells = < 0x01 >;
328			mbox-names = "mbox-tx";
329			mboxes = < 0x11 0x01 0x00 0x0b >;
330			phandle = < 0x0b >;
331		};
332
333		uart@f8015000 {
334			compatible = "arm,pl011\0arm,primecell";
335			reg = < 0x00 0xf8015000 0x00 0x1000 >;
336			interrupts = < 0x00 0x24 0x04 >;
337			clocks = < 0x12 0x24 0x12 0x24 >;
338			clock-names = "uartclk\0apb_pclk";
339		};
340
341		uart@f7111000 {
342			compatible = "arm,pl011\0arm,primecell";
343			reg = < 0x00 0xf7111000 0x00 0x1000 >;
344			interrupts = < 0x00 0x25 0x04 >;
345			clocks = < 0x13 0x11 0x13 0x11 >;
346			clock-names = "uartclk\0apb_pclk";
347			pinctrl-names = "default";
348			pinctrl-0 = < 0x14 0x15 0x16 >;
349			status = "ok";
350			assigned-clocks = < 0x13 0x29 >;
351			assigned-clock-rates = < 0x8f0d180 >;
352
353			bluetooth {
354				compatible = "ti,wl1835-st";
355				enable-gpios = < 0x17 0x07 0x00 >;
356				clocks = < 0x18 >;
357				clock-names = "ext_clock";
358			};
359		};
360
361		uart@f7112000 {
362			compatible = "arm,pl011\0arm,primecell";
363			reg = < 0x00 0xf7112000 0x00 0x1000 >;
364			interrupts = < 0x00 0x26 0x04 >;
365			clocks = < 0x13 0x12 0x13 0x12 >;
366			clock-names = "uartclk\0apb_pclk";
367			pinctrl-names = "default";
368			pinctrl-0 = < 0x19 0x1a >;
369			status = "ok";
370			label = "LS-UART0";
371		};
372
373		uart@f7113000 {
374			compatible = "arm,pl011\0arm,primecell";
375			reg = < 0x00 0xf7113000 0x00 0x1000 >;
376			interrupts = < 0x00 0x27 0x04 >;
377			clocks = < 0x13 0x13 0x13 0x13 >;
378			clock-names = "uartclk\0apb_pclk";
379			pinctrl-names = "default";
380			pinctrl-0 = < 0x1b 0x1c >;
381			status = "ok";
382			label = "LS-UART1";
383		};
384
385		uart@f7114000 {
386			compatible = "arm,pl011\0arm,primecell";
387			reg = < 0x00 0xf7114000 0x00 0x1000 >;
388			interrupts = < 0x00 0x28 0x04 >;
389			clocks = < 0x13 0x14 0x13 0x14 >;
390			clock-names = "uartclk\0apb_pclk";
391			pinctrl-names = "default";
392			pinctrl-0 = < 0x1d 0x1e >;
393			status = "disabled";
394		};
395
396		dma@f7370000 {
397			compatible = "hisilicon,k3-dma-1.0";
398			reg = < 0x00 0xf7370000 0x00 0x1000 >;
399			#dma-cells = < 0x01 >;
400			dma-channels = < 0x0f >;
401			dma-requests = < 0x20 >;
402			interrupts = < 0x00 0x54 0x04 >;
403			clocks = < 0x13 0x0b >;
404			dma-no-cci;
405			dma-type = "hi6220_dma";
406			status = "ok";
407			phandle = < 0x4f >;
408		};
409
410		timer@f8008000 {
411			compatible = "arm,sp804\0arm,primecell";
412			reg = < 0x00 0xf8008000 0x00 0x1000 >;
413			interrupts = < 0x00 0x0e 0x04 0x00 0x0f 0x04 >;
414			clocks = < 0x12 0x1b 0x12 0x1b 0x12 0x1b >;
415			clock-names = "timer1\0timer2\0apb_pclk";
416		};
417
418		rtc@f8003000 {
419			compatible = "arm,pl031\0arm,primecell";
420			reg = < 0x00 0xf8003000 0x00 0x1000 >;
421			interrupts = < 0x00 0x0c 0x04 >;
422			clocks = < 0x12 0x25 >;
423			clock-names = "apb_pclk";
424		};
425
426		rtc@f8004000 {
427			compatible = "arm,pl031\0arm,primecell";
428			reg = < 0x00 0xf8004000 0x00 0x1000 >;
429			interrupts = < 0x00 0x08 0x04 >;
430			clocks = < 0x12 0x26 >;
431			clock-names = "apb_pclk";
432		};
433
434		pinmux@f7010000 {
435			compatible = "pinctrl-single";
436			reg = < 0x00 0xf7010000 0x00 0x27c >;
437			#address-cells = < 0x01 >;
438			#size-cells = < 0x01 >;
439			#pinctrl-cells = < 0x01 >;
440			#gpio-range-cells = < 0x03 >;
441			pinctrl-single,register-width = < 0x20 >;
442			pinctrl-single,function-mask = < 0x07 >;
443			pinctrl-single,gpio-range = < 0x1f 0x50 0x08 0x00 0x1f 0x58 0x08 0x00 0x1f 0x60 0x08 0x00 0x1f 0x68 0x08 0x00 0x1f 0x70 0x08 0x00 0x1f 0x78 0x02 0x00 0x1f 0x02 0x06 0x01 0x1f 0x08 0x08 0x01 0x1f 0x00 0x01 0x01 0x1f 0x10 0x07 0x01 0x1f 0x17 0x03 0x01 0x1f 0x1c 0x05 0x01 0x1f 0x21 0x03 0x01 0x1f 0x2b 0x05 0x01 0x1f 0x30 0x08 0x01 0x1f 0x38 0x08 0x01 0x1f 0x4a 0x06 0x01 0x1f 0x7a 0x01 0x01 0x1f 0x7e 0x01 0x01 0x1f 0x7f 0x08 0x01 0x1f 0x87 0x08 0x01 0x1f 0x8f 0x08 0x01 0x1f 0x97 0x08 0x01 >;
444			pinctrl-names = "default";
445			pinctrl-0 = < 0x20 0x21 0x22 0x23 0x24 >;
446			phandle = < 0x2b >;
447
448			gpio-range {
449				#pinctrl-single,gpio-range-cells = < 0x03 >;
450				phandle = < 0x1f >;
451			};
452
453			boot_sel_pmx_func {
454				pinctrl-single,pins = < 0x00 0x00 >;
455				phandle = < 0x20 >;
456			};
457
458			emmc_pmx_func {
459				pinctrl-single,pins = < 0x100 0x00 0x104 0x00 0x108 0x00 0x10c 0x00 0x110 0x00 0x114 0x00 0x118 0x00 0x11c 0x00 0x120 0x00 0x124 0x00 >;
460				phandle = < 0x3a >;
461			};
462
463			sd_pmx_func {
464				pinctrl-single,pins = < 0x0c 0x00 0x10 0x00 0x14 0x00 0x18 0x00 0x1c 0x00 0x20 0x00 >;
465				phandle = < 0x3f >;
466			};
467
468			sd_pmx_idle {
469				pinctrl-single,pins = < 0x0c 0x01 0x10 0x01 0x14 0x01 0x18 0x01 0x1c 0x01 0x20 0x01 >;
470				phandle = < 0x42 >;
471			};
472
473			sdio_pmx_func {
474				pinctrl-single,pins = < 0x128 0x00 0x12c 0x00 0x130 0x00 0x134 0x00 0x138 0x00 0x13c 0x00 >;
475				phandle = < 0x47 >;
476			};
477
478			sdio_pmx_idle {
479				pinctrl-single,pins = < 0x128 0x01 0x12c 0x01 0x130 0x01 0x134 0x01 0x138 0x01 0x13c 0x01 >;
480				phandle = < 0x4a >;
481			};
482
483			isp_pmx_func {
484				pinctrl-single,pins = < 0x24 0x00 0x28 0x00 0x2c 0x00 0x30 0x01 0x34 0x01 0x38 0x01 0x3c 0x00 0x40 0x00 0x44 0x00 0x48 0x00 0x4c 0x01 0x50 0x01 0x54 0x00 0x58 0x00 0x5c 0x00 0x60 0x00 >;
485			};
486
487			hkadc_ssi_pmx_func {
488				pinctrl-single,pins = < 0x68 0x00 >;
489				phandle = < 0x21 >;
490			};
491
492			codec_clk_pmx_func {
493				pinctrl-single,pins = < 0x6c 0x00 >;
494				phandle = < 0x22 >;
495			};
496
497			codec_pmx_func {
498				pinctrl-single,pins = < 0x70 0x01 0x74 0x00 0x78 0x00 0x7c 0x00 >;
499			};
500
501			fm_pmx_func {
502				pinctrl-single,pins = < 0x80 0x01 0x84 0x01 0x88 0x01 0x8c 0x01 >;
503			};
504
505			bt_pmx_func {
506				pinctrl-single,pins = < 0x90 0x00 0x94 0x00 0x98 0x00 0x9c 0x00 >;
507			};
508
509			pwm_in_pmx_func {
510				pinctrl-single,pins = < 0xb8 0x01 >;
511				phandle = < 0x23 >;
512			};
513
514			bl_pwm_pmx_func {
515				pinctrl-single,pins = < 0xbc 0x01 >;
516				phandle = < 0x24 >;
517			};
518
519			uart0_pmx_func {
520				pinctrl-single,pins = < 0xc0 0x00 0xc4 0x00 >;
521			};
522
523			uart1_pmx_func {
524				pinctrl-single,pins = < 0xc8 0x00 0xcc 0x00 0xd0 0x00 0xd4 0x00 >;
525				phandle = < 0x14 >;
526			};
527
528			uart2_pmx_func {
529				pinctrl-single,pins = < 0xd8 0x00 0xdc 0x00 0xe0 0x00 0xe4 0x00 >;
530				phandle = < 0x19 >;
531			};
532
533			uart3_pmx_func {
534				pinctrl-single,pins = < 0x180 0x01 0x184 0x01 0x188 0x01 0x18c 0x01 >;
535				phandle = < 0x1b >;
536			};
537
538			uart4_pmx_func {
539				pinctrl-single,pins = < 0x1d0 0x01 0x1d4 0x01 0x1d8 0x01 0x1dc 0x01 >;
540				phandle = < 0x1d >;
541			};
542
543			uart5_pmx_func {
544				pinctrl-single,pins = < 0x1c8 0x01 0x1cc 0x01 >;
545			};
546
547			i2c0_pmx_func {
548				pinctrl-single,pins = < 0xe8 0x00 0xec 0x00 >;
549				phandle = < 0x2f >;
550			};
551
552			i2c1_pmx_func {
553				pinctrl-single,pins = < 0xf0 0x00 0xf4 0x00 >;
554				phandle = < 0x31 >;
555			};
556
557			i2c2_pmx_func {
558				pinctrl-single,pins = < 0xf8 0x00 0xfc 0x00 >;
559				phandle = < 0x33 >;
560			};
561
562			spi0_pmx_func {
563				pinctrl-single,pins = < 0x1a0 0x01 0x1a4 0x01 0x1a8 0x01 0x1ac 0x01 >;
564				phandle = < 0x2c >;
565			};
566		};
567
568		pinmux@f7010800 {
569			compatible = "pinconf-single";
570			reg = < 0x00 0xf7010800 0x00 0x28c >;
571			#address-cells = < 0x01 >;
572			#size-cells = < 0x01 >;
573			#pinctrl-cells = < 0x01 >;
574			pinctrl-single,register-width = < 0x20 >;
575			pinctrl-names = "default";
576			pinctrl-0 = < 0x25 0x26 0x27 0x28 0x29 >;
577
578			boot_sel_cfg_func {
579				pinctrl-single,pins = < 0x00 0x00 >;
580				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
581				pinctrl-single,bias-pullup = < 0x01 0x01 0x00 0x01 >;
582				pinctrl-single,drive-strength = < 0x00 0x70 >;
583				phandle = < 0x25 >;
584			};
585
586			hkadc_ssi_cfg_func {
587				pinctrl-single,pins = < 0x6c 0x00 >;
588				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
589				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
590				pinctrl-single,drive-strength = < 0x00 0x70 >;
591				phandle = < 0x26 >;
592			};
593
594			emmc_clk_cfg_func {
595				pinctrl-single,pins = < 0x104 0x00 >;
596				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
597				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
598				pinctrl-single,drive-strength = < 0x20 0x70 >;
599				phandle = < 0x3b >;
600			};
601
602			emmc_cfg_func {
603				pinctrl-single,pins = < 0x108 0x00 0x10c 0x00 0x110 0x00 0x114 0x00 0x118 0x00 0x11c 0x00 0x120 0x00 0x124 0x00 0x128 0x00 >;
604				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
605				pinctrl-single,bias-pullup = < 0x01 0x01 0x00 0x01 >;
606				pinctrl-single,drive-strength = < 0x10 0x70 >;
607				phandle = < 0x3c >;
608			};
609
610			emmc_rst_cfg_func {
611				pinctrl-single,pins = < 0x12c 0x00 >;
612				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
613				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
614				pinctrl-single,drive-strength = < 0x10 0x70 >;
615				phandle = < 0x3d >;
616			};
617
618			sd_clk_cfg_func {
619				pinctrl-single,pins = < 0x0c 0x00 >;
620				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
621				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
622				pinctrl-single,drive-strength = < 0x30 0x70 >;
623				phandle = < 0x40 >;
624			};
625
626			sd_clk_cfg_idle {
627				pinctrl-single,pins = < 0x0c 0x00 >;
628				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
629				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
630				pinctrl-single,drive-strength = < 0x00 0x70 >;
631				phandle = < 0x43 >;
632			};
633
634			sd_cfg_func {
635				pinctrl-single,pins = < 0x10 0x00 0x14 0x00 0x18 0x00 0x1c 0x00 0x20 0x00 >;
636				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
637				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
638				pinctrl-single,drive-strength = < 0x20 0x70 >;
639				phandle = < 0x41 >;
640			};
641
642			sd_cfg_idle {
643				pinctrl-single,pins = < 0x10 0x00 0x14 0x00 0x18 0x00 0x1c 0x00 0x20 0x00 >;
644				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
645				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
646				pinctrl-single,drive-strength = < 0x00 0x70 >;
647				phandle = < 0x44 >;
648			};
649
650			sdio_clk_cfg_func {
651				pinctrl-single,pins = < 0x134 0x00 >;
652				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
653				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
654				pinctrl-single,drive-strength = < 0x20 0x70 >;
655				phandle = < 0x48 >;
656			};
657
658			sdio_clk_cfg_idle {
659				pinctrl-single,pins = < 0x134 0x00 >;
660				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
661				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
662				pinctrl-single,drive-strength = < 0x00 0x70 >;
663				phandle = < 0x4b >;
664			};
665
666			sdio_cfg_func {
667				pinctrl-single,pins = < 0x138 0x00 0x13c 0x00 0x140 0x00 0x144 0x00 0x148 0x00 >;
668				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
669				pinctrl-single,bias-pullup = < 0x01 0x01 0x00 0x01 >;
670				pinctrl-single,drive-strength = < 0x10 0x70 >;
671				phandle = < 0x49 >;
672			};
673
674			sdio_cfg_idle {
675				pinctrl-single,pins = < 0x138 0x00 0x13c 0x00 0x140 0x00 0x144 0x00 0x148 0x00 >;
676				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
677				pinctrl-single,bias-pullup = < 0x01 0x01 0x00 0x01 >;
678				pinctrl-single,drive-strength = < 0x00 0x70 >;
679				phandle = < 0x4c >;
680			};
681
682			isp_cfg_func1 {
683				pinctrl-single,pins = < 0x28 0x00 0x2c 0x00 0x30 0x00 0x34 0x00 0x38 0x00 0x3c 0x00 0x40 0x00 0x44 0x00 0x48 0x00 0x4c 0x00 0x50 0x00 0x58 0x00 0x5c 0x00 0x60 0x00 0x64 0x00 >;
684				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
685				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
686				pinctrl-single,drive-strength = < 0x00 0x70 >;
687			};
688
689			isp_cfg_idle1 {
690				pinctrl-single,pins = < 0x34 0x00 0x38 0x00 >;
691				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
692				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
693				pinctrl-single,drive-strength = < 0x00 0x70 >;
694			};
695
696			isp_cfg_func2 {
697				pinctrl-single,pins = < 0x54 0x00 >;
698				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
699				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
700				pinctrl-single,drive-strength = < 0x00 0x70 >;
701			};
702
703			codec_clk_cfg_func {
704				pinctrl-single,pins = < 0x70 0x00 >;
705				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
706				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
707				pinctrl-single,drive-strength = < 0x10 0x70 >;
708				phandle = < 0x27 >;
709			};
710
711			codec_clk_cfg_idle {
712				pinctrl-single,pins = < 0x70 0x00 >;
713				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
714				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
715				pinctrl-single,drive-strength = < 0x00 0x70 >;
716			};
717
718			codec_cfg_func1 {
719				pinctrl-single,pins = < 0x74 0x00 >;
720				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
721				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
722				pinctrl-single,drive-strength = < 0x00 0x70 >;
723			};
724
725			codec_cfg_func2 {
726				pinctrl-single,pins = < 0x78 0x00 0x7c 0x00 0x80 0x00 >;
727				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
728				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
729				pinctrl-single,drive-strength = < 0x10 0x70 >;
730			};
731
732			codec_cfg_idle2 {
733				pinctrl-single,pins = < 0x78 0x00 0x7c 0x00 0x80 0x00 >;
734				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
735				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
736				pinctrl-single,drive-strength = < 0x00 0x70 >;
737			};
738
739			fm_cfg_func {
740				pinctrl-single,pins = < 0x84 0x00 0x88 0x00 0x8c 0x00 0x90 0x00 >;
741				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
742				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
743				pinctrl-single,drive-strength = < 0x00 0x70 >;
744			};
745
746			bt_cfg_func {
747				pinctrl-single,pins = < 0x94 0x00 0x98 0x00 0x9c 0x00 0xa0 0x00 >;
748				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
749				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
750				pinctrl-single,drive-strength = < 0x00 0x70 >;
751			};
752
753			bt_cfg_idle {
754				pinctrl-single,pins = < 0x94 0x00 0x98 0x00 0x9c 0x00 0xa0 0x00 >;
755				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
756				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
757				pinctrl-single,drive-strength = < 0x00 0x70 >;
758			};
759
760			pwm_in_cfg_func {
761				pinctrl-single,pins = < 0xbc 0x00 >;
762				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
763				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
764				pinctrl-single,drive-strength = < 0x00 0x70 >;
765				phandle = < 0x28 >;
766			};
767
768			bl_pwm_cfg_func {
769				pinctrl-single,pins = < 0xc0 0x00 >;
770				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
771				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
772				pinctrl-single,drive-strength = < 0x00 0x70 >;
773				phandle = < 0x29 >;
774			};
775
776			uart0_cfg_func1 {
777				pinctrl-single,pins = < 0xc4 0x00 >;
778				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
779				pinctrl-single,bias-pullup = < 0x01 0x01 0x00 0x01 >;
780				pinctrl-single,drive-strength = < 0x00 0x70 >;
781			};
782
783			uart0_cfg_func2 {
784				pinctrl-single,pins = < 0xc8 0x00 >;
785				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
786				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
787				pinctrl-single,drive-strength = < 0x10 0x70 >;
788			};
789
790			uart1_cfg_func1 {
791				pinctrl-single,pins = < 0xcc 0x00 0xd4 0x00 >;
792				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
793				pinctrl-single,bias-pullup = < 0x01 0x01 0x00 0x01 >;
794				pinctrl-single,drive-strength = < 0x00 0x70 >;
795				phandle = < 0x15 >;
796			};
797
798			uart1_cfg_func2 {
799				pinctrl-single,pins = < 0xd0 0x00 0xd8 0x00 >;
800				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
801				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
802				pinctrl-single,drive-strength = < 0x00 0x70 >;
803				phandle = < 0x16 >;
804			};
805
806			uart2_cfg_func {
807				pinctrl-single,pins = < 0xdc 0x00 0xe0 0x00 0xe4 0x00 0xe8 0x00 >;
808				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
809				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
810				pinctrl-single,drive-strength = < 0x00 0x70 >;
811				phandle = < 0x1a >;
812			};
813
814			uart3_cfg_func {
815				pinctrl-single,pins = < 0x190 0x00 0x194 0x00 0x198 0x00 0x19c 0x00 >;
816				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
817				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
818				pinctrl-single,drive-strength = < 0x00 0x70 >;
819				phandle = < 0x1c >;
820			};
821
822			uart4_cfg_func {
823				pinctrl-single,pins = < 0x1e0 0x00 0x1e4 0x00 0x1e8 0x00 0x1ec 0x00 >;
824				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
825				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
826				pinctrl-single,drive-strength = < 0x00 0x70 >;
827				phandle = < 0x1e >;
828			};
829
830			uart5_cfg_func {
831				pinctrl-single,pins = < 0x1d8 0x00 0x1dc 0x00 >;
832				pinctrl-single,bias-pulldown = < 0x02 0x02 0x00 0x02 >;
833				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
834				pinctrl-single,drive-strength = < 0x00 0x70 >;
835			};
836
837			i2c0_cfg_func {
838				pinctrl-single,pins = < 0xec 0x00 0xf0 0x00 >;
839				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
840				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
841				pinctrl-single,drive-strength = < 0x00 0x70 >;
842				phandle = < 0x30 >;
843			};
844
845			i2c1_cfg_func {
846				pinctrl-single,pins = < 0xf4 0x00 0xf8 0x00 >;
847				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
848				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
849				pinctrl-single,drive-strength = < 0x00 0x70 >;
850				phandle = < 0x32 >;
851			};
852
853			i2c2_cfg_func {
854				pinctrl-single,pins = < 0xfc 0x00 0x100 0x00 >;
855				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
856				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
857				pinctrl-single,drive-strength = < 0x00 0x70 >;
858				phandle = < 0x34 >;
859			};
860
861			spi0_cfg_func {
862				pinctrl-single,pins = < 0x1b0 0x00 0x1b4 0x00 0x1b8 0x00 0x1bc 0x00 >;
863				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
864				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
865				pinctrl-single,drive-strength = < 0x00 0x70 >;
866				phandle = < 0x2d >;
867			};
868		};
869
870		pinmux@f8001800 {
871			compatible = "pinconf-single";
872			reg = < 0x00 0xf8001800 0x00 0x78 >;
873			#address-cells = < 0x01 >;
874			#size-cells = < 0x01 >;
875			#pinctrl-cells = < 0x01 >;
876			pinctrl-single,register-width = < 0x20 >;
877			pinctrl-names = "default";
878			pinctrl-0 = < 0x2a >;
879
880			rstout_n_cfg_func {
881				pinctrl-single,pins = < 0x00 0x00 >;
882				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
883				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
884				pinctrl-single,drive-strength = < 0x00 0x70 >;
885				phandle = < 0x2a >;
886			};
887
888			pmu_peri_en_cfg_func {
889				pinctrl-single,pins = < 0x04 0x00 >;
890				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
891				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
892				pinctrl-single,drive-strength = < 0x00 0x70 >;
893			};
894
895			sysclk0_en_cfg_func {
896				pinctrl-single,pins = < 0x08 0x00 >;
897				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
898				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
899				pinctrl-single,drive-strength = < 0x00 0x70 >;
900			};
901
902			jtag_tdo_cfg_func {
903				pinctrl-single,pins = < 0x0c 0x00 >;
904				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
905				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
906				pinctrl-single,drive-strength = < 0x20 0x70 >;
907			};
908
909			rf_reset_cfg_func {
910				pinctrl-single,pins = < 0x70 0x00 0x74 0x00 >;
911				pinctrl-single,bias-pulldown = < 0x00 0x02 0x00 0x02 >;
912				pinctrl-single,bias-pullup = < 0x00 0x01 0x00 0x01 >;
913				pinctrl-single,drive-strength = < 0x00 0x70 >;
914			};
915		};
916
917		gpio@f8011000 {
918			compatible = "arm,pl061\0arm,primecell";
919			reg = < 0x00 0xf8011000 0x00 0x1000 >;
920			interrupts = < 0x00 0x34 0x04 >;
921			gpio-controller;
922			#gpio-cells = < 0x02 >;
923			interrupt-controller;
924			#interrupt-cells = < 0x02 >;
925			clocks = < 0x12 0x02 >;
926			clock-names = "apb_pclk";
927			gpio-line-names = "PWR_HOLD\0DSI_SEL\0USB_HUB_RESET_N\0USB_SEL\0HDMI_PD\0WL_REG_ON\0PWRON_DET\05V_HUB_EN";
928			phandle = < 0x35 >;
929		};
930
931		gpio@f8012000 {
932			compatible = "arm,pl061\0arm,primecell";
933			reg = < 0x00 0xf8012000 0x00 0x1000 >;
934			interrupts = < 0x00 0x35 0x04 >;
935			gpio-controller;
936			#gpio-cells = < 0x02 >;
937			interrupt-controller;
938			#interrupt-cells = < 0x02 >;
939			clocks = < 0x12 0x02 >;
940			clock-names = "apb_pclk";
941			gpio-line-names = "SD_DET\0HDMI_INT\0PMU_IRQ_N\0WL_HOST_WAKE\0NC\0NC\0NC\0BT_REG_ON";
942			phandle = < 0x17 >;
943		};
944
945		gpio@f8013000 {
946			compatible = "arm,pl061\0arm,primecell";
947			reg = < 0x00 0xf8013000 0x00 0x1000 >;
948			interrupts = < 0x00 0x36 0x04 >;
949			gpio-controller;
950			#gpio-cells = < 0x02 >;
951			interrupt-controller;
952			#interrupt-cells = < 0x02 >;
953			clocks = < 0x12 0x02 >;
954			clock-names = "apb_pclk";
955			gpio-line-names = "GPIO-A\0GPIO-B\0GPIO-C\0GPIO-D\0GPIO-E\0USB_ID_DET\0USB_VBUS_DET\0GPIO-H";
956		};
957
958		gpio@f8014000 {
959			compatible = "arm,pl061\0arm,primecell";
960			reg = < 0x00 0xf8014000 0x00 0x1000 >;
961			interrupts = < 0x00 0x37 0x04 >;
962			gpio-controller;
963			#gpio-cells = < 0x02 >;
964			gpio-ranges = < 0x2b 0x00 0x50 0x08 >;
965			interrupt-controller;
966			#interrupt-cells = < 0x02 >;
967			clocks = < 0x12 0x02 >;
968			clock-names = "apb_pclk";
969			gpio-line-names = "GPIO3_0\0NC\0NC\0\0NC\0\0WLAN_ACTIVE\0NC\0NC";
970			phandle = < 0x75 >;
971		};
972
973		gpio@f7020000 {
974			compatible = "arm,pl061\0arm,primecell";
975			reg = < 0x00 0xf7020000 0x00 0x1000 >;
976			interrupts = < 0x00 0x38 0x04 >;
977			gpio-controller;
978			#gpio-cells = < 0x02 >;
979			gpio-ranges = < 0x2b 0x00 0x58 0x08 >;
980			interrupt-controller;
981			#interrupt-cells = < 0x02 >;
982			clocks = < 0x12 0x02 >;
983			clock-names = "apb_pclk";
984			gpio-line-names = "USER_LED1\0USER_LED2\0USER_LED3\0USER_LED4\0SD_SEL\0NC\0NC\0BT_ACTIVE";
985			phandle = < 0x74 >;
986		};
987
988		gpio@f7021000 {
989			compatible = "arm,pl061\0arm,primecell";
990			reg = < 0x00 0xf7021000 0x00 0x1000 >;
991			interrupts = < 0x00 0x39 0x04 >;
992			gpio-controller;
993			#gpio-cells = < 0x02 >;
994			gpio-ranges = < 0x2b 0x00 0x60 0x08 >;
995			interrupt-controller;
996			#interrupt-cells = < 0x02 >;
997			clocks = < 0x12 0x02 >;
998			clock-names = "apb_pclk";
999			gpio-line-names = "NC\0NC\0[UART1_RxD]\0[UART1_TxD]\0[AUX_SSI1]\0NC\0[PCM_CLK]\0[PCM_FS]";
1000		};
1001
1002		gpio@f7022000 {
1003			compatible = "arm,pl061\0arm,primecell";
1004			reg = < 0x00 0xf7022000 0x00 0x1000 >;
1005			interrupts = < 0x00 0x3a 0x04 >;
1006			gpio-controller;
1007			#gpio-cells = < 0x02 >;
1008			gpio-ranges = < 0x2b 0x00 0x68 0x08 >;
1009			interrupt-controller;
1010			#interrupt-cells = < 0x02 >;
1011			clocks = < 0x12 0x02 >;
1012			clock-names = "apb_pclk";
1013			gpio-line-names = "[SPI0_DIN]\0[SPI0_DOUT]\0[SPI0_CS]\0[SPI0_SCLK]\0NC\0NC\0NC\0GPIO-G";
1014			phandle = < 0x2e >;
1015		};
1016
1017		gpio@f7023000 {
1018			compatible = "arm,pl061\0arm,primecell";
1019			reg = < 0x00 0xf7023000 0x00 0x1000 >;
1020			interrupts = < 0x00 0x3b 0x04 >;
1021			gpio-controller;
1022			#gpio-cells = < 0x02 >;
1023			gpio-ranges = < 0x2b 0x00 0x70 0x08 >;
1024			interrupt-controller;
1025			#interrupt-cells = < 0x02 >;
1026			clocks = < 0x12 0x02 >;
1027			clock-names = "apb_pclk";
1028			gpio-line-names = "NC\0NC\0NC\0NC\0[PCM_DI]\0[PCM_DO]\0NC\0NC";
1029		};
1030
1031		gpio@f7024000 {
1032			compatible = "arm,pl061\0arm,primecell";
1033			reg = < 0x00 0xf7024000 0x00 0x1000 >;
1034			interrupts = < 0x00 0x3c 0x04 >;
1035			gpio-controller;
1036			#gpio-cells = < 0x02 >;
1037			gpio-ranges = < 0x2b 0x00 0x78 0x02 0x2b 0x02 0x02 0x06 >;
1038			interrupt-controller;
1039			#interrupt-cells = < 0x02 >;
1040			clocks = < 0x12 0x02 >;
1041			clock-names = "apb_pclk";
1042			gpio-line-names = "NC\0[CEC_CLK_19_2MHZ]\0NC\0\0\0\0\0\0";
1043		};
1044
1045		gpio@f7025000 {
1046			compatible = "arm,pl061\0arm,primecell";
1047			reg = < 0x00 0xf7025000 0x00 0x1000 >;
1048			interrupts = < 0x00 0x3d 0x04 >;
1049			gpio-controller;
1050			#gpio-cells = < 0x02 >;
1051			gpio-ranges = < 0x2b 0x00 0x08 0x08 >;
1052			interrupt-controller;
1053			#interrupt-cells = < 0x02 >;
1054			clocks = < 0x12 0x02 >;
1055			clock-names = "apb_pclk";
1056			gpio-line-names = "\0GPIO-J\0GPIO-L\0NC\0NC\0NC\0NC\0[ISP_CCLK0]";
1057		};
1058
1059		gpio@f7026000 {
1060			compatible = "arm,pl061\0arm,primecell";
1061			reg = < 0x00 0xf7026000 0x00 0x1000 >;
1062			interrupts = < 0x00 0x3e 0x04 >;
1063			gpio-controller;
1064			#gpio-cells = < 0x02 >;
1065			gpio-ranges = < 0x2b 0x00 0x00 0x01 0x2b 0x01 0x10 0x07 >;
1066			interrupt-controller;
1067			#interrupt-cells = < 0x02 >;
1068			clocks = < 0x12 0x02 >;
1069			clock-names = "apb_pclk";
1070			gpio-line-names = "BOOT_SEL\0[ISP_CCLK1]\0GPIO-I\0GPIO-K\0NC\0NC\0[I2C2_SDA]\0[I2C2_SCL]";
1071		};
1072
1073		gpio@f7027000 {
1074			compatible = "arm,pl061\0arm,primecell";
1075			reg = < 0x00 0xf7027000 0x00 0x1000 >;
1076			interrupts = < 0x00 0x3f 0x04 >;
1077			gpio-controller;
1078			#gpio-cells = < 0x02 >;
1079			gpio-ranges = < 0x2b 0x00 0x17 0x03 0x2b 0x03 0x1c 0x05 >;
1080			interrupt-controller;
1081			#interrupt-cells = < 0x02 >;
1082			clocks = < 0x12 0x02 >;
1083			clock-names = "apb_pclk";
1084			gpio-line-names = "[I2C3_SDA]\0[I2C3_SCL]\0\0NC\0NC\0NC\0\0";
1085		};
1086
1087		gpio@f7028000 {
1088			compatible = "arm,pl061\0arm,primecell";
1089			reg = < 0x00 0xf7028000 0x00 0x1000 >;
1090			interrupts = < 0x00 0x40 0x04 >;
1091			gpio-controller;
1092			#gpio-cells = < 0x02 >;
1093			gpio-ranges = < 0x2b 0x00 0x21 0x03 0x2b 0x03 0x2b 0x05 >;
1094			interrupt-controller;
1095			#interrupt-cells = < 0x02 >;
1096			clocks = < 0x12 0x02 >;
1097			clock-names = "apb_pclk";
1098			gpio-line-names = "[BT_PCM_XFS]\0[BT_PCM_DI]\0[BT_PCM_DO]\0NC\0NC\0NC\0NC\0GPIO-F";
1099		};
1100
1101		gpio@f7029000 {
1102			compatible = "arm,pl061\0arm,primecell";
1103			reg = < 0x00 0xf7029000 0x00 0x1000 >;
1104			interrupts = < 0x00 0x41 0x04 >;
1105			gpio-controller;
1106			#gpio-cells = < 0x02 >;
1107			gpio-ranges = < 0x2b 0x00 0x30 0x08 >;
1108			interrupt-controller;
1109			#interrupt-cells = < 0x02 >;
1110			clocks = < 0x12 0x02 >;
1111			clock-names = "apb_pclk";
1112			gpio-line-names = "[UART0_RX]\0[UART0_TX]\0[BT_UART1_CTS]\0[BT_UART1_RTS]\0[BT_UART1_RX]\0[BT_UART1_TX]\0[UART0_CTS]\0[UART0_RTS]";
1113		};
1114
1115		gpio@f702a000 {
1116			compatible = "arm,pl061\0arm,primecell";
1117			reg = < 0x00 0xf702a000 0x00 0x1000 >;
1118			interrupts = < 0x00 0x42 0x04 >;
1119			gpio-controller;
1120			#gpio-cells = < 0x02 >;
1121			gpio-ranges = < 0x2b 0x00 0x38 0x08 >;
1122			interrupt-controller;
1123			#interrupt-cells = < 0x02 >;
1124			clocks = < 0x12 0x02 >;
1125			clock-names = "apb_pclk";
1126			gpio-line-names = "[UART0_RxD]\0[UART0_TxD]\0[I2C0_SCL]\0[I2C0_SDA]\0[I2C1_SCL]\0[I2C1_SDA]\0[I2C2_SCL]\0[I2C2_SDA]";
1127		};
1128
1129		gpio@f702b000 {
1130			compatible = "arm,pl061\0arm,primecell";
1131			reg = < 0x00 0xf702b000 0x00 0x1000 >;
1132			interrupts = < 0x00 0x43 0x04 >;
1133			gpio-controller;
1134			#gpio-cells = < 0x02 >;
1135			gpio-ranges = < 0x2b 0x00 0x4a 0x06 0x2b 0x06 0x7a 0x01 0x2b 0x07 0x7e 0x01 >;
1136			interrupt-controller;
1137			#interrupt-cells = < 0x02 >;
1138			clocks = < 0x12 0x02 >;
1139			clock-names = "apb_pclk";
1140			gpio-line-names = [ 00 00 00 00 00 00 4e 43 00 00 ];
1141		};
1142
1143		gpio@f702c000 {
1144			compatible = "arm,pl061\0arm,primecell";
1145			reg = < 0x00 0xf702c000 0x00 0x1000 >;
1146			interrupts = < 0x00 0x44 0x04 >;
1147			gpio-controller;
1148			#gpio-cells = < 0x02 >;
1149			gpio-ranges = < 0x2b 0x00 0x7f 0x08 >;
1150			interrupt-controller;
1151			#interrupt-cells = < 0x02 >;
1152			clocks = < 0x12 0x02 >;
1153			clock-names = "apb_pclk";
1154		};
1155
1156		gpio@f702d000 {
1157			compatible = "arm,pl061\0arm,primecell";
1158			reg = < 0x00 0xf702d000 0x00 0x1000 >;
1159			interrupts = < 0x00 0x45 0x04 >;
1160			gpio-controller;
1161			#gpio-cells = < 0x02 >;
1162			gpio-ranges = < 0x2b 0x00 0x87 0x08 >;
1163			interrupt-controller;
1164			#interrupt-cells = < 0x02 >;
1165			clocks = < 0x12 0x02 >;
1166			clock-names = "apb_pclk";
1167		};
1168
1169		gpio@f702e000 {
1170			compatible = "arm,pl061\0arm,primecell";
1171			reg = < 0x00 0xf702e000 0x00 0x1000 >;
1172			interrupts = < 0x00 0x46 0x04 >;
1173			gpio-controller;
1174			#gpio-cells = < 0x02 >;
1175			gpio-ranges = < 0x2b 0x00 0x8f 0x08 >;
1176			interrupt-controller;
1177			#interrupt-cells = < 0x02 >;
1178			clocks = < 0x12 0x02 >;
1179			clock-names = "apb_pclk";
1180		};
1181
1182		gpio@f702f000 {
1183			compatible = "arm,pl061\0arm,primecell";
1184			reg = < 0x00 0xf702f000 0x00 0x1000 >;
1185			interrupts = < 0x00 0x47 0x04 >;
1186			gpio-controller;
1187			#gpio-cells = < 0x02 >;
1188			gpio-ranges = < 0x2b 0x00 0x97 0x08 >;
1189			interrupt-controller;
1190			#interrupt-cells = < 0x02 >;
1191			clocks = < 0x12 0x02 >;
1192			clock-names = "apb_pclk";
1193		};
1194
1195		spi@f7106000 {
1196			compatible = "arm,pl022\0arm,primecell";
1197			reg = < 0x00 0xf7106000 0x00 0x1000 >;
1198			interrupts = < 0x00 0x32 0x04 >;
1199			bus-id = < 0x00 >;
1200			enable-dma = < 0x00 >;
1201			clocks = < 0x13 0x15 >;
1202			clock-names = "apb_pclk";
1203			pinctrl-names = "default";
1204			pinctrl-0 = < 0x2c 0x2d >;
1205			num-cs = < 0x01 >;
1206			cs-gpios = < 0x2e 0x02 0x00 >;
1207			status = "ok";
1208		};
1209
1210		i2c@f7100000 {
1211			compatible = "snps,designware-i2c";
1212			reg = < 0x00 0xf7100000 0x00 0x1000 >;
1213			interrupts = < 0x00 0x2c 0x04 >;
1214			clocks = < 0x13 0x0d >;
1215			i2c-sda-hold-time-ns = < 0x12c >;
1216			pinctrl-names = "default";
1217			pinctrl-0 = < 0x2f 0x30 >;
1218			status = "ok";
1219		};
1220
1221		i2c@f7101000 {
1222			compatible = "snps,designware-i2c";
1223			reg = < 0x00 0xf7101000 0x00 0x1000 >;
1224			clocks = < 0x13 0x0e >;
1225			interrupts = < 0x00 0x2d 0x04 >;
1226			i2c-sda-hold-time-ns = < 0x12c >;
1227			pinctrl-names = "default";
1228			pinctrl-0 = < 0x31 0x32 >;
1229			status = "ok";
1230		};
1231
1232		i2c@f7102000 {
1233			compatible = "snps,designware-i2c";
1234			reg = < 0x00 0xf7102000 0x00 0x1000 >;
1235			clocks = < 0x13 0x0f >;
1236			interrupts = < 0x00 0x2e 0x04 >;
1237			i2c-sda-hold-time-ns = < 0x12c >;
1238			pinctrl-names = "default";
1239			pinctrl-0 = < 0x33 0x34 >;
1240			status = "ok";
1241			#address-cells = < 0x01 >;
1242			#size-cells = < 0x00 >;
1243
1244			adv7533@39 {
1245				compatible = "adi,adv7533";
1246				reg = < 0x39 >;
1247				interrupt-parent = < 0x17 >;
1248				interrupts = < 0x01 0x02 >;
1249				pd-gpio = < 0x35 0x04 0x00 >;
1250				adi,dsi-lanes = < 0x04 >;
1251				#sound-dai-cells = < 0x00 >;
1252
1253				ports {
1254					#address-cells = < 0x01 >;
1255					#size-cells = < 0x00 >;
1256
1257					port@0 {
1258
1259						endpoint {
1260							remote-endpoint = < 0x36 >;
1261							phandle = < 0x57 >;
1262						};
1263					};
1264
1265					port@2 {
1266						reg = < 0x02 >;
1267
1268						endpoint {
1269							remote-endpoint = < 0x37 >;
1270							phandle = < 0x50 >;
1271						};
1272					};
1273				};
1274			};
1275		};
1276
1277		usbphy {
1278			compatible = "hisilicon,hi6220-usb-phy";
1279			#phy-cells = < 0x00 >;
1280			phy-supply = < 0x38 >;
1281			hisilicon,peripheral-syscon = < 0x13 >;
1282			phandle = < 0x39 >;
1283		};
1284
1285		usb@f72c0000 {
1286			compatible = "hisilicon,hi6220-usb";
1287			reg = < 0x00 0xf72c0000 0x00 0x40000 >;
1288			phys = < 0x39 >;
1289			phy-names = "usb2-phy";
1290			clocks = < 0x13 0x07 >;
1291			clock-names = "otg";
1292			dr_mode = "otg";
1293			g-rx-fifo-size = < 0x200 >;
1294			g-np-tx-fifo-size = < 0x80 >;
1295			g-tx-fifo-size = < 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x10 0x10 0x10 0x10 0x10 0x10 0x10 >;
1296			interrupts = < 0x00 0x4d 0x04 >;
1297		};
1298
1299		mailbox@f7510000 {
1300			compatible = "hisilicon,hi6220-mbox";
1301			reg = < 0x00 0xf7510000 0x00 0x1000 0x00 0x6dff800 0x00 0x800 >;
1302			interrupts = < 0x00 0x5e 0x04 >;
1303			#mbox-cells = < 0x03 >;
1304			phandle = < 0x11 >;
1305		};
1306
1307		dwmmc0@f723d000 {
1308			compatible = "hisilicon,hi6220-dw-mshc";
1309			reg = < 0x00 0xf723d000 0x00 0x1000 >;
1310			interrupts = < 0x00 0x48 0x04 >;
1311			clocks = < 0x13 0x02 0x13 0x01 >;
1312			clock-names = "ciu\0biu";
1313			resets = < 0x13 0x00 >;
1314			reset-names = "reset";
1315			pinctrl-names = "default";
1316			pinctrl-0 = < 0x3a 0x3b 0x3c 0x3d >;
1317			cap-mmc-highspeed;
1318			mmc-hs200-1_8v;
1319			non-removable;
1320			bus-width = < 0x08 >;
1321			vmmc-supply = < 0x3e >;
1322		};
1323
1324		dwmmc1@f723e000 {
1325			compatible = "hisilicon,hi6220-dw-mshc";
1326			hisilicon,peripheral-syscon = < 0x12 >;
1327			reg = < 0x00 0xf723e000 0x00 0x1000 >;
1328			interrupts = < 0x00 0x49 0x04 >;
1329			#address-cells = < 0x01 >;
1330			#size-cells = < 0x00 >;
1331			clocks = < 0x13 0x04 0x13 0x03 >;
1332			clock-names = "ciu\0biu";
1333			resets = < 0x13 0x01 >;
1334			reset-names = "reset";
1335			pinctrl-names = "default\0idle";
1336			pinctrl-0 = < 0x3f 0x40 0x41 >;
1337			pinctrl-1 = < 0x42 0x43 0x44 >;
1338			card-detect-delay = < 0xc8 >;
1339			cap-sd-highspeed;
1340			sd-uhs-sdr12;
1341			sd-uhs-sdr25;
1342			sd-uhs-sdr50;
1343			vqmmc-supply = < 0x45 >;
1344			vmmc-supply = < 0x46 >;
1345			bus-width = < 0x04 >;
1346			disable-wp;
1347			cd-gpios = < 0x17 0x00 0x01 >;
1348		};
1349
1350		dwmmc2@f723f000 {
1351			compatible = "hisilicon,hi6220-dw-mshc";
1352			reg = < 0x00 0xf723f000 0x00 0x1000 >;
1353			interrupts = < 0x00 0x4a 0x04 >;
1354			clocks = < 0x13 0x06 0x13 0x05 >;
1355			clock-names = "ciu\0biu";
1356			resets = < 0x13 0x02 >;
1357			reset-names = "reset";
1358			pinctrl-names = "default\0idle";
1359			pinctrl-0 = < 0x47 0x48 0x49 >;
1360			pinctrl-1 = < 0x4a 0x4b 0x4c >;
1361			bus-width = < 0x04 >;
1362			non-removable;
1363			cap-power-off-card;
1364			vmmc-supply = < 0x4d >;
1365			mmc-pwrseq = < 0x4e >;
1366			#address-cells = < 0x01 >;
1367			#size-cells = < 0x00 >;
1368
1369			wlcore@2 {
1370				compatible = "ti,wl1835";
1371				reg = < 0x02 >;
1372				interrupt-parent = < 0x17 >;
1373				interrupts = < 0x03 0x01 >;
1374			};
1375		};
1376
1377		watchdog@f8005000 {
1378			compatible = "arm,sp805-wdt\0arm,primecell";
1379			reg = < 0x00 0xf8005000 0x00 0x1000 >;
1380			interrupts = < 0x00 0x0d 0x04 >;
1381			clocks = < 0x12 0x18 >;
1382			clock-names = "apb_pclk";
1383		};
1384
1385		tsensor@0,f7030700 {
1386			compatible = "hisilicon,tsensor";
1387			reg = < 0x00 0xf7030700 0x00 0x1000 >;
1388			interrupts = < 0x00 0x07 0x04 >;
1389			clocks = < 0x13 0x16 >;
1390			clock-names = "thermal_clk";
1391			#thermal-sensor-cells = < 0x01 >;
1392			phandle = < 0x51 >;
1393		};
1394
1395		i2s@f7118000 {
1396			compatible = "hisilicon,hi6210-i2s";
1397			reg = < 0x00 0xf7118000 0x00 0x8000 >;
1398			interrupts = < 0x00 0x7b 0x04 >;
1399			clocks = < 0x13 0x0a 0x13 0x38 >;
1400			clock-names = "dacodec\0i2s-base";
1401			dmas = < 0x4f 0x0f 0x4f 0x0e >;
1402			dma-names = "rx\0tx";
1403			hisilicon,sysctrl-syscon = < 0x13 >;
1404			#sound-dai-cells = < 0x01 >;
1405
1406			ports {
1407
1408				port@0 {
1409					phandle = < 0x76 >;
1410
1411					endpoint {
1412						remote-endpoint = < 0x50 >;
1413						dai-format = "i2s";
1414						phandle = < 0x37 >;
1415					};
1416				};
1417			};
1418		};
1419
1420		thermal-zones {
1421
1422			cls0 {
1423				polling-delay = < 0x3e8 >;
1424				polling-delay-passive = < 0x64 >;
1425				sustainable-power = < 0xcfe >;
1426				thermal-sensors = < 0x51 0x02 >;
1427
1428				trips {
1429
1430					trip-point@0 {
1431						temperature = < 0xfde8 >;
1432						hysteresis = < 0x00 >;
1433						type = "passive";
1434					};
1435
1436					trip-point@1 {
1437						temperature = < 0x124f8 >;
1438						hysteresis = < 0x00 >;
1439						type = "passive";
1440						phandle = < 0x52 >;
1441					};
1442				};
1443
1444				cooling-maps {
1445
1446					map0 {
1447						trip = < 0x52 >;
1448						cooling-device = < 0x02 0xffffffff 0xffffffff >;
1449					};
1450				};
1451			};
1452		};
1453
1454		ade@f4100000 {
1455			compatible = "hisilicon,hi6220-ade";
1456			reg = < 0x00 0xf4100000 0x00 0x7800 >;
1457			reg-names = "ade_base";
1458			hisilicon,noc-syscon = < 0x53 >;
1459			resets = < 0x54 0x05 >;
1460			interrupts = < 0x00 0x73 0x04 >;
1461			clocks = < 0x54 0x05 0x54 0x11 0x54 0x15 >;
1462			clock-names = "clk_ade_core\0clk_codec_jpeg\0clk_ade_pix";
1463			assigned-clocks = < 0x54 0x05 0x54 0x11 >;
1464			assigned-clock-rates = < 0x15752a00 0x112a8800 >;
1465			dma-coherent;
1466			status = "ok";
1467
1468			port {
1469
1470				endpoint {
1471					remote-endpoint = < 0x55 >;
1472					phandle = < 0x56 >;
1473				};
1474			};
1475		};
1476
1477		dsi@f4107800 {
1478			compatible = "hisilicon,hi6220-dsi";
1479			reg = < 0x00 0xf4107800 0x00 0x100 >;
1480			clocks = < 0x54 0x01 >;
1481			clock-names = "pclk";
1482			status = "ok";
1483
1484			ports {
1485				#address-cells = < 0x01 >;
1486				#size-cells = < 0x00 >;
1487
1488				port@0 {
1489					reg = < 0x00 >;
1490
1491					endpoint {
1492						remote-endpoint = < 0x56 >;
1493						phandle = < 0x55 >;
1494					};
1495				};
1496
1497				port@1 {
1498					reg = < 0x01 >;
1499
1500					endpoint@0 {
1501						remote-endpoint = < 0x57 >;
1502						phandle = < 0x36 >;
1503					};
1504				};
1505			};
1506		};
1507
1508		debug@f6590000 {
1509			compatible = "arm,coresight-cpu-debug\0arm,primecell";
1510			reg = < 0x00 0xf6590000 0x00 0x1000 >;
1511			clocks = < 0x13 0x3b >;
1512			clock-names = "apb_pclk";
1513			cpu = < 0x02 >;
1514		};
1515
1516		debug@f6592000 {
1517			compatible = "arm,coresight-cpu-debug\0arm,primecell";
1518			reg = < 0x00 0xf6592000 0x00 0x1000 >;
1519			clocks = < 0x13 0x3b >;
1520			clock-names = "apb_pclk";
1521			cpu = < 0x03 >;
1522		};
1523
1524		debug@f6594000 {
1525			compatible = "arm,coresight-cpu-debug\0arm,primecell";
1526			reg = < 0x00 0xf6594000 0x00 0x1000 >;
1527			clocks = < 0x13 0x3b >;
1528			clock-names = "apb_pclk";
1529			cpu = < 0x04 >;
1530		};
1531
1532		debug@f6596000 {
1533			compatible = "arm,coresight-cpu-debug\0arm,primecell";
1534			reg = < 0x00 0xf6596000 0x00 0x1000 >;
1535			clocks = < 0x13 0x3b >;
1536			clock-names = "apb_pclk";
1537			cpu = < 0x05 >;
1538		};
1539
1540		debug@f65d0000 {
1541			compatible = "arm,coresight-cpu-debug\0arm,primecell";
1542			reg = < 0x00 0xf65d0000 0x00 0x1000 >;
1543			clocks = < 0x13 0x3b >;
1544			clock-names = "apb_pclk";
1545			cpu = < 0x06 >;
1546		};
1547
1548		debug@f65d2000 {
1549			compatible = "arm,coresight-cpu-debug\0arm,primecell";
1550			reg = < 0x00 0xf65d2000 0x00 0x1000 >;
1551			clocks = < 0x13 0x3b >;
1552			clock-names = "apb_pclk";
1553			cpu = < 0x07 >;
1554		};
1555
1556		debug@f65d4000 {
1557			compatible = "arm,coresight-cpu-debug\0arm,primecell";
1558			reg = < 0x00 0xf65d4000 0x00 0x1000 >;
1559			clocks = < 0x13 0x3b >;
1560			clock-names = "apb_pclk";
1561			cpu = < 0x08 >;
1562		};
1563
1564		debug@f65d6000 {
1565			compatible = "arm,coresight-cpu-debug\0arm,primecell";
1566			reg = < 0x00 0xf65d6000 0x00 0x1000 >;
1567			clocks = < 0x13 0x3b >;
1568			clock-names = "apb_pclk";
1569			cpu = < 0x09 >;
1570		};
1571
1572		funnel@f6401000 {
1573			compatible = "arm,coresight-funnel\0arm,primecell";
1574			reg = < 0x00 0xf6401000 0x00 0x1000 >;
1575			clocks = < 0x58 0x00 >;
1576			clock-names = "apb_pclk";
1577
1578			out-ports {
1579
1580				port {
1581
1582					endpoint {
1583						remote-endpoint = < 0x59 >;
1584						phandle = < 0x5b >;
1585					};
1586				};
1587			};
1588
1589			in-ports {
1590
1591				port {
1592
1593					endpoint {
1594						remote-endpoint = < 0x5a >;
1595						phandle = < 0x62 >;
1596					};
1597				};
1598			};
1599		};
1600
1601		etf@f6402000 {
1602			compatible = "arm,coresight-tmc\0arm,primecell";
1603			reg = < 0x00 0xf6402000 0x00 0x1000 >;
1604			clocks = < 0x58 0x00 >;
1605			clock-names = "apb_pclk";
1606
1607			in-ports {
1608
1609				port {
1610
1611					endpoint {
1612						remote-endpoint = < 0x5b >;
1613						phandle = < 0x59 >;
1614					};
1615				};
1616			};
1617
1618			out-ports {
1619
1620				port {
1621
1622					endpoint {
1623						remote-endpoint = < 0x5c >;
1624						phandle = < 0x5d >;
1625					};
1626				};
1627			};
1628		};
1629
1630		replicator {
1631			compatible = "arm,coresight-replicator";
1632			clocks = < 0x58 0x00 >;
1633			clock-names = "apb_pclk";
1634
1635			in-ports {
1636
1637				port {
1638
1639					endpoint {
1640						remote-endpoint = < 0x5d >;
1641						phandle = < 0x5c >;
1642					};
1643				};
1644			};
1645
1646			out-ports {
1647				#address-cells = < 0x01 >;
1648				#size-cells = < 0x00 >;
1649
1650				port@0 {
1651					reg = < 0x00 >;
1652
1653					endpoint {
1654						remote-endpoint = < 0x5e >;
1655						phandle = < 0x60 >;
1656					};
1657				};
1658
1659				port@1 {
1660					reg = < 0x01 >;
1661
1662					endpoint {
1663						remote-endpoint = < 0x5f >;
1664						phandle = < 0x61 >;
1665					};
1666				};
1667			};
1668		};
1669
1670		etr@f6404000 {
1671			compatible = "arm,coresight-tmc\0arm,primecell";
1672			reg = < 0x00 0xf6404000 0x00 0x1000 >;
1673			clocks = < 0x58 0x00 >;
1674			clock-names = "apb_pclk";
1675
1676			in-ports {
1677
1678				port {
1679
1680					endpoint {
1681						remote-endpoint = < 0x60 >;
1682						phandle = < 0x5e >;
1683					};
1684				};
1685			};
1686		};
1687
1688		tpiu@f6405000 {
1689			compatible = "arm,coresight-tpiu\0arm,primecell";
1690			reg = < 0x00 0xf6405000 0x00 0x1000 >;
1691			clocks = < 0x58 0x00 >;
1692			clock-names = "apb_pclk";
1693
1694			in-ports {
1695
1696				port {
1697
1698					endpoint {
1699						remote-endpoint = < 0x61 >;
1700						phandle = < 0x5f >;
1701					};
1702				};
1703			};
1704		};
1705
1706		funnel@f6501000 {
1707			compatible = "arm,coresight-funnel\0arm,primecell";
1708			reg = < 0x00 0xf6501000 0x00 0x1000 >;
1709			clocks = < 0x58 0x00 >;
1710			clock-names = "apb_pclk";
1711
1712			out-ports {
1713
1714				port {
1715
1716					endpoint {
1717						remote-endpoint = < 0x62 >;
1718						phandle = < 0x5a >;
1719					};
1720				};
1721			};
1722
1723			in-ports {
1724				#address-cells = < 0x01 >;
1725				#size-cells = < 0x00 >;
1726
1727				port@0 {
1728					reg = < 0x00 >;
1729
1730					endpoint {
1731						remote-endpoint = < 0x63 >;
1732						phandle = < 0x6b >;
1733					};
1734				};
1735
1736				port@1 {
1737					reg = < 0x01 >;
1738
1739					endpoint {
1740						remote-endpoint = < 0x64 >;
1741						phandle = < 0x6c >;
1742					};
1743				};
1744
1745				port@2 {
1746					reg = < 0x02 >;
1747
1748					endpoint {
1749						remote-endpoint = < 0x65 >;
1750						phandle = < 0x6d >;
1751					};
1752				};
1753
1754				port@3 {
1755					reg = < 0x03 >;
1756
1757					endpoint {
1758						remote-endpoint = < 0x66 >;
1759						phandle = < 0x6e >;
1760					};
1761				};
1762
1763				port@4 {
1764					reg = < 0x04 >;
1765
1766					endpoint {
1767						remote-endpoint = < 0x67 >;
1768						phandle = < 0x6f >;
1769					};
1770				};
1771
1772				port@5 {
1773					reg = < 0x05 >;
1774
1775					endpoint {
1776						remote-endpoint = < 0x68 >;
1777						phandle = < 0x70 >;
1778					};
1779				};
1780
1781				port@6 {
1782					reg = < 0x06 >;
1783
1784					endpoint {
1785						remote-endpoint = < 0x69 >;
1786						phandle = < 0x71 >;
1787					};
1788				};
1789
1790				port@7 {
1791					reg = < 0x07 >;
1792
1793					endpoint {
1794						remote-endpoint = < 0x6a >;
1795						phandle = < 0x72 >;
1796					};
1797				};
1798			};
1799		};
1800
1801		etm@f659c000 {
1802			compatible = "arm,coresight-etm4x\0arm,primecell";
1803			reg = < 0x00 0xf659c000 0x00 0x1000 >;
1804			clocks = < 0x58 0x00 >;
1805			clock-names = "apb_pclk";
1806			cpu = < 0x02 >;
1807
1808			out-ports {
1809
1810				port {
1811
1812					endpoint {
1813						remote-endpoint = < 0x6b >;
1814						phandle = < 0x63 >;
1815					};
1816				};
1817			};
1818		};
1819
1820		etm@f659d000 {
1821			compatible = "arm,coresight-etm4x\0arm,primecell";
1822			reg = < 0x00 0xf659d000 0x00 0x1000 >;
1823			clocks = < 0x58 0x00 >;
1824			clock-names = "apb_pclk";
1825			cpu = < 0x03 >;
1826
1827			out-ports {
1828
1829				port {
1830
1831					endpoint {
1832						remote-endpoint = < 0x6c >;
1833						phandle = < 0x64 >;
1834					};
1835				};
1836			};
1837		};
1838
1839		etm@f659e000 {
1840			compatible = "arm,coresight-etm4x\0arm,primecell";
1841			reg = < 0x00 0xf659e000 0x00 0x1000 >;
1842			clocks = < 0x58 0x00 >;
1843			clock-names = "apb_pclk";
1844			cpu = < 0x04 >;
1845
1846			out-ports {
1847
1848				port {
1849
1850					endpoint {
1851						remote-endpoint = < 0x6d >;
1852						phandle = < 0x65 >;
1853					};
1854				};
1855			};
1856		};
1857
1858		etm@f659f000 {
1859			compatible = "arm,coresight-etm4x\0arm,primecell";
1860			reg = < 0x00 0xf659f000 0x00 0x1000 >;
1861			clocks = < 0x58 0x00 >;
1862			clock-names = "apb_pclk";
1863			cpu = < 0x05 >;
1864
1865			out-ports {
1866
1867				port {
1868
1869					endpoint {
1870						remote-endpoint = < 0x6e >;
1871						phandle = < 0x66 >;
1872					};
1873				};
1874			};
1875		};
1876
1877		etm@f65dc000 {
1878			compatible = "arm,coresight-etm4x\0arm,primecell";
1879			reg = < 0x00 0xf65dc000 0x00 0x1000 >;
1880			clocks = < 0x58 0x00 >;
1881			clock-names = "apb_pclk";
1882			cpu = < 0x06 >;
1883
1884			out-ports {
1885
1886				port {
1887
1888					endpoint {
1889						remote-endpoint = < 0x6f >;
1890						phandle = < 0x67 >;
1891					};
1892				};
1893			};
1894		};
1895
1896		etm@f65dd000 {
1897			compatible = "arm,coresight-etm4x\0arm,primecell";
1898			reg = < 0x00 0xf65dd000 0x00 0x1000 >;
1899			clocks = < 0x58 0x00 >;
1900			clock-names = "apb_pclk";
1901			cpu = < 0x07 >;
1902
1903			out-ports {
1904
1905				port {
1906
1907					endpoint {
1908						remote-endpoint = < 0x70 >;
1909						phandle = < 0x68 >;
1910					};
1911				};
1912			};
1913		};
1914
1915		etm@f65de000 {
1916			compatible = "arm,coresight-etm4x\0arm,primecell";
1917			reg = < 0x00 0xf65de000 0x00 0x1000 >;
1918			clocks = < 0x58 0x00 >;
1919			clock-names = "apb_pclk";
1920			cpu = < 0x08 >;
1921
1922			out-ports {
1923
1924				port {
1925
1926					endpoint {
1927						remote-endpoint = < 0x71 >;
1928						phandle = < 0x69 >;
1929					};
1930				};
1931			};
1932		};
1933
1934		etm@f65df000 {
1935			compatible = "arm,coresight-etm4x\0arm,primecell";
1936			reg = < 0x00 0xf65df000 0x00 0x1000 >;
1937			clocks = < 0x58 0x00 >;
1938			clock-names = "apb_pclk";
1939			cpu = < 0x09 >;
1940
1941			out-ports {
1942
1943				port {
1944
1945					endpoint {
1946						remote-endpoint = < 0x72 >;
1947						phandle = < 0x6a >;
1948					};
1949				};
1950			};
1951		};
1952	};
1953
1954	aliases {
1955		serial0 = "/soc/uart@f8015000";
1956		serial1 = "/soc/uart@f7111000";
1957		serial2 = "/soc/uart@f7112000";
1958		serial3 = "/soc/uart@f7113000";
1959	};
1960
1961	chosen {
1962		stdout-path = "serial3:115200n8";
1963	};
1964
1965	memory@0 {
1966		device_type = "memory";
1967		reg = < 0x00 0x00 0x00 0x5e00000 0x00 0x5f00000 0x00 0x1000 0x00 0x5f02000 0x00 0xefd000 0x00 0x6e00000 0x00 0x60f000 0x00 0x7410000 0x00 0x1aaf0000 0x00 0x22000000 0x00 0x1c000000 >;
1968	};
1969
1970	reserved-memory {
1971		#address-cells = < 0x02 >;
1972		#size-cells = < 0x02 >;
1973		ranges;
1974
1975		ramoops@21f00000 {
1976			compatible = "ramoops";
1977			reg = < 0x00 0x21f00000 0x00 0x100000 >;
1978			record-size = < 0x20000 >;
1979			console-size = < 0x20000 >;
1980			ftrace-size = < 0x20000 >;
1981		};
1982
1983		linux,cma {
1984			compatible = "shared-dma-pool";
1985			reusable;
1986			size = < 0x00 0x8000000 >;
1987			linux,cma-default;
1988		};
1989	};
1990
1991	reboot-mode-syscon@5f01000 {
1992		compatible = "syscon\0simple-mfd";
1993		reg = < 0x00 0x5f01000 0x00 0x1000 >;
1994
1995		reboot-mode {
1996			compatible = "syscon-reboot-mode";
1997			offset = < 0x00 >;
1998			mode-normal = < 0x77665501 >;
1999			mode-bootloader = "wfU";
2000			mode-recovery = < 0x77665502 >;
2001		};
2002	};
2003
2004	regulator@0 {
2005		compatible = "regulator-fixed";
2006		regulator-name = "SYS_5V";
2007		regulator-min-microvolt = < 0x4c4b40 >;
2008		regulator-max-microvolt = < 0x4c4b40 >;
2009		regulator-boot-on;
2010		regulator-always-on;
2011		phandle = < 0x73 >;
2012	};
2013
2014	regulator@1 {
2015		compatible = "regulator-fixed";
2016		regulator-name = "VDD_3V3";
2017		regulator-min-microvolt = < 0x325aa0 >;
2018		regulator-max-microvolt = < 0x325aa0 >;
2019		regulator-boot-on;
2020		regulator-always-on;
2021		vin-supply = < 0x73 >;
2022		phandle = < 0x4d >;
2023	};
2024
2025	regulator@2 {
2026		compatible = "regulator-fixed";
2027		regulator-name = "5V_HUB";
2028		regulator-min-microvolt = < 0x4c4b40 >;
2029		regulator-max-microvolt = < 0x4c4b40 >;
2030		regulator-boot-on;
2031		gpio = < 0x35 0x07 0x00 >;
2032		regulator-always-on;
2033		vin-supply = < 0x73 >;
2034		phandle = < 0x38 >;
2035	};
2036
2037	wl1835-pwrseq {
2038		compatible = "mmc-pwrseq-simple";
2039		reset-gpios = < 0x35 0x05 0x01 >;
2040		clocks = < 0x18 >;
2041		clock-names = "ext_clock";
2042		power-off-delay-us = < 0x0a >;
2043		phandle = < 0x4e >;
2044	};
2045
2046	leds {
2047		compatible = "gpio-leds";
2048
2049		user_led4 {
2050			label = "user_led4";
2051			gpios = < 0x74 0x00 0x00 >;
2052			linux,default-trigger = "heartbeat";
2053		};
2054
2055		user_led3 {
2056			label = "user_led3";
2057			gpios = < 0x74 0x01 0x00 >;
2058			linux,default-trigger = "mmc0";
2059		};
2060
2061		user_led2 {
2062			label = "user_led2";
2063			gpios = < 0x74 0x02 0x00 >;
2064			linux,default-trigger = "mmc1";
2065		};
2066
2067		user_led1 {
2068			label = "user_led1";
2069			gpios = < 0x74 0x03 0x00 >;
2070			panic-indicator;
2071			linux,default-trigger = "cpu0";
2072		};
2073
2074		wlan_active_led {
2075			label = "wifi_active";
2076			gpios = < 0x75 0x05 0x00 >;
2077			linux,default-trigger = "phy0tx";
2078			default-state = "off";
2079		};
2080
2081		bt_active_led {
2082			label = "bt_active";
2083			gpios = < 0x74 0x07 0x00 >;
2084			linux,default-trigger = "hci0rx";
2085			default-state = "off";
2086		};
2087	};
2088
2089	pmic@f8000000 {
2090		compatible = "hisilicon,hi655x-pmic";
2091		reg = < 0x00 0xf8000000 0x00 0x1000 >;
2092		#clock-cells = < 0x00 >;
2093		interrupt-controller;
2094		#interrupt-cells = < 0x02 >;
2095		pmic-gpios = < 0x17 0x02 0x00 >;
2096		phandle = < 0x18 >;
2097
2098		regulators {
2099
2100			LDO2 {
2101				regulator-name = "LDO2_2V8";
2102				regulator-min-microvolt = < 0x2625a0 >;
2103				regulator-max-microvolt = < 0x30d400 >;
2104				regulator-enable-ramp-delay = < 0x78 >;
2105			};
2106
2107			LDO7 {
2108				regulator-name = "LDO7_SDIO";
2109				regulator-min-microvolt = < 0x1b7740 >;
2110				regulator-max-microvolt = < 0x325aa0 >;
2111				regulator-enable-ramp-delay = < 0x78 >;
2112				phandle = < 0x45 >;
2113			};
2114
2115			LDO10 {
2116				regulator-name = "LDO10_2V85";
2117				regulator-min-microvolt = < 0x1b7740 >;
2118				regulator-max-microvolt = < 0x2dc6c0 >;
2119				regulator-enable-ramp-delay = < 0x168 >;
2120				phandle = < 0x46 >;
2121			};
2122
2123			LDO13 {
2124				regulator-name = "LDO13_1V8";
2125				regulator-min-microvolt = < 0x186a00 >;
2126				regulator-max-microvolt = < 0x1dc130 >;
2127				regulator-enable-ramp-delay = < 0x78 >;
2128			};
2129
2130			LDO14 {
2131				regulator-name = "LDO14_2V8";
2132				regulator-min-microvolt = < 0x2625a0 >;
2133				regulator-max-microvolt = < 0x30d400 >;
2134				regulator-enable-ramp-delay = < 0x78 >;
2135			};
2136
2137			LDO15 {
2138				regulator-name = "LDO15_1V8";
2139				regulator-min-microvolt = < 0x186a00 >;
2140				regulator-max-microvolt = < 0x1dc130 >;
2141				regulator-boot-on;
2142				regulator-always-on;
2143				regulator-enable-ramp-delay = < 0x78 >;
2144			};
2145
2146			LDO17 {
2147				regulator-name = "LDO17_2V5";
2148				regulator-min-microvolt = < 0x2625a0 >;
2149				regulator-max-microvolt = < 0x30d400 >;
2150				regulator-enable-ramp-delay = < 0x78 >;
2151			};
2152
2153			LDO19 {
2154				regulator-name = "LDO19_3V0";
2155				regulator-min-microvolt = < 0x1b7740 >;
2156				regulator-max-microvolt = < 0x2dc6c0 >;
2157				regulator-enable-ramp-delay = < 0x168 >;
2158				phandle = < 0x3e >;
2159			};
2160
2161			LDO21 {
2162				regulator-name = "LDO21_1V8";
2163				regulator-min-microvolt = < 0x192d50 >;
2164				regulator-max-microvolt = < 0x1e8480 >;
2165				regulator-always-on;
2166				regulator-enable-ramp-delay = < 0x78 >;
2167			};
2168
2169			LDO22 {
2170				regulator-name = "LDO22_1V2";
2171				regulator-min-microvolt = < 0xdbba0 >;
2172				regulator-max-microvolt = < 0x124f80 >;
2173				regulator-boot-on;
2174				regulator-always-on;
2175				regulator-enable-ramp-delay = < 0x78 >;
2176			};
2177		};
2178	};
2179
2180	firmware {
2181
2182		optee {
2183			compatible = "linaro,optee-tz";
2184			method = "smc";
2185		};
2186	};
2187
2188	sound_card {
2189		compatible = "audio-graph-card";
2190		dais = < 0x76 >;
2191	};
2192};
2193