1/* 2 * Copyright 2014, General Dynamics C4 Systems 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7#pragma once 8 9#include <arch/types.h> 10#include <arch/object/structures.h> 11#include <arch/machine/hardware.h> 12#include <arch/machine/pat.h> 13#include <arch/machine/cpu_registers.h> 14#include <model/statedata.h> 15#include <arch/model/statedata.h> 16#include <object/interrupt.h> 17 18#define IA32_APIC_BASE_MSR 0x01B 19#define IA32_ARCH_CAPABILITIES_MSR 0x10A 20#define IA32_SYSENTER_CS_MSR 0x174 21#define IA32_SYSENTER_ESP_MSR 0x175 22#define IA32_SYSENTER_EIP_MSR 0x176 23#define IA32_TSC_DEADLINE_MSR 0x6e0 24#define IA32_FS_BASE_MSR 0xC0000100 25#define IA32_GS_BASE_MSR 0xC0000101 26#define IA32_LSTAR_MSR 0xC0000082 27#define IA32_STAR_MSR 0xC0000081 28#define IA32_FMASK_MSR 0xC0000084 29#define IA32_EFER_MSR 0xC0000080 30#define IA32_PLATFORM_INFO_MSR 0xCE 31#define IA32_XSS_MSR 0xD0A 32#define IA32_FEATURE_CONTROL_MSR 0x3A 33#define IA32_KERNEL_GS_BASE_MSR 0xC0000102 34#define IA32_VMX_BASIC_MSR 0x480 35#define IA32_VMX_PINBASED_CTLS_MSR 0x481 36#define IA32_VMX_PROCBASED_CTLS_MSR 0x482 37#define IA32_VMX_PROCBASED_CTLS2_MSR 0x48B 38#define IA32_VMX_EXIT_CTLS_MSR 0x483 39#define IA32_VMX_ENTRY_CTLS_MSR 0x484 40#define IA32_VMX_TRUE_PINBASED_CTLS_MSR 0x48D 41#define IA32_VMX_TRUE_PROCBASED_CTLS_MSR 0x48E 42#define IA32_VMX_TRUE_EXIT_CTLS_MSR 0x48F 43#define IA32_VMX_TRUE_ENTRY_CTLS_MSR 0x490 44#define IA32_VMX_CR0_FIXED0_MSR 0x486 45#define IA32_VMX_CR0_FIXED1_MSR 0x487 46#define IA32_VMX_CR4_FIXED0_MSR 0x488 47#define IA32_VMX_CR4_FIXED1_MSR 0x489 48#define IA32_VMX_EPT_VPID_CAP_MSR 0x48C 49 50#define IA32_PREFETCHER_COMPATIBLE_FAMILIES_ID (0x06) 51 52/* These values taken from: 53 * * Intel manuals, Vol3, table 35-1. 54 * * https://software.intel.com/en-us/articles/intel-architecture-and-processor-identification-with-cpuid-model-and-family-numbers 55 */ 56#define SKYLAKE_1_MODEL_ID 0x4E 57#define SKYLAKE_2_MODEL_ID 0x5E 58#define BROADWELL_1_MODEL_ID 0x4D 59#define BROADWELL_2_MODEL_ID 0x56 60#define BROADWELL_3_MODEL_ID 0x4F 61#define BROADWELL_4_MODEL_ID 0x47 62#define BROADWELL_5_MODEL_ID 0x3D 63#define HASWELL_1_MODEL_ID 0x3C 64#define HASWELL_2_MODEL_ID 0x3F 65#define HASWELL_3_MODEL_ID 0x45 66#define HASWELL_4_MODEL_ID 0x46 67#define IVY_BRIDGE_1_MODEL_ID 0x9A 68#define IVY_BRIDGE_2_MODEL_ID 0x3E 69#define IVY_BRIDGE_3_MODEL_ID 0x3A 70#define SANDY_BRIDGE_1_MODEL_ID 0x2A /* Sandy Bridge */ 71#define SANDY_BRIDGE_2_MODEL_ID 0x2D /* Sandy Bridge-E, Sandy Bridge-EN and Sandy Bridge-EP */ 72#define WESTMERE_1_MODEL_ID 0x25 /* Arrandale and Clarksdale */ 73#define WESTMERE_2_MODEL_ID 0x2C /* Gulftown and Westmere-EP */ 74#define WESTMERE_3_MODEL_ID 0x2F /* Westemere-EX */ 75#define NEHALEM_1_MODEL_ID 0x1E /* Clarksfield, Lynnfield and Jasper Forest */ 76#define NEHALEM_2_MODEL_ID 0x1A /* Bloomfield and Nehalem-EP */ 77#define NEHALEM_3_MODEL_ID 0x2E /* Nehalem-EX */ 78 79#define X86_CPUID_VENDOR_STRING_MAXLENGTH (12) 80#define X86_CPU_MODEL_STRING_MAXLENGTH (47) 81 82/* This article discloses prefetcher control on Intel processors; Nehalem, Westmere, Sandy Bridge, 83 Ivy Bridge, Haswell, and Broadwell. It is currently undocumented in the regular intel manuals. 84 https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors */ 85#define IA32_PREFETCHER_MSR 0x1A4 86#define IA32_PREFETCHER_MSR_L2 BIT(0) 87#define IA32_PREFETCHER_MSR_L2_ADJACENT BIT(1) 88#define IA32_PREFETCHER_MSR_DCU BIT(2) 89#define IA32_PREFETCHER_MSR_DCU_IP BIT(3) 90 91#define IA32_SPEC_CTRL_MSR 0x48 92#define IA32_SPEC_CTRL_MSR_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 93#define IA32_SPEC_CTRL_MSR_STIBP BIT(1) /* Single Thread Indirect Branch Predictors */ 94 95#define IA32_PRED_CMD_MSR 0x49 96 97word_t PURE getRestartPC(tcb_t *thread); 98void setNextPC(tcb_t *thread, word_t v); 99 100static uint64_t x86_rdmsr(const uint32_t reg) 101{ 102 uint32_t low, high; 103 uint64_t value; 104 asm volatile("rdmsr" : "=a"(low), "=d"(high) : "c"(reg)); 105 value = ((uint64_t)high << 32) | (uint64_t)low; 106 return value; 107} 108 109/* Read model specific register */ 110static inline uint32_t x86_rdmsr_low(const uint32_t reg) 111{ 112 return (uint32_t)x86_rdmsr(reg); 113} 114 115static inline uint32_t x86_rdmsr_high(const uint32_t reg) 116{ 117 return (uint32_t)(x86_rdmsr(reg) >> 32ull); 118} 119 120/* Write model specific register */ 121static inline void x86_wrmsr_parts(const uint32_t reg, const uint32_t high, const uint32_t low) 122{ 123 asm volatile("wrmsr" :: "a"(low), "d"(high), "c"(reg)); 124} 125 126static inline void x86_wrmsr(const uint32_t reg, const uint64_t val) 127{ 128 uint32_t low = (uint32_t)val; 129 uint32_t high = (uint32_t)(val >> 32); 130 x86_wrmsr_parts(reg, high, low); 131} 132 133/* Read different parts of CPUID */ 134static inline uint32_t x86_cpuid_edx(uint32_t eax, uint32_t ecx) 135{ 136 uint32_t edx, ebx; 137 asm volatile("cpuid" 138 : "=a"(eax), 139 "=b"(ebx), 140 "=c"(ecx), 141 "=d"(edx) 142 : "a"(eax), "c"(ecx) 143 : "memory"); 144 return edx; 145} 146 147static inline uint32_t x86_cpuid_eax(uint32_t eax, uint32_t ecx) 148{ 149 uint32_t edx, ebx; 150 asm volatile("cpuid" 151 : "=a"(eax), 152 "=b"(ebx), 153 "=c"(ecx), 154 "=d"(edx) 155 : "a"(eax), "c"(ecx) 156 : "memory"); 157 return eax; 158} 159 160static inline uint32_t x86_cpuid_ecx(uint32_t eax, uint32_t ecx) 161{ 162 uint32_t edx, ebx; 163 asm volatile("cpuid" 164 : "=a"(eax), 165 "=b"(ebx), 166 "=c"(ecx), 167 "=d"(edx) 168 : "a"(eax), "c"(ecx) 169 : "memory"); 170 return ecx; 171} 172 173static inline uint32_t x86_cpuid_ebx(uint32_t eax, uint32_t ecx) 174{ 175 uint32_t edx, ebx; 176 asm volatile("cpuid" 177 : "=a"(eax), 178 "=b"(ebx), 179 "=c"(ecx), 180 "=d"(edx) 181 : "a"(eax), "c"(ecx) 182 : "memory"); 183 return ebx; 184} 185 186static inline uint64_t x86_rdtsc(void) 187{ 188 uint32_t hi, lo; 189 asm volatile("rdtsc" 190 : "=a"(lo), 191 "=d"(hi) 192 ); 193 return ((uint64_t) hi) << 32llu | (uint64_t) lo; 194} 195 196#ifdef ENABLE_SMP_SUPPORT 197static inline void arch_pause(void) 198{ 199 asm volatile("pause"); 200} 201#endif /* ENABLE_SMP_SUPPORT */ 202 203enum x86_vendor { 204 X86_VENDOR_INTEL = 0, 205 X86_VENDOR_AMD, 206 X86_VENDOR_OTHER 207}; 208 209typedef struct _x86_cpu_identity { 210 uint8_t family, model, stepping, extended_family, extended_model; 211 uint8_t brand; 212} x86_cpu_identity_t; 213 214typedef struct _cpu_identity { 215 enum x86_vendor vendor; 216 char vendor_string[X86_CPUID_VENDOR_STRING_MAXLENGTH + 1]; 217 218 /* Adjusted and normalized family, model and stepping values as recommended 219 * by Intel. The name "display" was chosen because that's the nomenclature 220 * Intel uses. 221 */ 222 x86_cpu_identity_t display; 223} cpu_identity_t; 224 225/* This, and all its adjoint routines will be called at init time; see boot.c */ 226BOOT_CODE bool_t x86_cpuid_initialize(void); 227 228/** To be used by code that wants to know the family/model/stepping/brand of 229 * a CPU. 230 */ 231x86_cpu_identity_t *x86_cpuid_get_model_info(void); 232 233/** To be used by code that wants to get the CPU vendor name. 234 */ 235cpu_identity_t *x86_cpuid_get_identity(void); 236 237/* 238 * Forward declarations here as these may instead be later defined in 239 * mode-specific machine.h 240 */ 241 242static inline void x86_write_fs_base_impl(word_t base); 243static inline word_t x86_read_fs_base_impl(void); 244static inline void x86_write_gs_base_impl(word_t base); 245static inline word_t x86_read_gs_base_impl(void); 246 247#ifdef CONFIG_FSGSBASE_MSR 248 249static inline void x86_write_fs_base_impl(word_t base) 250{ 251 x86_wrmsr(IA32_FS_BASE_MSR, base); 252} 253 254static inline word_t x86_read_fs_base_impl(void) 255{ 256 return x86_rdmsr(IA32_FS_BASE_MSR); 257} 258 259#endif 260 261 262#ifdef CONFIG_FSGSBASE_INST 263 264/* 265 * With fsgsbase, these registers can and are allowed to be changed from 266 * user-space. 267 * 268 * These calls are also cheap as they read from the hidden register 269 * state for the segment selectors rather than from the GDT. 270 */ 271 272static inline void x86_write_fs_base(word_t base, cpu_id_t cpu) 273{ 274 x86_write_fs_base_impl(base); 275} 276 277static inline void x86_write_gs_base(word_t base, cpu_id_t cpu) 278{ 279 x86_write_gs_base_impl(base); 280} 281 282static inline word_t x86_read_fs_base(cpu_id_t cpu) 283{ 284 return x86_read_fs_base_impl(); 285} 286 287static inline word_t x86_read_gs_base(cpu_id_t cpu) 288{ 289 return x86_read_gs_base_impl(); 290} 291 292#else 293 294/* Writing the fs/gs bases can be expensive (especially if it requires a MSR 295 write), so we avoid actually writing them if they aren't actually changed. */ 296 297static inline void x86_write_fs_base(word_t base, cpu_id_t cpu) 298{ 299 if (base != ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu)) { 300 ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu) = base; 301 x86_write_fs_base_impl(base); 302 } 303} 304 305static inline void x86_write_gs_base(word_t base, cpu_id_t cpu) 306{ 307 if (likely(base != ARCH_NODE_STATE_ON_CORE(x86KSCurrentGSBase, cpu))) { 308 ARCH_NODE_STATE_ON_CORE(x86KSCurrentGSBase, cpu) = base; 309 x86_write_gs_base_impl(base); 310 } 311} 312 313static inline word_t x86_read_fs_base(cpu_id_t cpu) 314{ 315 return ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu); 316} 317 318static inline word_t x86_read_gs_base(cpu_id_t cpu) 319{ 320 return ARCH_NODE_STATE_ON_CORE(x86KSCurrentGSBase, cpu); 321} 322 323#endif 324 325 326static inline void x86_load_fsgs_base(tcb_t *thread, cpu_id_t cpu) 327{ 328 /* 329 * Restore the FS and GS base registers. 330 * 331 * These should only be accessed inside the kernel, between the 332 * entry and exit calls to swapgs if used. 333 */ 334 word_t fs_base = getRegister(thread, FS_BASE); 335 x86_write_fs_base(fs_base, cpu); 336 word_t gs_base = getRegister(thread, GS_BASE); 337 x86_write_gs_base(gs_base, cpu); 338} 339 340/* Cleaning memory before user-level access */ 341static inline void clearMemory(void *ptr, unsigned int bits) 342{ 343 memzero(ptr, BIT(bits)); 344 /* no cleaning of caches necessary on IA-32 */ 345} 346 347/* Initialises MSRs required to setup sysenter and sysexit */ 348void init_sysenter_msrs(void); 349 350/* Read/write memory fence */ 351static inline void x86_mfence(void) 352{ 353 asm volatile("mfence" ::: "memory"); 354} 355 356/* Get page fault address from CR2 register */ 357static inline unsigned long getFaultAddr(void) 358{ 359 return read_cr2(); 360} 361 362static inline void Arch_finaliseInterrupt(void) 363{ 364 ARCH_NODE_STATE(x86KScurInterrupt) = int_invalid; 365} 366 367static inline void x86_set_tls_segment_base(word_t tls_base); 368 369/* Update the value of the actual regsiter to hold the expected value */ 370static inline exception_t Arch_setTLSRegister(word_t tls_base) 371{ 372 word_t sanitised = Mode_sanitiseRegister(TLS_BASE, tls_base); 373 374 if (sanitised != tls_base) { 375 return EXCEPTION_SYSCALL_ERROR; 376 } 377 378#ifndef CONFIG_FSGSBASE_INST 379 /* 380 * The context is only updated from the register on a context switch 381 * if the FSGS instructions are enabled. When they aren't it msut be 382 * manually stored here. 383 */ 384 setRegister(NODE_STATE(ksCurThread), TLS_BASE, tls_base); 385#endif 386 387 x86_set_tls_segment_base(sanitised); 388 389 return EXCEPTION_NONE; 390} 391 392/* we do not cache the IBRS value as writing the enable bit is meaningful even if it 393 * is already set. On some processors if the enable bit was set it must be 're-written' 394 * in order for a higher privilege to correctly not have its branch predictions affected */ 395static inline void x86_enable_ibrs(void) 396{ 397 /* we always enable the STIBP bit since we want it on if its supported and it 398 * isn't a fault to set the bit if support is missing */ 399 x86_wrmsr(IA32_SPEC_CTRL_MSR, IA32_SPEC_CTRL_MSR_IBRS | IA32_SPEC_CTRL_MSR_STIBP); 400} 401 402static inline void x86_disable_ibrs(void) 403{ 404 /* we always enable the STIBP bit since we want it on if its supported and it 405 * isn't a fault to set the bit if support is missing */ 406 x86_wrmsr(IA32_SPEC_CTRL_MSR, IA32_SPEC_CTRL_MSR_STIBP); 407} 408 409static inline void x86_ibpb(void) 410{ 411 x86_wrmsr(IA32_PRED_CMD_MSR, 1); 412} 413 414static inline void x86_flush_rsb(void) 415{ 416 /* perform 32 near calls with a non zero displacement to flush the rsb with 417 * speculation traps. */ 418 word_t iter = 32; 419 asm volatile( 420 "1:\n" 421 "sub $2, %[iter]\n" 422 "call 2f\n" 423 "pause\n" 424 "jmp 1b\n" 425 "2:\n" 426 "call 3f\n" 427 "pause\n" 428 "jmp 2b\n" 429 "3:\n" 430 "cmp $0, %[iter]\n" 431 "jne 1b\n" 432#ifdef CONFIG_ARCH_X86_64 433 "add %[stack_amount], %%rsp\n" 434#else 435 "add %[stack_amount], %%esp\n" 436#endif 437 : [iter]"+r"(iter) 438 : [stack_amount]"i"(sizeof(word_t) * iter) 439 : "cc" 440 ); 441} 442 443/* sysenter entry point */ 444void handle_syscall(void); 445 446/** MODIFIES: phantom_machine_state */ 447void int_00(void); 448/** MODIFIES: phantom_machine_state */ 449void int_01(void); 450/** MODIFIES: phantom_machine_state */ 451void int_02(void); 452/** MODIFIES: phantom_machine_state */ 453void int_03(void); 454/** MODIFIES: phantom_machine_state */ 455void int_04(void); 456/** MODIFIES: phantom_machine_state */ 457void int_05(void); 458/** MODIFIES: phantom_machine_state */ 459void int_06(void); 460/** MODIFIES: phantom_machine_state */ 461void int_07(void); 462/** MODIFIES: phantom_machine_state */ 463void int_08(void); 464/** MODIFIES: phantom_machine_state */ 465void int_09(void); 466/** MODIFIES: phantom_machine_state */ 467void int_0a(void); 468/** MODIFIES: phantom_machine_state */ 469void int_0b(void); 470/** MODIFIES: phantom_machine_state */ 471void int_0c(void); 472/** MODIFIES: phantom_machine_state */ 473void int_0d(void); 474/** MODIFIES: phantom_machine_state */ 475void int_0e(void); 476/** MODIFIES: phantom_machine_state */ 477void int_0f(void); 478 479/** MODIFIES: phantom_machine_state */ 480void int_10(void); 481/** MODIFIES: phantom_machine_state */ 482void int_11(void); 483/** MODIFIES: phantom_machine_state */ 484void int_12(void); 485/** MODIFIES: phantom_machine_state */ 486void int_13(void); 487/** MODIFIES: phantom_machine_state */ 488void int_14(void); 489/** MODIFIES: phantom_machine_state */ 490void int_15(void); 491/** MODIFIES: phantom_machine_state */ 492void int_16(void); 493/** MODIFIES: phantom_machine_state */ 494void int_17(void); 495/** MODIFIES: phantom_machine_state */ 496void int_18(void); 497/** MODIFIES: phantom_machine_state */ 498void int_19(void); 499/** MODIFIES: phantom_machine_state */ 500void int_1a(void); 501/** MODIFIES: phantom_machine_state */ 502void int_1b(void); 503/** MODIFIES: phantom_machine_state */ 504void int_1c(void); 505/** MODIFIES: phantom_machine_state */ 506void int_1d(void); 507/** MODIFIES: phantom_machine_state */ 508void int_1e(void); 509/** MODIFIES: phantom_machine_state */ 510void int_1f(void); 511 512/** MODIFIES: phantom_machine_state */ 513void int_20(void); 514/** MODIFIES: phantom_machine_state */ 515void int_21(void); 516/** MODIFIES: phantom_machine_state */ 517void int_22(void); 518/** MODIFIES: phantom_machine_state */ 519void int_23(void); 520/** MODIFIES: phantom_machine_state */ 521void int_24(void); 522/** MODIFIES: phantom_machine_state */ 523void int_25(void); 524/** MODIFIES: phantom_machine_state */ 525void int_26(void); 526/** MODIFIES: phantom_machine_state */ 527void int_27(void); 528/** MODIFIES: phantom_machine_state */ 529void int_28(void); 530/** MODIFIES: phantom_machine_state */ 531void int_29(void); 532/** MODIFIES: phantom_machine_state */ 533void int_2a(void); 534/** MODIFIES: phantom_machine_state */ 535void int_2b(void); 536/** MODIFIES: phantom_machine_state */ 537void int_2c(void); 538/** MODIFIES: phantom_machine_state */ 539void int_2d(void); 540/** MODIFIES: phantom_machine_state */ 541void int_2e(void); 542/** MODIFIES: phantom_machine_state */ 543void int_2f(void); 544 545/** MODIFIES: phantom_machine_state */ 546void int_30(void); 547/** MODIFIES: phantom_machine_state */ 548void int_31(void); 549/** MODIFIES: phantom_machine_state */ 550void int_32(void); 551/** MODIFIES: phantom_machine_state */ 552void int_33(void); 553/** MODIFIES: phantom_machine_state */ 554void int_34(void); 555/** MODIFIES: phantom_machine_state */ 556void int_35(void); 557/** MODIFIES: phantom_machine_state */ 558void int_36(void); 559/** MODIFIES: phantom_machine_state */ 560void int_37(void); 561/** MODIFIES: phantom_machine_state */ 562void int_38(void); 563/** MODIFIES: phantom_machine_state */ 564void int_39(void); 565/** MODIFIES: phantom_machine_state */ 566void int_3a(void); 567/** MODIFIES: phantom_machine_state */ 568void int_3b(void); 569/** MODIFIES: phantom_machine_state */ 570void int_3c(void); 571/** MODIFIES: phantom_machine_state */ 572void int_3d(void); 573/** MODIFIES: phantom_machine_state */ 574void int_3e(void); 575/** MODIFIES: phantom_machine_state */ 576void int_3f(void); 577 578/** MODIFIES: phantom_machine_state */ 579void int_40(void); 580/** MODIFIES: phantom_machine_state */ 581void int_41(void); 582/** MODIFIES: phantom_machine_state */ 583void int_42(void); 584/** MODIFIES: phantom_machine_state */ 585void int_43(void); 586/** MODIFIES: phantom_machine_state */ 587void int_44(void); 588/** MODIFIES: phantom_machine_state */ 589void int_45(void); 590/** MODIFIES: phantom_machine_state */ 591void int_46(void); 592/** MODIFIES: phantom_machine_state */ 593void int_47(void); 594/** MODIFIES: phantom_machine_state */ 595void int_48(void); 596/** MODIFIES: phantom_machine_state */ 597void int_49(void); 598/** MODIFIES: phantom_machine_state */ 599void int_4a(void); 600/** MODIFIES: phantom_machine_state */ 601void int_4b(void); 602/** MODIFIES: phantom_machine_state */ 603void int_4c(void); 604/** MODIFIES: phantom_machine_state */ 605void int_4d(void); 606/** MODIFIES: phantom_machine_state */ 607void int_4e(void); 608/** MODIFIES: phantom_machine_state */ 609void int_4f(void); 610 611/** MODIFIES: phantom_machine_state */ 612void int_50(void); 613/** MODIFIES: phantom_machine_state */ 614void int_51(void); 615/** MODIFIES: phantom_machine_state */ 616void int_52(void); 617/** MODIFIES: phantom_machine_state */ 618void int_53(void); 619/** MODIFIES: phantom_machine_state */ 620void int_54(void); 621/** MODIFIES: phantom_machine_state */ 622void int_55(void); 623/** MODIFIES: phantom_machine_state */ 624void int_56(void); 625/** MODIFIES: phantom_machine_state */ 626void int_57(void); 627/** MODIFIES: phantom_machine_state */ 628void int_58(void); 629/** MODIFIES: phantom_machine_state */ 630void int_59(void); 631/** MODIFIES: phantom_machine_state */ 632void int_5a(void); 633/** MODIFIES: phantom_machine_state */ 634void int_5b(void); 635/** MODIFIES: phantom_machine_state */ 636void int_5c(void); 637/** MODIFIES: phantom_machine_state */ 638void int_5d(void); 639/** MODIFIES: phantom_machine_state */ 640void int_5e(void); 641/** MODIFIES: phantom_machine_state */ 642void int_5f(void); 643 644/** MODIFIES: phantom_machine_state */ 645void int_60(void); 646/** MODIFIES: phantom_machine_state */ 647void int_61(void); 648/** MODIFIES: phantom_machine_state */ 649void int_62(void); 650/** MODIFIES: phantom_machine_state */ 651void int_63(void); 652/** MODIFIES: phantom_machine_state */ 653void int_64(void); 654/** MODIFIES: phantom_machine_state */ 655void int_65(void); 656/** MODIFIES: phantom_machine_state */ 657void int_66(void); 658/** MODIFIES: phantom_machine_state */ 659void int_67(void); 660/** MODIFIES: phantom_machine_state */ 661void int_68(void); 662/** MODIFIES: phantom_machine_state */ 663void int_69(void); 664/** MODIFIES: phantom_machine_state */ 665void int_6a(void); 666/** MODIFIES: phantom_machine_state */ 667void int_6b(void); 668/** MODIFIES: phantom_machine_state */ 669void int_6c(void); 670/** MODIFIES: phantom_machine_state */ 671void int_6d(void); 672/** MODIFIES: phantom_machine_state */ 673void int_6e(void); 674/** MODIFIES: phantom_machine_state */ 675void int_6f(void); 676 677/** MODIFIES: phantom_machine_state */ 678void int_70(void); 679/** MODIFIES: phantom_machine_state */ 680void int_71(void); 681/** MODIFIES: phantom_machine_state */ 682void int_72(void); 683/** MODIFIES: phantom_machine_state */ 684void int_73(void); 685/** MODIFIES: phantom_machine_state */ 686void int_74(void); 687/** MODIFIES: phantom_machine_state */ 688void int_75(void); 689/** MODIFIES: phantom_machine_state */ 690void int_76(void); 691/** MODIFIES: phantom_machine_state */ 692void int_77(void); 693/** MODIFIES: phantom_machine_state */ 694void int_78(void); 695/** MODIFIES: phantom_machine_state */ 696void int_79(void); 697/** MODIFIES: phantom_machine_state */ 698void int_7a(void); 699/** MODIFIES: phantom_machine_state */ 700void int_7b(void); 701/** MODIFIES: phantom_machine_state */ 702void int_7c(void); 703/** MODIFIES: phantom_machine_state */ 704void int_7d(void); 705/** MODIFIES: phantom_machine_state */ 706void int_7e(void); 707/** MODIFIES: phantom_machine_state */ 708void int_7f(void); 709 710/** MODIFIES: phantom_machine_state */ 711void int_80(void); 712/** MODIFIES: phantom_machine_state */ 713void int_81(void); 714/** MODIFIES: phantom_machine_state */ 715void int_82(void); 716/** MODIFIES: phantom_machine_state */ 717void int_83(void); 718/** MODIFIES: phantom_machine_state */ 719void int_84(void); 720/** MODIFIES: phantom_machine_state */ 721void int_85(void); 722/** MODIFIES: phantom_machine_state */ 723void int_86(void); 724/** MODIFIES: phantom_machine_state */ 725void int_87(void); 726/** MODIFIES: phantom_machine_state */ 727void int_88(void); 728/** MODIFIES: phantom_machine_state */ 729void int_89(void); 730/** MODIFIES: phantom_machine_state */ 731void int_8a(void); 732/** MODIFIES: phantom_machine_state */ 733void int_8b(void); 734/** MODIFIES: phantom_machine_state */ 735void int_8c(void); 736/** MODIFIES: phantom_machine_state */ 737void int_8d(void); 738/** MODIFIES: phantom_machine_state */ 739void int_8e(void); 740/** MODIFIES: phantom_machine_state */ 741void int_8f(void); 742 743/** MODIFIES: phantom_machine_state */ 744void int_90(void); 745/** MODIFIES: phantom_machine_state */ 746void int_91(void); 747/** MODIFIES: phantom_machine_state */ 748void int_92(void); 749/** MODIFIES: phantom_machine_state */ 750void int_93(void); 751/** MODIFIES: phantom_machine_state */ 752void int_94(void); 753/** MODIFIES: phantom_machine_state */ 754void int_95(void); 755/** MODIFIES: phantom_machine_state */ 756void int_96(void); 757/** MODIFIES: phantom_machine_state */ 758void int_97(void); 759/** MODIFIES: phantom_machine_state */ 760void int_98(void); 761/** MODIFIES: phantom_machine_state */ 762void int_99(void); 763/** MODIFIES: phantom_machine_state */ 764void int_9a(void); 765/** MODIFIES: phantom_machine_state */ 766void int_9b(void); 767/** MODIFIES: phantom_machine_state */ 768void int_9c(void); 769/** MODIFIES: phantom_machine_state */ 770void int_9d(void); 771/** MODIFIES: phantom_machine_state */ 772void int_9e(void); 773/** MODIFIES: phantom_machine_state */ 774void int_9f(void); 775 776/** MODIFIES: phantom_machine_state */ 777void int_a0(void); 778/** MODIFIES: phantom_machine_state */ 779void int_a1(void); 780/** MODIFIES: phantom_machine_state */ 781void int_a2(void); 782/** MODIFIES: phantom_machine_state */ 783void int_a3(void); 784/** MODIFIES: phantom_machine_state */ 785void int_a4(void); 786/** MODIFIES: phantom_machine_state */ 787void int_a5(void); 788/** MODIFIES: phantom_machine_state */ 789void int_a6(void); 790/** MODIFIES: phantom_machine_state */ 791void int_a7(void); 792/** MODIFIES: phantom_machine_state */ 793void int_a8(void); 794/** MODIFIES: phantom_machine_state */ 795void int_a9(void); 796/** MODIFIES: phantom_machine_state */ 797void int_aa(void); 798/** MODIFIES: phantom_machine_state */ 799void int_ab(void); 800/** MODIFIES: phantom_machine_state */ 801void int_ac(void); 802/** MODIFIES: phantom_machine_state */ 803void int_ad(void); 804/** MODIFIES: phantom_machine_state */ 805void int_ae(void); 806/** MODIFIES: phantom_machine_state */ 807void int_af(void); 808 809/** MODIFIES: phantom_machine_state */ 810void int_b0(void); 811/** MODIFIES: phantom_machine_state */ 812void int_b1(void); 813/** MODIFIES: phantom_machine_state */ 814void int_b2(void); 815/** MODIFIES: phantom_machine_state */ 816void int_b3(void); 817/** MODIFIES: phantom_machine_state */ 818void int_b4(void); 819/** MODIFIES: phantom_machine_state */ 820void int_b5(void); 821/** MODIFIES: phantom_machine_state */ 822void int_b6(void); 823/** MODIFIES: phantom_machine_state */ 824void int_b7(void); 825/** MODIFIES: phantom_machine_state */ 826void int_b8(void); 827/** MODIFIES: phantom_machine_state */ 828void int_b9(void); 829/** MODIFIES: phantom_machine_state */ 830void int_ba(void); 831/** MODIFIES: phantom_machine_state */ 832void int_bb(void); 833/** MODIFIES: phantom_machine_state */ 834void int_bc(void); 835/** MODIFIES: phantom_machine_state */ 836void int_bd(void); 837/** MODIFIES: phantom_machine_state */ 838void int_be(void); 839/** MODIFIES: phantom_machine_state */ 840void int_bf(void); 841 842/** MODIFIES: phantom_machine_state */ 843void int_c0(void); 844/** MODIFIES: phantom_machine_state */ 845void int_c1(void); 846/** MODIFIES: phantom_machine_state */ 847void int_c2(void); 848/** MODIFIES: phantom_machine_state */ 849void int_c3(void); 850/** MODIFIES: phantom_machine_state */ 851void int_c4(void); 852/** MODIFIES: phantom_machine_state */ 853void int_c5(void); 854/** MODIFIES: phantom_machine_state */ 855void int_c6(void); 856/** MODIFIES: phantom_machine_state */ 857void int_c7(void); 858/** MODIFIES: phantom_machine_state */ 859void int_c8(void); 860/** MODIFIES: phantom_machine_state */ 861void int_c9(void); 862/** MODIFIES: phantom_machine_state */ 863void int_ca(void); 864/** MODIFIES: phantom_machine_state */ 865void int_cb(void); 866/** MODIFIES: phantom_machine_state */ 867void int_cc(void); 868/** MODIFIES: phantom_machine_state */ 869void int_cd(void); 870/** MODIFIES: phantom_machine_state */ 871void int_ce(void); 872/** MODIFIES: phantom_machine_state */ 873void int_cf(void); 874 875/** MODIFIES: phantom_machine_state */ 876void int_d0(void); 877/** MODIFIES: phantom_machine_state */ 878void int_d1(void); 879/** MODIFIES: phantom_machine_state */ 880void int_d2(void); 881/** MODIFIES: phantom_machine_state */ 882void int_d3(void); 883/** MODIFIES: phantom_machine_state */ 884void int_d4(void); 885/** MODIFIES: phantom_machine_state */ 886void int_d5(void); 887/** MODIFIES: phantom_machine_state */ 888void int_d6(void); 889/** MODIFIES: phantom_machine_state */ 890void int_d7(void); 891/** MODIFIES: phantom_machine_state */ 892void int_d8(void); 893/** MODIFIES: phantom_machine_state */ 894void int_d9(void); 895/** MODIFIES: phantom_machine_state */ 896void int_da(void); 897/** MODIFIES: phantom_machine_state */ 898void int_db(void); 899/** MODIFIES: phantom_machine_state */ 900void int_dc(void); 901/** MODIFIES: phantom_machine_state */ 902void int_dd(void); 903/** MODIFIES: phantom_machine_state */ 904void int_de(void); 905/** MODIFIES: phantom_machine_state */ 906void int_df(void); 907 908/** MODIFIES: phantom_machine_state */ 909void int_e0(void); 910/** MODIFIES: phantom_machine_state */ 911void int_e1(void); 912/** MODIFIES: phantom_machine_state */ 913void int_e2(void); 914/** MODIFIES: phantom_machine_state */ 915void int_e3(void); 916/** MODIFIES: phantom_machine_state */ 917void int_e4(void); 918/** MODIFIES: phantom_machine_state */ 919void int_e5(void); 920/** MODIFIES: phantom_machine_state */ 921void int_e6(void); 922/** MODIFIES: phantom_machine_state */ 923void int_e7(void); 924/** MODIFIES: phantom_machine_state */ 925void int_e8(void); 926/** MODIFIES: phantom_machine_state */ 927void int_e9(void); 928/** MODIFIES: phantom_machine_state */ 929void int_ea(void); 930/** MODIFIES: phantom_machine_state */ 931void int_eb(void); 932/** MODIFIES: phantom_machine_state */ 933void int_ec(void); 934/** MODIFIES: phantom_machine_state */ 935void int_ed(void); 936/** MODIFIES: phantom_machine_state */ 937void int_ee(void); 938/** MODIFIES: phantom_machine_state */ 939void int_ef(void); 940 941/** MODIFIES: phantom_machine_state */ 942void int_f0(void); 943/** MODIFIES: phantom_machine_state */ 944void int_f1(void); 945/** MODIFIES: phantom_machine_state */ 946void int_f2(void); 947/** MODIFIES: phantom_machine_state */ 948void int_f3(void); 949/** MODIFIES: phantom_machine_state */ 950void int_f4(void); 951/** MODIFIES: phantom_machine_state */ 952void int_f5(void); 953/** MODIFIES: phantom_machine_state */ 954void int_f6(void); 955/** MODIFIES: phantom_machine_state */ 956void int_f7(void); 957/** MODIFIES: phantom_machine_state */ 958void int_f8(void); 959/** MODIFIES: phantom_machine_state */ 960void int_f9(void); 961/** MODIFIES: phantom_machine_state */ 962void int_fa(void); 963/** MODIFIES: phantom_machine_state */ 964void int_fb(void); 965/** MODIFIES: phantom_machine_state */ 966void int_fc(void); 967/** MODIFIES: phantom_machine_state */ 968void int_fd(void); 969/** MODIFIES: phantom_machine_state */ 970void int_fe(void); 971/** MODIFIES: phantom_machine_state */ 972void int_ff(void); 973 974#ifdef CONFIG_VTX 975void handle_vmexit(void); 976#endif 977 978