1/* 2 * oxnas pinctrl driver based on at91 pinctrl driver 3 * 4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 * 6 * Under GPLv2 only 7 */ 8#include <linux/clk.h> 9#include <linux/err.h> 10#include <linux/init.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/of_device.h> 14#include <linux/of_address.h> 15#include <linux/of_irq.h> 16#include <linux/slab.h> 17#include <linux/interrupt.h> 18#include <linux/irq.h> 19#include <linux/irqdomain.h> 20#include <linux/irqchip/chained_irq.h> 21#include <linux/io.h> 22#include <linux/gpio.h> 23#include <linux/pinctrl/machine.h> 24#include <linux/pinctrl/pinconf.h> 25#include <linux/pinctrl/pinctrl.h> 26#include <linux/pinctrl/pinmux.h> 27/* Since we request GPIOs from ourself */ 28#include <linux/pinctrl/consumer.h> 29#include <linux/spinlock.h> 30#include <linux/version.h> 31 32#include "core.h" 33 34#include <mach/utils.h> 35 36#define MAX_NB_GPIO_PER_BANK 32 37#define MAX_GPIO_BANKS 2 38 39struct oxnas_gpio_chip { 40 struct gpio_chip chip; 41 struct pinctrl_gpio_range range; 42 void __iomem *regbase; /* GPIOA/B virtual address */ 43 void __iomem *ctrlbase; /* SYS/SEC_CTRL virtual address */ 44 struct irq_domain *domain; /* associated irq domain */ 45 spinlock_t lock; 46}; 47 48#define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip) 49 50static struct oxnas_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 51 52static int gpio_banks; 53 54#define PULL_UP (1 << 0) 55#define PULL_DOWN (1 << 1) 56#define DEBOUNCE (1 << 2) 57 58/** 59 * struct oxnas_pmx_func - describes pinmux functions 60 * @name: the name of this specific function 61 * @groups: corresponding pin groups 62 * @ngroups: the number of groups 63 */ 64struct oxnas_pmx_func { 65 const char *name; 66 const char **groups; 67 unsigned ngroups; 68}; 69 70enum oxnas_mux { 71 OXNAS_PINMUX_GPIO, 72 OXNAS_PINMUX_FUNC2, 73 OXNAS_PINMUX_FUNC3, 74 OXNAS_PINMUX_FUNC4, 75 OXNAS_PINMUX_DEBUG, 76 OXNAS_PINMUX_ALT, 77}; 78 79enum { 80 INPUT_VALUE = 0, 81 OUTPUT_ENABLE = 4, 82 IRQ_PENDING = 0xC, 83 OUTPUT_VALUE = 0x10, 84 OUTPUT_SET = 0x14, 85 OUTPUT_CLEAR = 0x18, 86 OUTPUT_EN_SET = 0x1C, 87 OUTPUT_EN_CLEAR = 0x20, 88 DEBOUNCE_ENABLE = 0x24, 89 RE_IRQ_ENABLE = 0x28, /* rising edge */ 90 FE_IRQ_ENABLE = 0x2C, /* falling edge */ 91 RE_IRQ_PENDING = 0x30, /* rising edge */ 92 FE_IRQ_PENDING = 0x34, /* falling edge */ 93 CLOCK_DIV = 0x48, 94 PULL_ENABLE = 0x50, 95 PULL_SENSE = 0x54, /* 1 up, 0 down */ 96 97 98 DEBOUNCE_MASK = 0x3FFF0000, 99 /* put hw debounce and soft config at same bit position*/ 100 DEBOUNCE_SHIFT = 16 101}; 102 103enum { 104 PINMUX_SECONDARY_SEL = 0x14, 105 PINMUX_TERTIARY_SEL = 0x8c, 106 PINMUX_QUATERNARY_SEL = 0x94, 107 PINMUX_DEBUG_SEL = 0x9c, 108 PINMUX_ALTERNATIVE_SEL = 0xa4, 109 PINMUX_PULLUP_SEL = 0xac, 110}; 111 112/** 113 * struct oxnas_pmx_pin - describes an pin mux 114 * @bank: the bank of the pin 115 * @pin: the pin number in the @bank 116 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 117 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 118 */ 119struct oxnas_pmx_pin { 120 uint32_t bank; 121 uint32_t pin; 122 enum oxnas_mux mux; 123 unsigned long conf; 124}; 125 126/** 127 * struct oxnas_pin_group - describes an pin group 128 * @name: the name of this specific pin group 129 * @pins_conf: the mux mode for each pin in this group. The size of this 130 * array is the same as pins. 131 * @pins: an array of discrete physical pins used in this group, taken 132 * from the driver-local pin enumeration space 133 * @npins: the number of pins in this group array, i.e. the number of 134 * elements in .pins so we can iterate over that array 135 */ 136struct oxnas_pin_group { 137 const char *name; 138 struct oxnas_pmx_pin *pins_conf; 139 unsigned int *pins; 140 unsigned npins; 141}; 142 143struct oxnas_pinctrl { 144 struct device *dev; 145 struct pinctrl_dev *pctl; 146 147 int nbanks; 148 149 uint32_t *mux_mask; 150 int nmux; 151 152 struct oxnas_pmx_func *functions; 153 int nfunctions; 154 155 struct oxnas_pin_group *groups; 156 int ngroups; 157}; 158 159static const inline struct oxnas_pin_group *oxnas_pinctrl_find_group_by_name( 160 const struct oxnas_pinctrl *info, 161 const char *name) 162{ 163 const struct oxnas_pin_group *grp = NULL; 164 int i; 165 166 for (i = 0; i < info->ngroups; i++) { 167 if (strcmp(info->groups[i].name, name)) 168 continue; 169 170 grp = &info->groups[i]; 171 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, 172 grp->pins[0]); 173 break; 174 } 175 176 return grp; 177} 178 179static int oxnas_get_groups_count(struct pinctrl_dev *pctldev) 180{ 181 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 182 183 return info->ngroups; 184} 185 186static const char *oxnas_get_group_name(struct pinctrl_dev *pctldev, 187 unsigned selector) 188{ 189 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 190 191 return info->groups[selector].name; 192} 193 194static int oxnas_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 195 const unsigned **pins, 196 unsigned *npins) 197{ 198 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 199 200 if (selector >= info->ngroups) 201 return -EINVAL; 202 203 *pins = info->groups[selector].pins; 204 *npins = info->groups[selector].npins; 205 206 return 0; 207} 208 209static void oxnas_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 210 unsigned offset) 211{ 212 seq_printf(s, "%s", dev_name(pctldev->dev)); 213} 214 215static int oxnas_dt_node_to_map(struct pinctrl_dev *pctldev, 216 struct device_node *np, 217 struct pinctrl_map **map, unsigned *num_maps) 218{ 219 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 220 const struct oxnas_pin_group *grp; 221 struct pinctrl_map *new_map; 222 struct device_node *parent; 223 int map_num = 1; 224 int i; 225 226 /* 227 * first find the group of this node and check if we need create 228 * config maps for pins 229 */ 230 grp = oxnas_pinctrl_find_group_by_name(info, np->name); 231 if (!grp) { 232 dev_err(info->dev, "unable to find group for node %s\n", 233 np->name); 234 return -EINVAL; 235 } 236 237 map_num += grp->npins; 238 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 239 GFP_KERNEL); 240 if (!new_map) 241 return -ENOMEM; 242 243 *map = new_map; 244 *num_maps = map_num; 245 246 /* create mux map */ 247 parent = of_get_parent(np); 248 if (!parent) { 249 devm_kfree(pctldev->dev, new_map); 250 return -EINVAL; 251 } 252 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 253 new_map[0].data.mux.function = parent->name; 254 new_map[0].data.mux.group = np->name; 255 of_node_put(parent); 256 257 /* create config map */ 258 new_map++; 259 for (i = 0; i < grp->npins; i++) { 260 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 261 new_map[i].data.configs.group_or_pin = 262 pin_get_name(pctldev, grp->pins[i]); 263 new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 264 new_map[i].data.configs.num_configs = 1; 265 } 266 267 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 268 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 269 270 return 0; 271} 272 273static void oxnas_dt_free_map(struct pinctrl_dev *pctldev, 274 struct pinctrl_map *map, unsigned num_maps) 275{ 276} 277 278static const struct pinctrl_ops oxnas_pctrl_ops = { 279 .get_groups_count = oxnas_get_groups_count, 280 .get_group_name = oxnas_get_group_name, 281 .get_group_pins = oxnas_get_group_pins, 282 .pin_dbg_show = oxnas_pin_dbg_show, 283 .dt_node_to_map = oxnas_dt_node_to_map, 284 .dt_free_map = oxnas_dt_free_map, 285}; 286 287static void __iomem *pin_to_gpioctrl(struct oxnas_pinctrl *info, 288 unsigned int bank) 289{ 290 return gpio_chips[bank]->regbase; 291} 292 293static void __iomem *pin_to_muxctrl(struct oxnas_pinctrl *info, 294 unsigned int bank) 295{ 296 return gpio_chips[bank]->ctrlbase; 297} 298 299 300static inline int pin_to_bank(unsigned pin) 301{ 302 return pin / MAX_NB_GPIO_PER_BANK; 303} 304 305static unsigned pin_to_mask(unsigned int pin) 306{ 307 return 1 << pin; 308} 309 310static void oxnas_mux_disable_interrupt(void __iomem *pio, unsigned mask) 311{ 312 oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask); 313 oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask); 314} 315 316static unsigned oxnas_mux_get_pullup(void __iomem *pio, unsigned pin) 317{ 318 return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) && 319 (readl_relaxed(pio + PULL_SENSE) & BIT(pin)); 320} 321 322static void oxnas_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 323{ 324 if (on) { 325 oxnas_register_set_mask(pio + PULL_SENSE, mask); 326 oxnas_register_set_mask(pio + PULL_ENABLE, mask); 327 } else { 328 oxnas_register_clear_mask(pio + PULL_ENABLE, mask); 329 } 330} 331 332static bool oxnas_mux_get_pulldown(void __iomem *pio, unsigned pin) 333{ 334 return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) && 335 (!(readl_relaxed(pio + PULL_SENSE) & BIT(pin))); 336} 337 338static void oxnas_mux_set_pulldown(void __iomem *pio, unsigned mask, bool on) 339{ 340 if (on) { 341 oxnas_register_clear_mask(pio + PULL_SENSE, mask); 342 oxnas_register_set_mask(pio + PULL_ENABLE, mask); 343 } else { 344 oxnas_register_clear_mask(pio + PULL_ENABLE, mask); 345 }; 346} 347 348/* unfortunately debounce control are shared */ 349static bool oxnas_mux_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 350{ 351 *div = __raw_readl(pio + CLOCK_DIV) & DEBOUNCE_MASK; 352 return __raw_readl(pio + DEBOUNCE_ENABLE) & BIT(pin); 353} 354 355static void oxnas_mux_set_debounce(void __iomem *pio, unsigned mask, 356 bool is_on, u32 div) 357{ 358 if (is_on) { 359 oxnas_register_value_mask(pio + CLOCK_DIV, DEBOUNCE_MASK, div); 360 oxnas_register_set_mask(pio + DEBOUNCE_ENABLE, mask); 361 } else { 362 oxnas_register_clear_mask(pio + DEBOUNCE_ENABLE, mask); 363 } 364} 365 366 367static void oxnas_mux_set_func2(void __iomem *cio, unsigned mask) 368{ 369/* in fact, SECONDARY takes precedence, so clear others is not necessary */ 370 oxnas_register_set_mask(cio + PINMUX_SECONDARY_SEL, mask); 371 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); 372 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); 373 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); 374 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); 375} 376 377static void oxnas_mux_set_func3(void __iomem *cio, unsigned mask) 378{ 379 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); 380 oxnas_register_set_mask(cio + PINMUX_TERTIARY_SEL, mask); 381 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); 382 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); 383 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); 384} 385 386static void oxnas_mux_set_func4(void __iomem *cio, unsigned mask) 387{ 388 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); 389 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); 390 oxnas_register_set_mask(cio + PINMUX_QUATERNARY_SEL, mask); 391 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); 392 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); 393} 394 395static void oxnas_mux_set_func_dbg(void __iomem *cio, unsigned mask) 396{ 397 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); 398 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); 399 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); 400 oxnas_register_set_mask(cio + PINMUX_DEBUG_SEL, mask); 401 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); 402} 403 404static void oxnas_mux_set_func_alt(void __iomem *cio, unsigned mask) 405{ 406 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); 407 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); 408 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); 409 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); 410 oxnas_register_set_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); 411} 412 413static void oxnas_mux_set_gpio(void __iomem *cio, unsigned mask) 414{ 415 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); 416 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); 417 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); 418 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); 419 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); 420} 421 422static enum oxnas_mux oxnas_mux_get_func(void __iomem *cio, unsigned mask) 423{ 424 if (readl_relaxed(cio + PINMUX_SECONDARY_SEL) & mask) 425 return OXNAS_PINMUX_FUNC2; 426 if (readl_relaxed(cio + PINMUX_TERTIARY_SEL) & mask) 427 return OXNAS_PINMUX_FUNC3; 428 if (readl_relaxed(cio + PINMUX_QUATERNARY_SEL) & mask) 429 return OXNAS_PINMUX_FUNC4; 430 if (readl_relaxed(cio + PINMUX_DEBUG_SEL) & mask) 431 return OXNAS_PINMUX_DEBUG; 432 if (readl_relaxed(cio + PINMUX_ALTERNATIVE_SEL) & mask) 433 return OXNAS_PINMUX_ALT; 434 return OXNAS_PINMUX_GPIO; 435} 436 437 438static void oxnas_pin_dbg(const struct device *dev, 439 const struct oxnas_pmx_pin *pin) 440{ 441 if (pin->mux) { 442 dev_dbg(dev, 443 "MF_%c%d configured as periph%c with conf = 0x%lu\n", 444 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', 445 pin->conf); 446 } else { 447 dev_dbg(dev, "MF_%c%d configured as gpio with conf = 0x%lu\n", 448 pin->bank + 'A', pin->pin, pin->conf); 449 } 450} 451 452static int pin_check_config(struct oxnas_pinctrl *info, const char *name, 453 int index, const struct oxnas_pmx_pin *pin) 454{ 455 int mux; 456 457 /* check if it's a valid config */ 458 if (pin->bank >= info->nbanks) { 459 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 460 name, index, pin->bank, info->nbanks); 461 return -EINVAL; 462 } 463 464 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 465 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 466 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 467 return -EINVAL; 468 } 469 /* gpio always allowed */ 470 if (!pin->mux) 471 return 0; 472 473 mux = pin->mux - 1; 474 475 if (mux >= info->nmux) { 476 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 477 name, index, mux, info->nmux); 478 return -EINVAL; 479 } 480 481 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 482 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n", 483 name, index, mux, pin->bank + 'A', pin->pin); 484 return -EINVAL; 485 } 486 487 return 0; 488} 489 490static void oxnas_mux_gpio_enable(void __iomem *cio, void __iomem *pio, 491 unsigned mask, bool input) 492{ 493 oxnas_mux_set_gpio(cio, mask); 494 if (input) 495 writel_relaxed(mask, pio + OUTPUT_EN_CLEAR); 496 else 497 writel_relaxed(mask, pio + OUTPUT_EN_SET); 498} 499 500static void oxnas_mux_gpio_disable(void __iomem *cio, void __iomem *pio, 501 unsigned mask) 502{ 503 /* when switch to other function, gpio is disabled automatically */ 504 return; 505} 506 507static int oxnas_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector, 508 unsigned group) 509{ 510 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 511 const struct oxnas_pmx_pin *pins_conf = info->groups[group].pins_conf; 512 const struct oxnas_pmx_pin *pin; 513 uint32_t npins = info->groups[group].npins; 514 int i, ret; 515 unsigned mask; 516 void __iomem *pio; 517 void __iomem *cio; 518 519 dev_dbg(info->dev, "enable function %s group %s\n", 520 info->functions[selector].name, info->groups[group].name); 521 522 /* first check that all the pins of the group are valid with a valid 523 * paramter */ 524 for (i = 0; i < npins; i++) { 525 pin = &pins_conf[i]; 526 ret = pin_check_config(info, info->groups[group].name, i, pin); 527 if (ret) 528 return ret; 529 } 530 531 for (i = 0; i < npins; i++) { 532 pin = &pins_conf[i]; 533 oxnas_pin_dbg(info->dev, pin); 534 535 pio = pin_to_gpioctrl(info, pin->bank); 536 cio = pin_to_muxctrl(info, pin->bank); 537 538 mask = pin_to_mask(pin->pin); 539 oxnas_mux_disable_interrupt(pio, mask); 540 541 switch (pin->mux) { 542 case OXNAS_PINMUX_GPIO: 543 oxnas_mux_gpio_enable(cio, pio, mask, 1); 544 break; 545 case OXNAS_PINMUX_FUNC2: 546 oxnas_mux_set_func2(cio, mask); 547 break; 548 case OXNAS_PINMUX_FUNC3: 549 oxnas_mux_set_func3(cio, mask); 550 break; 551 case OXNAS_PINMUX_FUNC4: 552 oxnas_mux_set_func4(cio, mask); 553 break; 554 case OXNAS_PINMUX_DEBUG: 555 oxnas_mux_set_func_dbg(cio, mask); 556 break; 557 case OXNAS_PINMUX_ALT: 558 oxnas_mux_set_func_alt(cio, mask); 559 break; 560 } 561 if (pin->mux) 562 oxnas_mux_gpio_disable(cio, pio, mask); 563 } 564 565 return 0; 566} 567 568static int oxnas_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 569{ 570 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 571 572 return info->nfunctions; 573} 574 575static const char *oxnas_pmx_get_func_name(struct pinctrl_dev *pctldev, 576 unsigned selector) 577{ 578 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 579 580 return info->functions[selector].name; 581} 582 583static int oxnas_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 584 const char * const **groups, 585 unsigned * const num_groups) 586{ 587 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 588 589 *groups = info->functions[selector].groups; 590 *num_groups = info->functions[selector].ngroups; 591 592 return 0; 593} 594 595static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev, 596 struct pinctrl_gpio_range *range, 597 unsigned offset) 598{ 599 struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 600 struct oxnas_gpio_chip *oxnas_chip; 601 struct gpio_chip *chip; 602 unsigned mask; 603 604 if (!range) { 605 dev_err(npct->dev, "invalid range\n"); 606 return -EINVAL; 607 } 608 if (!range->gc) { 609 dev_err(npct->dev, "missing GPIO chip in range\n"); 610 return -EINVAL; 611 } 612 chip = range->gc; 613 oxnas_chip = container_of(chip, struct oxnas_gpio_chip, chip); 614 615 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 616 617 mask = 1 << (offset - chip->base); 618 619 dev_dbg(npct->dev, "enable pin %u as MF_%c%d 0x%x\n", 620 offset, 'A' + range->id, offset - chip->base, mask); 621 622 oxnas_mux_set_gpio(oxnas_chip->ctrlbase, mask); 623 624 return 0; 625} 626 627static void oxnas_gpio_disable_free(struct pinctrl_dev *pctldev, 628 struct pinctrl_gpio_range *range, 629 unsigned offset) 630{ 631 struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 632 633 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 634 /* Set the pin to some default state, GPIO is usually default */ 635} 636 637static const struct pinmux_ops oxnas_pmx_ops = { 638 .get_functions_count = oxnas_pmx_get_funcs_count, 639 .get_function_name = oxnas_pmx_get_func_name, 640 .get_function_groups = oxnas_pmx_get_groups, 641 .set_mux = oxnas_pmx_set_mux, 642 .gpio_request_enable = oxnas_gpio_request_enable, 643 .gpio_disable_free = oxnas_gpio_disable_free, 644}; 645 646static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, 647 unsigned pin_id, unsigned long *config) 648{ 649 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 650 void __iomem *pio; 651 unsigned pin; 652 int div; 653 654 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, 655 __LINE__, pin_id, *config); 656 pio = pin_to_gpioctrl(info, pin_to_bank(pin_id)); 657 pin = pin_id % MAX_NB_GPIO_PER_BANK; 658 659 if (oxnas_mux_get_pullup(pio, pin)) 660 *config |= PULL_UP; 661 662 if (oxnas_mux_get_pulldown(pio, pin)) 663 *config |= PULL_DOWN; 664 665 if (oxnas_mux_get_debounce(pio, pin, &div)) 666 *config |= DEBOUNCE | div; 667 return 0; 668} 669 670static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, 671 unsigned pin_id, unsigned long *configs, 672 unsigned num_configs) 673{ 674 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 675 unsigned mask; 676 void __iomem *pio; 677 int i; 678 unsigned long config; 679 680 pio = pin_to_gpioctrl(info, pin_to_bank(pin_id)); 681 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); 682 683 for (i = 0; i < num_configs; i++) { 684 config = configs[i]; 685 686 dev_dbg(info->dev, 687 "%s:%d, pin_id=%d, config=0x%lx", 688 __func__, __LINE__, pin_id, config); 689 690 if ((config & PULL_UP) && (config & PULL_DOWN)) 691 return -EINVAL; 692 693 oxnas_mux_set_pullup(pio, mask, config & PULL_UP); 694 oxnas_mux_set_pulldown(pio, mask, config & PULL_DOWN); 695 oxnas_mux_set_debounce(pio, mask, config & DEBOUNCE, 696 config & DEBOUNCE_MASK); 697 698 } /* for each config */ 699 700 return 0; 701} 702 703static void oxnas_pinconf_dbg_show(struct pinctrl_dev *pctldev, 704 struct seq_file *s, unsigned pin_id) 705{ 706 707} 708 709static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 710 struct seq_file *s, unsigned group) 711{ 712} 713 714static const struct pinconf_ops oxnas_pinconf_ops = { 715 .pin_config_get = oxnas_pinconf_get, 716 .pin_config_set = oxnas_pinconf_set, 717 .pin_config_dbg_show = oxnas_pinconf_dbg_show, 718 .pin_config_group_dbg_show = oxnas_pinconf_group_dbg_show, 719}; 720 721static struct pinctrl_desc oxnas_pinctrl_desc = { 722 .pctlops = &oxnas_pctrl_ops, 723 .pmxops = &oxnas_pmx_ops, 724 .confops = &oxnas_pinconf_ops, 725 .owner = THIS_MODULE, 726}; 727 728static const char *gpio_compat = "plxtech,nas782x-gpio"; 729 730static void oxnas_pinctrl_child_count(struct oxnas_pinctrl *info, 731 struct device_node *np) 732{ 733 struct device_node *child; 734 735 for_each_child_of_node(np, child) { 736 if (of_device_is_compatible(child, gpio_compat)) { 737 info->nbanks++; 738 } else { 739 info->nfunctions++; 740 info->ngroups += of_get_child_count(child); 741 } 742 } 743} 744 745static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl *info, 746 struct device_node *np) 747{ 748 int ret = 0; 749 int size; 750 const __be32 *list; 751 752 list = of_get_property(np, "plxtech,mux-mask", &size); 753 if (!list) { 754 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 755 return -EINVAL; 756 } 757 758 size /= sizeof(*list); 759 if (!size || size % info->nbanks) { 760 dev_err(info->dev, "wrong mux mask array should be by %d\n", 761 info->nbanks); 762 return -EINVAL; 763 } 764 info->nmux = size / info->nbanks; 765 766 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); 767 if (!info->mux_mask) { 768 dev_err(info->dev, "could not alloc mux_mask\n"); 769 return -ENOMEM; 770 } 771 772 ret = of_property_read_u32_array(np, "plxtech,mux-mask", 773 info->mux_mask, size); 774 if (ret) 775 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 776 return ret; 777} 778 779static int oxnas_pinctrl_parse_groups(struct device_node *np, 780 struct oxnas_pin_group *grp, 781 struct oxnas_pinctrl *info, u32 index) 782{ 783 struct oxnas_pmx_pin *pin; 784 int size; 785 const __be32 *list; 786 int i, j; 787 788 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 789 790 /* Initialise group */ 791 grp->name = np->name; 792 793 /* 794 * the binding format is plxtech,pins = <bank pin mux CONFIG ...>, 795 * do sanity check and calculate pins number 796 */ 797 list = of_get_property(np, "plxtech,pins", &size); 798 /* we do not check return since it's safe node passed down */ 799 size /= sizeof(*list); 800 if (!size || size % 4) { 801 dev_err(info->dev, "wrong pins number or pins and configs" 802 " should be divisible by 4\n"); 803 return -EINVAL; 804 } 805 806 grp->npins = size / 4; 807 pin = grp->pins_conf = devm_kzalloc(info->dev, 808 grp->npins * sizeof(struct oxnas_pmx_pin), 809 GFP_KERNEL); 810 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 811 GFP_KERNEL); 812 if (!grp->pins_conf || !grp->pins) 813 return -ENOMEM; 814 815 for (i = 0, j = 0; i < size; i += 4, j++) { 816 pin->bank = be32_to_cpu(*list++); 817 pin->pin = be32_to_cpu(*list++); 818 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 819 pin->mux = be32_to_cpu(*list++); 820 pin->conf = be32_to_cpu(*list++); 821 822 oxnas_pin_dbg(info->dev, pin); 823 pin++; 824 } 825 826 return 0; 827} 828 829static int oxnas_pinctrl_parse_functions(struct device_node *np, 830 struct oxnas_pinctrl *info, u32 index) 831{ 832 struct device_node *child; 833 struct oxnas_pmx_func *func; 834 struct oxnas_pin_group *grp; 835 int ret; 836 static u32 grp_index; 837 u32 i = 0; 838 839 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 840 841 func = &info->functions[index]; 842 843 /* Initialise function */ 844 func->name = np->name; 845 func->ngroups = of_get_child_count(np); 846 if (func->ngroups <= 0) { 847 dev_err(info->dev, "no groups defined\n"); 848 return -EINVAL; 849 } 850 func->groups = devm_kzalloc(info->dev, 851 func->ngroups * sizeof(char *), GFP_KERNEL); 852 if (!func->groups) 853 return -ENOMEM; 854 855 for_each_child_of_node(np, child) { 856 func->groups[i] = child->name; 857 grp = &info->groups[grp_index++]; 858 ret = oxnas_pinctrl_parse_groups(child, grp, info, i++); 859 if (ret) 860 return ret; 861 } 862 863 return 0; 864} 865 866static struct of_device_id oxnas_pinctrl_of_match[] = { 867 { .compatible = "plxtech,nas782x-pinctrl"}, 868 { /* sentinel */ } 869}; 870 871static int oxnas_pinctrl_probe_dt(struct platform_device *pdev, 872 struct oxnas_pinctrl *info) 873{ 874 int ret = 0; 875 int i, j; 876 uint32_t *tmp; 877 struct device_node *np = pdev->dev.of_node; 878 struct device_node *child; 879 880 if (!np) 881 return -ENODEV; 882 883 info->dev = &pdev->dev; 884 885 oxnas_pinctrl_child_count(info, np); 886 887 if (info->nbanks < 1) { 888 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); 889 return -EINVAL; 890 } 891 892 ret = oxnas_pinctrl_mux_mask(info, np); 893 if (ret) 894 return ret; 895 896 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 897 898 dev_dbg(&pdev->dev, "mux-mask\n"); 899 tmp = info->mux_mask; 900 for (i = 0; i < info->nbanks; i++) 901 for (j = 0; j < info->nmux; j++, tmp++) 902 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 903 904 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 905 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 906 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * 907 sizeof(struct oxnas_pmx_func), 908 GFP_KERNEL); 909 if (!info->functions) 910 return -ENOMEM; 911 912 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * 913 sizeof(struct oxnas_pin_group), 914 GFP_KERNEL); 915 if (!info->groups) 916 return -ENOMEM; 917 918 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); 919 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 920 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 921 922 i = 0; 923 924 for_each_child_of_node(np, child) { 925 if (of_device_is_compatible(child, gpio_compat)) 926 continue; 927 ret = oxnas_pinctrl_parse_functions(child, info, i++); 928 if (ret) { 929 dev_err(&pdev->dev, "failed to parse function\n"); 930 return ret; 931 } 932 } 933 934 return 0; 935} 936 937static int oxnas_pinctrl_probe(struct platform_device *pdev) 938{ 939 struct oxnas_pinctrl *info; 940 struct pinctrl_pin_desc *pdesc; 941 int ret, i, j, k; 942 943 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 944 if (!info) 945 return -ENOMEM; 946 947 ret = oxnas_pinctrl_probe_dt(pdev, info); 948 if (ret) 949 return ret; 950 951 /* 952 * We need all the GPIO drivers to probe FIRST, or we will not be able 953 * to obtain references to the struct gpio_chip * for them, and we 954 * need this to proceed. 955 */ 956 for (i = 0; i < info->nbanks; i++) { 957 if (!gpio_chips[i]) { 958 dev_warn(&pdev->dev, 959 "GPIO chip %d not registered yet\n", i); 960 devm_kfree(&pdev->dev, info); 961 return -EPROBE_DEFER; 962 } 963 } 964 965 oxnas_pinctrl_desc.name = dev_name(&pdev->dev); 966 oxnas_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; 967 oxnas_pinctrl_desc.pins = pdesc = 968 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * 969 oxnas_pinctrl_desc.npins, GFP_KERNEL); 970 971 if (!oxnas_pinctrl_desc.pins) 972 return -ENOMEM; 973 974 for (i = 0 , k = 0; i < info->nbanks; i++) { 975 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 976 pdesc->number = k; 977 pdesc->name = kasprintf(GFP_KERNEL, "MF_%c%d", i + 'A', 978 j); 979 pdesc++; 980 } 981 } 982 983 platform_set_drvdata(pdev, info); 984 info->pctl = pinctrl_register(&oxnas_pinctrl_desc, &pdev->dev, info); 985 986 if (!info->pctl) { 987 dev_err(&pdev->dev, "could not register OX820 pinctrl driver\n"); 988 ret = -EINVAL; 989 goto err; 990 } 991 992 /* We will handle a range of GPIO pins */ 993 for (i = 0; i < info->nbanks; i++) 994 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 995 996 dev_info(&pdev->dev, "initialized OX820 pinctrl driver\n"); 997 998 return 0; 999 1000err: 1001 return ret; 1002} 1003 1004static int oxnas_pinctrl_remove(struct platform_device *pdev) 1005{ 1006 struct oxnas_pinctrl *info = platform_get_drvdata(pdev); 1007 1008 pinctrl_unregister(info->pctl); 1009 1010 return 0; 1011} 1012 1013static int oxnas_gpio_request(struct gpio_chip *chip, unsigned offset) 1014{ 1015 /* 1016 * Map back to global GPIO space and request muxing, the direction 1017 * parameter does not matter for this controller. 1018 */ 1019 int gpio = chip->base + offset; 1020 int bank = chip->base / chip->ngpio; 1021 1022 dev_dbg(chip->dev, "%s:%d MF_%c%d(%d)\n", __func__, __LINE__, 1023 'A' + bank, offset, gpio); 1024 1025 return pinctrl_request_gpio(gpio); 1026} 1027 1028static void oxnas_gpio_free(struct gpio_chip *chip, unsigned offset) 1029{ 1030 int gpio = chip->base + offset; 1031 1032 pinctrl_free_gpio(gpio); 1033} 1034 1035static int oxnas_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1036{ 1037 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); 1038 void __iomem *pio = oxnas_gpio->regbase; 1039 1040 writel_relaxed(BIT(offset), pio + OUTPUT_EN_CLEAR); 1041 return 0; 1042} 1043 1044static int oxnas_gpio_get(struct gpio_chip *chip, unsigned offset) 1045{ 1046 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); 1047 void __iomem *pio = oxnas_gpio->regbase; 1048 unsigned mask = 1 << offset; 1049 u32 pdsr; 1050 1051 pdsr = readl_relaxed(pio + INPUT_VALUE); 1052 return (pdsr & mask) != 0; 1053} 1054 1055static void oxnas_gpio_set(struct gpio_chip *chip, unsigned offset, 1056 int val) 1057{ 1058 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); 1059 void __iomem *pio = oxnas_gpio->regbase; 1060 1061 if (val) 1062 writel_relaxed(BIT(offset), pio + OUTPUT_SET); 1063 else 1064 writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR); 1065 1066} 1067 1068static int oxnas_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1069 int val) 1070{ 1071 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); 1072 void __iomem *pio = oxnas_gpio->regbase; 1073 1074 if (val) 1075 writel_relaxed(BIT(offset), pio + OUTPUT_SET); 1076 else 1077 writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR); 1078 1079 writel_relaxed(BIT(offset), pio + OUTPUT_EN_SET); 1080 1081 return 0; 1082} 1083 1084static int oxnas_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 1085{ 1086 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); 1087 int virq; 1088 1089 if (offset < chip->ngpio) 1090 virq = irq_create_mapping(oxnas_gpio->domain, offset); 1091 else 1092 virq = -ENXIO; 1093 1094 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 1095 chip->label, offset + chip->base, virq); 1096 return virq; 1097} 1098 1099#ifdef CONFIG_DEBUG_FS 1100static void oxnas_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1101{ 1102 enum oxnas_mux mode; 1103 int i; 1104 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); 1105 void __iomem *pio = oxnas_gpio->regbase; 1106 void __iomem *cio = oxnas_gpio->ctrlbase; 1107 1108 for (i = 0; i < chip->ngpio; i++) { 1109 unsigned pin = chip->base + i; 1110 unsigned mask = pin_to_mask(pin); 1111 const char *gpio_label; 1112 u32 pdsr; 1113 1114 gpio_label = gpiochip_is_requested(chip, i); 1115 if (!gpio_label) 1116 continue; 1117 /* FIXME */ 1118 mode = oxnas_mux_get_func(cio, mask); 1119 seq_printf(s, "[%s] GPIO%s%d: ", 1120 gpio_label, chip->label, i); 1121 if (mode == OXNAS_PINMUX_GPIO) { 1122 pdsr = readl_relaxed(pio + INPUT_VALUE); 1123 1124 seq_printf(s, "[gpio] %s\n", 1125 pdsr & mask ? 1126 "set" : "clear"); 1127 } else { 1128 seq_printf(s, "[periph %c]\n", 1129 mode + 'A' - 1); 1130 } 1131 } 1132} 1133#else 1134#define oxnas_gpio_dbg_show NULL 1135#endif 1136 1137/* Several AIC controller irqs are dispatched through this GPIO handler. 1138 * To use any AT91_PIN_* as an externally triggered IRQ, first call 1139 * oxnas_set_gpio_input() then maybe enable its glitch filter. 1140 * Then just request_irq() with the pin ID; it works like any ARM IRQ 1141 * handler. 1142 */ 1143 1144static void gpio_irq_mask(struct irq_data *d) 1145{ 1146 struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d); 1147 void __iomem *pio = oxnas_gpio->regbase; 1148 unsigned mask = 1 << d->hwirq; 1149 unsigned type = irqd_get_trigger_type(d); 1150 unsigned long flags; 1151 1152 if (!(type & IRQ_TYPE_EDGE_BOTH)) 1153 return; 1154 1155 spin_lock_irqsave(&oxnas_gpio->lock, flags); 1156 if (type & IRQ_TYPE_EDGE_RISING) 1157 oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask); 1158 if (type & IRQ_TYPE_EDGE_FALLING) 1159 oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask); 1160 spin_unlock_irqrestore(&oxnas_gpio->lock, flags); 1161} 1162 1163static void gpio_irq_unmask(struct irq_data *d) 1164{ 1165 struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d); 1166 void __iomem *pio = oxnas_gpio->regbase; 1167 unsigned mask = 1 << d->hwirq; 1168 unsigned type = irqd_get_trigger_type(d); 1169 unsigned long flags; 1170 1171 if (!(type & IRQ_TYPE_EDGE_BOTH)) 1172 return; 1173 1174 spin_lock_irqsave(&oxnas_gpio->lock, flags); 1175 if (type & IRQ_TYPE_EDGE_RISING) 1176 oxnas_register_set_mask(pio + RE_IRQ_ENABLE, mask); 1177 if (type & IRQ_TYPE_EDGE_FALLING) 1178 oxnas_register_set_mask(pio + FE_IRQ_ENABLE, mask); 1179 spin_unlock_irqrestore(&oxnas_gpio->lock, flags); 1180} 1181 1182 1183static int gpio_irq_type(struct irq_data *d, unsigned type) 1184{ 1185 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) { 1186 pr_warn("OX820: Unsupported type for irq %d\n", 1187 gpio_to_irq(d->irq)); 1188 return -EINVAL; 1189 } 1190 /* seems no way to set trigger type without enable irq, so leave it to unmask time */ 1191 1192 return 0; 1193} 1194 1195static struct irq_chip gpio_irqchip = { 1196 .name = "GPIO", 1197 .irq_disable = gpio_irq_mask, 1198 .irq_mask = gpio_irq_mask, 1199 .irq_unmask = gpio_irq_unmask, 1200 .irq_set_type = gpio_irq_type, 1201}; 1202 1203#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0) 1204static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1205#else 1206static void gpio_irq_handler(struct irq_desc *desc) 1207#endif 1208{ 1209 struct irq_chip *chip = irq_desc_get_chip(desc); 1210 struct irq_data *idata = irq_desc_get_irq_data(desc); 1211 struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(idata); 1212 void __iomem *pio = oxnas_gpio->regbase; 1213 unsigned long isr; 1214 int n; 1215 1216 chained_irq_enter(chip, desc); 1217 for (;;) { 1218 /* TODO: see if it works */ 1219 isr = readl_relaxed(pio + IRQ_PENDING); 1220 if (!isr) 1221 break; 1222 /* acks pending interrupts */ 1223 writel_relaxed(isr, pio + IRQ_PENDING); 1224 1225 for_each_set_bit(n, &isr, BITS_PER_LONG) { 1226 generic_handle_irq(irq_find_mapping(oxnas_gpio->domain, 1227 n)); 1228 } 1229 } 1230 chained_irq_exit(chip, desc); 1231 /* now it may re-trigger */ 1232} 1233 1234/* 1235 * This lock class tells lockdep that GPIO irqs are in a different 1236 * category than their parents, so it won't report false recursion. 1237 */ 1238static struct lock_class_key gpio_lock_class; 1239 1240static int oxnas_gpio_irq_map(struct irq_domain *h, unsigned int virq, 1241 irq_hw_number_t hw) 1242{ 1243 struct oxnas_gpio_chip *oxnas_gpio = h->host_data; 1244 1245 irq_set_lockdep_class(virq, &gpio_lock_class); 1246 1247 irq_set_chip_and_handler(virq, &gpio_irqchip, handle_edge_irq); 1248#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0) 1249 set_irq_flags(virq, IRQF_VALID); 1250#endif 1251 irq_set_chip_data(virq, oxnas_gpio); 1252 1253 return 0; 1254} 1255 1256static int oxnas_gpio_irq_domain_xlate(struct irq_domain *d, 1257 struct device_node *ctrlr, 1258 const u32 *intspec, 1259 unsigned int intsize, 1260 irq_hw_number_t *out_hwirq, 1261 unsigned int *out_type) 1262{ 1263 struct oxnas_gpio_chip *oxnas_gpio = d->host_data; 1264 int ret; 1265 int pin = oxnas_gpio->chip.base + intspec[0]; 1266 1267 if (WARN_ON(intsize < 2)) 1268 return -EINVAL; 1269 *out_hwirq = intspec[0]; 1270 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; 1271 1272 ret = gpio_request(pin, ctrlr->full_name); 1273 if (ret) 1274 return ret; 1275 1276 ret = gpio_direction_input(pin); 1277 if (ret) 1278 return ret; 1279 1280 return 0; 1281} 1282 1283static struct irq_domain_ops oxnas_gpio_ops = { 1284 .map = oxnas_gpio_irq_map, 1285 .xlate = oxnas_gpio_irq_domain_xlate, 1286}; 1287 1288static int oxnas_gpio_of_irq_setup(struct device_node *node, 1289 struct oxnas_gpio_chip *oxnas_gpio, 1290 unsigned int irq) 1291{ 1292 /* Disable irqs of this controller */ 1293 writel_relaxed(0, oxnas_gpio->regbase + RE_IRQ_ENABLE); 1294 writel_relaxed(0, oxnas_gpio->regbase + FE_IRQ_ENABLE); 1295 1296 /* Setup irq domain */ 1297 oxnas_gpio->domain = irq_domain_add_linear(node, oxnas_gpio->chip.ngpio, 1298 &oxnas_gpio_ops, oxnas_gpio); 1299 if (!oxnas_gpio->domain) 1300 panic("oxnas_gpio: couldn't allocate irq domain (DT).\n"); 1301 1302 irq_set_chip_data(irq, oxnas_gpio); 1303 irq_set_chained_handler(irq, gpio_irq_handler); 1304 1305 return 0; 1306} 1307 1308/* This structure is replicated for each GPIO block allocated at probe time */ 1309static struct gpio_chip oxnas_gpio_template = { 1310 .request = oxnas_gpio_request, 1311 .free = oxnas_gpio_free, 1312 .direction_input = oxnas_gpio_direction_input, 1313 .get = oxnas_gpio_get, 1314 .direction_output = oxnas_gpio_direction_output, 1315 .set = oxnas_gpio_set, 1316 .to_irq = oxnas_gpio_to_irq, 1317 .dbg_show = oxnas_gpio_dbg_show, 1318 .can_sleep = 0, 1319 .ngpio = MAX_NB_GPIO_PER_BANK, 1320}; 1321 1322static struct of_device_id oxnas_gpio_of_match[] = { 1323 { .compatible = "plxtech,nas782x-gpio"}, 1324 { /* sentinel */ } 1325}; 1326 1327static int oxnas_gpio_probe(struct platform_device *pdev) 1328{ 1329 struct device_node *np = pdev->dev.of_node; 1330 struct resource *res; 1331 struct oxnas_gpio_chip *oxnas_chip = NULL; 1332 struct gpio_chip *chip; 1333 struct pinctrl_gpio_range *range; 1334 int ret = 0; 1335 int irq, i; 1336 int alias_idx = of_alias_get_id(np, "gpio"); 1337 uint32_t ngpio; 1338 char **names; 1339 1340 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 1341 if (gpio_chips[alias_idx]) { 1342 ret = -EBUSY; 1343 goto err; 1344 } 1345 1346 irq = platform_get_irq(pdev, 0); 1347 if (irq < 0) { 1348 ret = irq; 1349 goto err; 1350 } 1351 1352 oxnas_chip = devm_kzalloc(&pdev->dev, sizeof(*oxnas_chip), GFP_KERNEL); 1353 if (!oxnas_chip) { 1354 ret = -ENOMEM; 1355 goto err; 1356 } 1357 1358 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1359 oxnas_chip->regbase = devm_ioremap_resource(&pdev->dev, res); 1360 if (IS_ERR(oxnas_chip->regbase)) { 1361 ret = PTR_ERR(oxnas_chip->regbase); 1362 goto err; 1363 } 1364 1365 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1366 oxnas_chip->ctrlbase = devm_ioremap_resource(&pdev->dev, res); 1367 if (IS_ERR(oxnas_chip->ctrlbase)) { 1368 ret = PTR_ERR(oxnas_chip->ctrlbase); 1369 goto err; 1370 } 1371 1372 oxnas_chip->chip = oxnas_gpio_template; 1373 1374 spin_lock_init(&oxnas_chip->lock); 1375 1376 chip = &oxnas_chip->chip; 1377 chip->of_node = np; 1378 chip->label = dev_name(&pdev->dev); 1379 chip->dev = &pdev->dev; 1380 chip->owner = THIS_MODULE; 1381 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 1382 1383 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 1384 if (ngpio > MAX_NB_GPIO_PER_BANK) 1385 pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n", 1386 alias_idx, MAX_NB_GPIO_PER_BANK, 1387 MAX_NB_GPIO_PER_BANK); 1388 else 1389 chip->ngpio = ngpio; 1390 } 1391 1392 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, 1393 GFP_KERNEL); 1394 1395 if (!names) { 1396 ret = -ENOMEM; 1397 goto err; 1398 } 1399 1400 for (i = 0; i < chip->ngpio; i++) 1401 names[i] = kasprintf(GFP_KERNEL, "MF_%c%d", alias_idx + 'A', i); 1402 1403 chip->names = (const char *const *)names; 1404 1405 range = &oxnas_chip->range; 1406 range->name = chip->label; 1407 range->id = alias_idx; 1408 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 1409 1410 range->npins = chip->ngpio; 1411 range->gc = chip; 1412 1413 ret = gpiochip_add(chip); 1414 if (ret) 1415 goto err; 1416 1417 gpio_chips[alias_idx] = oxnas_chip; 1418 gpio_banks = max(gpio_banks, alias_idx + 1); 1419 1420 oxnas_gpio_of_irq_setup(np, oxnas_chip, irq); 1421 1422 dev_info(&pdev->dev, "at address %p\n", oxnas_chip->regbase); 1423 1424 return 0; 1425err: 1426 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 1427 1428 return ret; 1429} 1430 1431static struct platform_driver oxnas_gpio_driver = { 1432 .driver = { 1433 .name = "gpio-oxnas", 1434 .owner = THIS_MODULE, 1435 .of_match_table = of_match_ptr(oxnas_gpio_of_match), 1436 }, 1437 .probe = oxnas_gpio_probe, 1438}; 1439 1440static struct platform_driver oxnas_pinctrl_driver = { 1441 .driver = { 1442 .name = "pinctrl-oxnas", 1443 .owner = THIS_MODULE, 1444 .of_match_table = of_match_ptr(oxnas_pinctrl_of_match), 1445 }, 1446 .probe = oxnas_pinctrl_probe, 1447 .remove = oxnas_pinctrl_remove, 1448}; 1449 1450static int __init oxnas_pinctrl_init(void) 1451{ 1452 int ret; 1453 1454 ret = platform_driver_register(&oxnas_gpio_driver); 1455 if (ret) 1456 return ret; 1457 return platform_driver_register(&oxnas_pinctrl_driver); 1458} 1459arch_initcall(oxnas_pinctrl_init); 1460 1461static void __exit oxnas_pinctrl_exit(void) 1462{ 1463 platform_driver_unregister(&oxnas_pinctrl_driver); 1464} 1465 1466module_exit(oxnas_pinctrl_exit); 1467MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>"); 1468MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver"); 1469MODULE_LICENSE("GPL v2"); 1470