1/*
2 *  NAND flash driver for the MikroTik RouterBOARD 750
3 *
4 *  Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 *  This program is free software; you can redistribute it and/or modify it
7 *  under the terms of the GNU General Public License version 2 as published
8 *  by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/mtd/nand.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19
20#include <asm/mach-ath79/ar71xx_regs.h>
21#include <asm/mach-ath79/ath79.h>
22#include <asm/mach-ath79/mach-rb750.h>
23
24#define DRV_NAME	"rb750-nand"
25#define DRV_VERSION	"0.1.0"
26#define DRV_DESC	"NAND flash driver for the RouterBOARD 750"
27
28#define RB750_NAND_IO0		BIT(RB750_GPIO_NAND_IO0)
29#define RB750_NAND_ALE		BIT(RB750_GPIO_NAND_ALE)
30#define RB750_NAND_CLE		BIT(RB750_GPIO_NAND_CLE)
31#define RB750_NAND_NRE		BIT(RB750_GPIO_NAND_NRE)
32#define RB750_NAND_NWE		BIT(RB750_GPIO_NAND_NWE)
33#define RB750_NAND_RDY		BIT(RB750_GPIO_NAND_RDY)
34
35#define RB750_NAND_DATA_SHIFT	1
36#define RB750_NAND_DATA_BITS	(0xff << RB750_NAND_DATA_SHIFT)
37#define RB750_NAND_INPUT_BITS	(RB750_NAND_DATA_BITS | RB750_NAND_RDY)
38#define RB750_NAND_OUTPUT_BITS	(RB750_NAND_ALE | RB750_NAND_CLE | \
39				 RB750_NAND_NRE | RB750_NAND_NWE)
40
41struct rb750_nand_info {
42	struct nand_chip	chip;
43	struct mtd_info		mtd;
44	struct rb7xx_nand_platform_data *pdata;
45};
46
47static inline struct rb750_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
48{
49	return container_of(mtd, struct rb750_nand_info, mtd);
50}
51
52/*
53 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
54 * will not be able to find the kernel that we load.
55 */
56static struct nand_ecclayout rb750_nand_ecclayout = {
57	.eccbytes	= 6,
58	.eccpos		= { 8, 9, 10, 13, 14, 15 },
59	.oobavail	= 9,
60	.oobfree	= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
61};
62
63static struct mtd_partition rb750_nand_partitions[] = {
64	{
65		.name	= "booter",
66		.offset	= 0,
67		.size	= (256 * 1024),
68		.mask_flags = MTD_WRITEABLE,
69	}, {
70		.name	= "kernel",
71		.offset	= (256 * 1024),
72		.size	= (4 * 1024 * 1024) - (256 * 1024),
73	}, {
74		.name	= "rootfs",
75		.offset	= MTDPART_OFS_NXTBLK,
76		.size	= MTDPART_SIZ_FULL,
77	},
78};
79
80static void rb750_nand_write(const u8 *buf, unsigned len)
81{
82	void __iomem *base = ath79_gpio_base;
83	u32 out;
84	u32 t;
85	unsigned i;
86
87	/* set data lines to output mode */
88	t = __raw_readl(base + AR71XX_GPIO_REG_OE);
89	__raw_writel(t | RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE);
90
91	out = __raw_readl(base + AR71XX_GPIO_REG_OUT);
92	out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE);
93	for (i = 0; i != len; i++) {
94		u32 data;
95
96		data = buf[i];
97		data <<= RB750_NAND_DATA_SHIFT;
98		data |= out;
99		__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
100
101		__raw_writel(data | RB750_NAND_NWE, base + AR71XX_GPIO_REG_OUT);
102		/* flush write */
103		__raw_readl(base + AR71XX_GPIO_REG_OUT);
104	}
105
106	/* set data lines to input mode */
107	t = __raw_readl(base + AR71XX_GPIO_REG_OE);
108	__raw_writel(t & ~RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE);
109	/* flush write */
110	__raw_readl(base + AR71XX_GPIO_REG_OE);
111}
112
113static void rb750_nand_read(u8 *read_buf, unsigned len)
114{
115	void __iomem *base = ath79_gpio_base;
116	unsigned i;
117
118	for (i = 0; i < len; i++) {
119		u8 data;
120
121		/* activate RE line */
122		__raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_CLEAR);
123		/* flush write */
124		__raw_readl(base + AR71XX_GPIO_REG_CLEAR);
125
126		/* read input lines */
127		data = __raw_readl(base + AR71XX_GPIO_REG_IN) >>
128		       RB750_NAND_DATA_SHIFT;
129
130		/* deactivate RE line */
131		__raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_SET);
132
133		read_buf[i] = data;
134	}
135}
136
137static void rb750_nand_select_chip(struct mtd_info *mtd, int chip)
138{
139	struct rb750_nand_info *rbinfo = mtd_to_rbinfo(mtd);
140	void __iomem *base = ath79_gpio_base;
141	u32 t;
142
143	if (chip >= 0) {
144		rbinfo->pdata->enable_pins();
145
146		/* set input mode for data lines */
147		t = __raw_readl(base + AR71XX_GPIO_REG_OE);
148		__raw_writel(t & ~RB750_NAND_INPUT_BITS,
149			     base + AR71XX_GPIO_REG_OE);
150
151		/* deactivate RE and WE lines */
152		__raw_writel(RB750_NAND_NRE | RB750_NAND_NWE,
153			     base + AR71XX_GPIO_REG_SET);
154		/* flush write */
155		(void) __raw_readl(base + AR71XX_GPIO_REG_SET);
156
157		/* activate CE line */
158		__raw_writel(rbinfo->pdata->nce_line,
159			     base + AR71XX_GPIO_REG_CLEAR);
160	} else {
161		/* deactivate CE line */
162		__raw_writel(rbinfo->pdata->nce_line,
163			     base + AR71XX_GPIO_REG_SET);
164		/* flush write */
165		(void) __raw_readl(base + AR71XX_GPIO_REG_SET);
166
167		t = __raw_readl(base + AR71XX_GPIO_REG_OE);
168		__raw_writel(t | RB750_NAND_IO0 | RB750_NAND_RDY,
169			     base + AR71XX_GPIO_REG_OE);
170
171		rbinfo->pdata->disable_pins();
172	}
173}
174
175static int rb750_nand_dev_ready(struct mtd_info *mtd)
176{
177	void __iomem *base = ath79_gpio_base;
178
179	return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB750_NAND_RDY);
180}
181
182static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
183				unsigned int ctrl)
184{
185	if (ctrl & NAND_CTRL_CHANGE) {
186		void __iomem *base = ath79_gpio_base;
187		u32 t;
188
189		t = __raw_readl(base + AR71XX_GPIO_REG_OUT);
190
191		t &= ~(RB750_NAND_CLE | RB750_NAND_ALE);
192		t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0;
193		t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0;
194
195		__raw_writel(t, base + AR71XX_GPIO_REG_OUT);
196		/* flush write */
197		__raw_readl(base + AR71XX_GPIO_REG_OUT);
198	}
199
200	if (cmd != NAND_CMD_NONE) {
201		u8 t = cmd;
202		rb750_nand_write(&t, 1);
203	}
204}
205
206static u8 rb750_nand_read_byte(struct mtd_info *mtd)
207{
208	u8 data = 0;
209	rb750_nand_read(&data, 1);
210	return data;
211}
212
213static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
214{
215	rb750_nand_read(buf, len);
216}
217
218static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
219{
220	rb750_nand_write(buf, len);
221}
222
223static void __init rb750_nand_gpio_init(struct rb750_nand_info *info)
224{
225	void __iomem *base = ath79_gpio_base;
226	u32 out;
227	u32 t;
228
229	out = __raw_readl(base + AR71XX_GPIO_REG_OUT);
230
231	/* setup output levels */
232	__raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE,
233		     base + AR71XX_GPIO_REG_SET);
234
235	__raw_writel(RB750_NAND_ALE | RB750_NAND_CLE,
236		     base + AR71XX_GPIO_REG_CLEAR);
237
238	/* setup input lines */
239	t = __raw_readl(base + AR71XX_GPIO_REG_OE);
240	__raw_writel(t & ~(RB750_NAND_INPUT_BITS), base + AR71XX_GPIO_REG_OE);
241
242	/* setup output lines */
243	t = __raw_readl(base + AR71XX_GPIO_REG_OE);
244	t |= RB750_NAND_OUTPUT_BITS;
245	t |= info->pdata->nce_line;
246	__raw_writel(t, base + AR71XX_GPIO_REG_OE);
247
248	info->pdata->latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0);
249}
250
251static int rb750_nand_probe(struct platform_device *pdev)
252{
253	struct rb750_nand_info	*info;
254	struct rb7xx_nand_platform_data *pdata;
255	int ret;
256
257	printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
258
259	pdata = pdev->dev.platform_data;
260	if (!pdata)
261		return -EINVAL;
262
263	info = kzalloc(sizeof(*info), GFP_KERNEL);
264	if (!info)
265		return -ENOMEM;
266
267	info->chip.priv	= &info;
268	info->mtd.priv	= &info->chip;
269	info->mtd.owner	= THIS_MODULE;
270
271	info->chip.select_chip	= rb750_nand_select_chip;
272	info->chip.cmd_ctrl	= rb750_nand_cmd_ctrl;
273	info->chip.dev_ready	= rb750_nand_dev_ready;
274	info->chip.read_byte	= rb750_nand_read_byte;
275	info->chip.write_buf	= rb750_nand_write_buf;
276	info->chip.read_buf	= rb750_nand_read_buf;
277
278	info->chip.chip_delay	= 25;
279	info->chip.ecc.mode	= NAND_ECC_SOFT;
280
281	info->pdata = pdata;
282
283	platform_set_drvdata(pdev, info);
284
285	rb750_nand_gpio_init(info);
286
287	ret = nand_scan_ident(&info->mtd, 1, NULL);
288	if (ret) {
289		ret = -ENXIO;
290		goto err_free_info;
291	}
292
293	if (info->mtd.writesize == 512)
294		info->chip.ecc.layout = &rb750_nand_ecclayout;
295
296	ret = nand_scan_tail(&info->mtd);
297	if (ret) {
298		return -ENXIO;
299		goto err_set_drvdata;
300	}
301
302	ret = mtd_device_register(&info->mtd, rb750_nand_partitions,
303				 ARRAY_SIZE(rb750_nand_partitions));
304	if (ret)
305		goto err_release_nand;
306
307	return 0;
308
309err_release_nand:
310	nand_release(&info->mtd);
311err_set_drvdata:
312	platform_set_drvdata(pdev, NULL);
313err_free_info:
314	kfree(info);
315	return ret;
316}
317
318static int rb750_nand_remove(struct platform_device *pdev)
319{
320	struct rb750_nand_info *info = platform_get_drvdata(pdev);
321
322	nand_release(&info->mtd);
323	platform_set_drvdata(pdev, NULL);
324	kfree(info);
325
326	return 0;
327}
328
329static struct platform_driver rb750_nand_driver = {
330	.probe	= rb750_nand_probe,
331	.remove	= rb750_nand_remove,
332	.driver	= {
333		.name	= DRV_NAME,
334		.owner	= THIS_MODULE,
335	},
336};
337
338static int __init rb750_nand_init(void)
339{
340	return platform_driver_register(&rb750_nand_driver);
341}
342
343static void __exit rb750_nand_exit(void)
344{
345	platform_driver_unregister(&rb750_nand_driver);
346}
347
348module_init(rb750_nand_init);
349module_exit(rb750_nand_exit);
350
351MODULE_DESCRIPTION(DRV_DESC);
352MODULE_VERSION(DRV_VERSION);
353MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
354MODULE_LICENSE("GPL v2");
355