1/***************************************************************************** 2 ** FILE NAME : ifxusb_plat.h 3 ** PROJECT : IFX USB sub-system V3 4 ** MODULES : IFX USB sub-system Host and Device driver 5 ** SRC VERSION : 3.2 6 ** DATE : 1/Jan/2011 7 ** AUTHOR : Chen, Howard 8 ** DESCRIPTION : This file contains the Platform Specific constants, interfaces 9 ** (functions and macros). 10 ** FUNCTIONS : 11 ** COMPILER : gcc 12 ** REFERENCE : Synopsys DWC-OTG Driver 2.7 13 ** COPYRIGHT : Copyright (c) 2010 14 ** LANTIQ DEUTSCHLAND GMBH, 15 ** Am Campeon 3, 85579 Neubiberg, Germany 16 ** 17 ** This program is free software; you can redistribute it and/or modify 18 ** it under the terms of the GNU General Public License as published by 19 ** the Free Software Foundation; either version 2 of the License, or 20 ** (at your option) any later version. 21 ** 22 ** Version Control Section ** 23 ** $Author$ 24 ** $Date$ 25 ** $Revisions$ 26 ** $Log$ Revision history 27 *****************************************************************************/ 28 29/* 30 * This file contains code fragments from Synopsys HS OTG Linux Software Driver. 31 * For this code the following notice is applicable: 32 * 33 * ========================================================================== 34 * 35 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, 36 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless 37 * otherwise expressly agreed to in writing between Synopsys and you. 38 * 39 * The Software IS NOT an item of Licensed Software or Licensed Product under 40 * any End User Software License Agreement or Agreement for Licensed Product 41 * with Synopsys or any supplement thereto. You are permitted to use and 42 * redistribute this Software in source and binary forms, with or without 43 * modification, provided that redistributions of source code must retain this 44 * notice. You may not view, use, disclose, copy or distribute this file or 45 * any information contained herein except pursuant to this license grant from 46 * Synopsys. If you do not agree with this notice, including the disclaimer 47 * below, then you are not authorized to use the Software. 48 * 49 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS 50 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, 53 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 54 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 55 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 56 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 59 * DAMAGE. 60 * ========================================================================== */ 61 62 63/*! 64 \defgroup IFXUSB_PLATEFORM_DEFINITION Platform Specific constants, interfaces (functions and macros). 65 \ingroup IFXUSB_DRIVER_V3 66 \brief Maintain plateform specific definitions and macros in this file. 67 Each plateform has its own definition zone. 68 */ 69 70/*! 71 \defgroup IFXUSB_PLATEFORM_MEM_ADDR Definition of memory address and size and default parameters 72 \ingroup IFXUSB_PLATEFORM_DEFINITION 73 */ 74 75/*! 76 \defgroup IFXUSB_DBG_ROUTINE Routines for debug message 77 \ingroup IFXUSB_PLATEFORM_DEFINITION 78 */ 79 80 81/*! \file ifxusb_plat.h 82 \ingroup IFXUSB_DRIVER_V3 83 \brief This file contains the Platform Specific constants, interfaces (functions and macros). 84*/ 85 86#if !defined(__IFXUSB_PLAT_H__) 87#define __IFXUSB_PLAT_H__ 88 89 90#include <linux/types.h> 91#include <linux/slab.h> 92#include <linux/list.h> 93#include <linux/delay.h> 94#include <asm/io.h> 95 96 97#define IFXUSB_IOMEM_SIZE 0x00001000 98#define IFXUSB_FIFOMEM_SIZE 0x00010000 99#define IFXUSB_FIFODBG_SIZE 0x00020000 100 101 102 103/*! 104 \addtogroup IFXUSB_PLATEFORM_MEM_ADDR 105 */ 106/*@{*/ 107#if defined(__UEIP__) 108 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) 109 #define IFXUSB_IRQ 62 110 #define IFXUSB_IOMEM_BASE 0x1e101000 111 #define IFXUSB_FIFOMEM_BASE 0x1e120000 112 #define IFXUSB_FIFODBG_BASE 0x1e140000 113 #define IFXUSB_OC_IRQ 159 114 115 #ifndef DANUBE_RCU_BASE_ADDR 116 #define DANUBE_RCU_BASE_ADDR (0xBF203000) 117 #endif 118 119 #ifndef DANUBE_CGU 120 #define DANUBE_CGU (0xBF103000) 121 #endif 122 #ifndef DANUBE_CGU_IFCCR 123 #define DANUBE_CGU_IFCCR ((volatile unsigned long *)(DANUBE_CGU+ 0x0018)) 124 #endif 125 #ifndef DANUBE_PMU 126 #define DANUBE_PMU (KSEG1+0x1F102000) 127 #endif 128 #ifndef DANUBE_PMU_PWDCR 129 #define DANUBE_PMU_PWDCR ((volatile unsigned long *)(DANUBE_PMU+0x001C)) 130 #endif 131 132 #ifndef DANUBE_GPIO_P0_OUT 133 #define DANUBE_GPIO_P0_OUT (0xBF103000+0x10) 134 #define DANUBE_GPIO_P0_DIR (0xBF103000+0x18) 135 #define DANUBE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) 136 #define DANUBE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) 137 #define DANUBE_GPIO_P0_OD (0xBF103000+0x24) 138 #define DANUBE_GPIO_P0_PUDSEL (0xBF103000+0x2C) 139 #define DANUBE_GPIO_P0_PUDEN (0xBF103000+0x30) 140 #define DANUBE_GPIO_P1_OUT (0xBF103000+0x40) 141 #define DANUBE_GPIO_P1_DIR (0xBF103000+0x48) 142 #define DANUBE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) 143 #define DANUBE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) 144 #define DANUBE_GPIO_P1_OD (0xBF103000+0x54) 145 #define DANUBE_GPIO_P1_PUDSEL (0xBF103000+0x5C) 146 #define DANUBE_GPIO_P1_PUDEN (0xBF103000+0x60) 147 #endif 148 149 #define DANUBE_RCU_USBCFG ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18)) 150 #define DANUBE_RCU_RESET ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10)) 151 #define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device 152 #define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end 153 #define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end 154 155 #define default_param_dma_burst_size 4 156 157 #define default_param_speed IFXUSB_PARAM_SPEED_HIGH 158 159 #define default_param_max_transfer_size -1 //(Max, hwcfg) 160 #define default_param_max_packet_count -1 //(Max, hwcfg) 161 #define default_param_phy_utmi_width 16 162 163 #define default_param_turn_around_time_hs 4 164 #define default_param_turn_around_time_fs 4 165 #define default_param_timeout_cal_hs -1 //(NoChange) 166 #define default_param_timeout_cal_fs -1 //(NoChange) 167 168 #define default_param_data_fifo_size -1 //(Max, hwcfg) 169 170 #ifdef __IS_HOST__ 171 #define default_param_host_channels -1 //(Max, hwcfg) 172 #define default_param_rx_fifo_size 640 173 #define default_param_nperio_tx_fifo_size 640 174 #define default_param_perio_tx_fifo_size 768 175 #endif //__IS_HOST__ 176 177 #ifdef __IS_DEVICE__ 178 #ifdef __DED_INTR__ 179// #define default_param_rx_fifo_size 1024 180// #define default_param_nperio_tx_fifo_size 1016 181// #define default_param_perio_tx_fifo_size_01 8 182 #define default_param_rx_fifo_size 1008 183 #define default_param_nperio_tx_fifo_size 1008 184 #define default_param_perio_tx_fifo_size_01 32 185 #else 186 #define default_param_rx_fifo_size 1024 187 #define default_param_nperio_tx_fifo_size 1024 188 #define default_param_perio_tx_fifo_size_01 0 189 #endif 190 #define default_param_perio_tx_fifo_size_02 0 191 #define default_param_perio_tx_fifo_size_03 0 192 #define default_param_perio_tx_fifo_size_04 0 193 #define default_param_perio_tx_fifo_size_05 0 194 #define default_param_perio_tx_fifo_size_06 0 195 #define default_param_perio_tx_fifo_size_07 0 196 #define default_param_perio_tx_fifo_size_08 0 197 #define default_param_perio_tx_fifo_size_09 0 198 #define default_param_perio_tx_fifo_size_10 0 199 #define default_param_perio_tx_fifo_size_11 0 200 #define default_param_perio_tx_fifo_size_12 0 201 #define default_param_perio_tx_fifo_size_13 0 202 #define default_param_perio_tx_fifo_size_14 0 203 #define default_param_perio_tx_fifo_size_15 0 204 #endif //__IS_DEVICE__ 205 206 #elif defined(__IS_AMAZON_SE__) 207 //#include <asm/amazon_se/amazon_se.h> 208 //#include <asm/amazon_se/irq.h> 209 210 #define IFXUSB_IRQ 39 211 #define IFXUSB_IOMEM_BASE 0x1e101000 212 #define IFXUSB_FIFOMEM_BASE 0x1e120000 213 #define IFXUSB_FIFODBG_BASE 0x1e140000 214 #define IFXUSB_OC_IRQ 20 215 216 #ifndef AMAZON_SE_RCU_BASE_ADDR 217 #define AMAZON_SE_RCU_BASE_ADDR (0xBF203000) 218 #endif 219 #define AMAZON_SE_RCU_USBCFG ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18)) 220 #define AMAZON_SE_RCU_RESET ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10)) 221 #define AMAZON_SE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device 222 #define AMAZON_SE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end 223 #define AMAZON_SE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end 224 225 #ifndef AMAZON_SE_GPIO_P0_OUT 226 #define AMAZON_SE_GPIO_P0_OUT (0xBF103000+0x10) 227 #define AMAZON_SE_GPIO_P0_DIR (0xBF103000+0x18) 228 #define AMAZON_SE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) 229 #define AMAZON_SE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) 230 #define AMAZON_SE_GPIO_P0_OD (0xBF103000+0x24) 231 #define AMAZON_SE_GPIO_P0_PUDSEL (0xBF103000+0x2C) 232 #define AMAZON_SE_GPIO_P0_PUDEN (0xBF103000+0x30) 233 #define AMAZON_SE_GPIO_P1_OUT (0xBF103000+0x40) 234 #define AMAZON_SE_GPIO_P1_DIR (0xBF103000+0x48) 235 #define AMAZON_SE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) 236 #define AMAZON_SE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) 237 #define AMAZON_SE_GPIO_P1_OD (0xBF103000+0x54) 238 #define AMAZON_SE_GPIO_P1_PUDSEL (0xBF103000+0x5C) 239 #define AMAZON_SE_GPIO_P1_PUDEN (0xBF103000+0x60) 240 #endif 241 242 #ifndef AMAZON_SE_CGU 243 #define AMAZON_SE_CGU (0xBF103000) 244 #endif 245 #ifndef AMAZON_SE_CGU_IFCCR 246 #define AMAZON_SE_CGU_IFCCR ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018)) 247 #endif 248 #ifndef AMAZON_SE_PMU 249 #define AMAZON_SE_PMU (KSEG1+0x1F102000) 250 #endif 251 #ifndef AMAZON_SE_PMU_PWDCR 252 #define AMAZON_SE_PMU_PWDCR ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C)) 253 #endif 254 255 #define default_param_dma_burst_size 4 256 257 #define default_param_speed IFXUSB_PARAM_SPEED_HIGH 258 259 #define default_param_max_transfer_size -1 //(Max, hwcfg) 260 #define default_param_max_packet_count -1 //(Max, hwcfg) 261 #define default_param_phy_utmi_width 16 262 263 #define default_param_turn_around_time_hs 4 //(NoChange) 264 #define default_param_turn_around_time_fs 4 //(NoChange) 265 #define default_param_timeout_cal_hs -1 //(NoChange) 266 #define default_param_timeout_cal_fs -1 //(NoChange) 267 268 #define default_param_data_fifo_size -1 //(Max, hwcfg) 269 270 #ifdef __IS_HOST__ 271 #define default_param_host_channels -1 //(Max, hwcfg) 272 #define default_param_rx_fifo_size 240 273 #define default_param_nperio_tx_fifo_size 240 274 #define default_param_perio_tx_fifo_size 32 275 #endif //__IS_HOST__ 276 #ifdef __IS_DEVICE__ 277 #ifdef __DED_INTR__ 278// #define default_param_rx_fifo_size 256 279// #define default_param_nperio_tx_fifo_size 248 280// #define default_param_perio_tx_fifo_size_01 8 281 #define default_param_rx_fifo_size 240 282 #define default_param_nperio_tx_fifo_size 240 283 #define default_param_perio_tx_fifo_size_01 32 284 #else 285 #define default_param_rx_fifo_size 256 286 #define default_param_nperio_tx_fifo_size 256 287 #define default_param_perio_tx_fifo_size_01 0 288 #endif 289 #define default_param_perio_tx_fifo_size_02 0 290 #define default_param_perio_tx_fifo_size_03 0 291 #define default_param_perio_tx_fifo_size_04 0 292 #define default_param_perio_tx_fifo_size_05 0 293 #define default_param_perio_tx_fifo_size_06 0 294 #define default_param_perio_tx_fifo_size_07 0 295 #define default_param_perio_tx_fifo_size_08 0 296 #define default_param_perio_tx_fifo_size_09 0 297 #define default_param_perio_tx_fifo_size_10 0 298 #define default_param_perio_tx_fifo_size_11 0 299 #define default_param_perio_tx_fifo_size_12 0 300 #define default_param_perio_tx_fifo_size_13 0 301 #define default_param_perio_tx_fifo_size_14 0 302 #define default_param_perio_tx_fifo_size_15 0 303 #endif //__IS_DEVICE__ 304 305 #elif defined(__IS_AR9__) 306 #define IFXUSB1_IRQ 62 307 #define IFXUSB1_IOMEM_BASE 0x1E101000 308 #define IFXUSB1_FIFOMEM_BASE 0x1E120000 309 #define IFXUSB1_FIFODBG_BASE 0x1E140000 310 311 #define IFXUSB2_IRQ 91 312 #define IFXUSB2_IOMEM_BASE 0x1E106000 313 #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 314 #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 315 316 #define IFXUSB_OC_IRQ 68 317 318 #ifndef AR9_RCU_BASE_ADDR 319 #define AR9_RCU_BASE_ADDR (0xBF203000) 320 #endif 321 322 #ifndef AR9_CGU 323 #define AR9_CGU (0xBF103000) 324 #endif 325 #ifndef AR9_CGU_IFCCR 326 #define AR9_CGU_IFCCR ((volatile unsigned long *)(AR9_CGU+ 0x0018)) 327 #endif 328 329 #ifndef AR9_PMU 330 #define AR9_PMU (KSEG1+0x1F102000) 331 #endif 332 #ifndef AR9_PMU_PWDCR 333 #define AR9_PMU_PWDCR ((volatile unsigned long *)(AR9_PMU+0x001C)) 334 #endif 335 336 #ifndef AR9_GPIO_P0_OUT 337 #define AR9_GPIO_P0_OUT (0xBF103000+0x10) 338 #define AR9_GPIO_P0_DIR (0xBF103000+0x18) 339 #define AR9_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) 340 #define AR9_GPIO_P0_ALTSEL1 (0xBF103000+0x20) 341 #define AR9_GPIO_P0_OD (0xBF103000+0x24) 342 #define AR9_GPIO_P0_PUDSEL (0xBF103000+0x2C) 343 #define AR9_GPIO_P0_PUDEN (0xBF103000+0x30) 344 #define AR9_GPIO_P1_OUT (0xBF103000+0x40) 345 #define AR9_GPIO_P1_DIR (0xBF103000+0x48) 346 #define AR9_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) 347 #define AR9_GPIO_P1_ALTSEL1 (0xBF103000+0x50) 348 #define AR9_GPIO_P1_OD (0xBF103000+0x54) 349 #define AR9_GPIO_P1_PUDSEL (0xBF103000+0x5C) 350 #define AR9_GPIO_P1_PUDEN (0xBF103000+0x60) 351 #endif 352 353 #define AR9_RCU_USB1CFG ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x18)) 354 #define AR9_RCU_USB2CFG ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x34)) 355 #define AR9_RCU_USBRESET ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x10)) 356 #define AR9_USBCFG_ARB 7 // 357 #define AR9_USBCFG_HDSEL_BIT 11 // 0:host, 1:device 358 #define AR9_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end 359 #define AR9_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end 360 361 #define default_param_dma_burst_size 4 362 363 #define default_param_speed IFXUSB_PARAM_SPEED_HIGH 364 365 #define default_param_max_transfer_size -1 //(Max, hwcfg) 366 #define default_param_max_packet_count -1 //(Max, hwcfg) 367 #define default_param_phy_utmi_width 16 368 369 #define default_param_turn_around_time_hs 4 //(NoChange) 370 #define default_param_turn_around_time_fs 4 //(NoChange) 371 #define default_param_timeout_cal_hs -1 //(NoChange) 372 #define default_param_timeout_cal_fs -1 //(NoChange) 373 374 #define default_param_data_fifo_size -1 //(Max, hwcfg) 375 376 #ifdef __IS_HOST__ 377 #define default_param_host_channels -1 //(Max, hwcfg) 378 #define default_param_rx_fifo_size 240 379 #define default_param_nperio_tx_fifo_size 240 380 #define default_param_perio_tx_fifo_size 32 381 #endif //__IS_HOST__ 382 #ifdef __IS_DEVICE__ 383 #ifdef __DED_INTR__ 384// #define default_param_rx_fifo_size 256 385// #define default_param_nperio_tx_fifo_size 248 386// #define default_param_perio_tx_fifo_size_01 8 387 #define default_param_rx_fifo_size 240 388 #define default_param_nperio_tx_fifo_size 240 389 #define default_param_perio_tx_fifo_size_01 32 390 #else 391 #define default_param_rx_fifo_size 256 392 #define default_param_nperio_tx_fifo_size 256 393 #define default_param_perio_tx_fifo_size_01 0 394 #endif 395 #define default_param_perio_tx_fifo_size_02 0 396 #define default_param_perio_tx_fifo_size_03 0 397 #define default_param_perio_tx_fifo_size_04 0 398 #define default_param_perio_tx_fifo_size_05 0 399 #define default_param_perio_tx_fifo_size_06 0 400 #define default_param_perio_tx_fifo_size_07 0 401 #define default_param_perio_tx_fifo_size_08 0 402 #define default_param_perio_tx_fifo_size_09 0 403 #define default_param_perio_tx_fifo_size_10 0 404 #define default_param_perio_tx_fifo_size_11 0 405 #define default_param_perio_tx_fifo_size_12 0 406 #define default_param_perio_tx_fifo_size_13 0 407 #define default_param_perio_tx_fifo_size_14 0 408 #define default_param_perio_tx_fifo_size_15 0 409 #endif //__IS_DEVICE__ 410 411 #elif defined(__IS_VR9__) 412 #define IFXUSB1_IRQ 62 413 #define IFXUSB1_IOMEM_BASE 0x1E101000 414 #define IFXUSB1_FIFOMEM_BASE 0x1E120000 415 #define IFXUSB1_FIFODBG_BASE 0x1E140000 416 417 #define IFXUSB2_IRQ 91 418 #define IFXUSB2_IOMEM_BASE 0x1E106000 419 #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 420 #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 421 #define IFXUSB_OC_IRQ 60 422 423 #ifndef IFX_MPS 424 #define IFX_MPS (KSEG1+0x1F107000) 425 #endif 426 #ifndef IFX_MPS_CHIPID 427 #define IFX_MPS_CHIPID ((volatile unsigned long *)(IFX_MPS + 0x0344)) 428 #endif 429 430 #ifndef VR9_RCU_BASE_ADDR 431 #define VR9_RCU_BASE_ADDR (0xBF203000) 432 #endif 433 434 #ifndef VR9_CGU 435 #define VR9_CGU (0xBF103000) 436 #endif 437 #ifndef VR9_CGU_IFCCR 438 #define VR9_CGU_IFCCR ((volatile unsigned long *)(VR9_CGU+ 0x0018)) 439 #endif 440 441 #ifndef VR9_PMU 442 #define VR9_PMU (KSEG1+0x1F102000) 443 #endif 444 #ifndef VR9_PMU_PWDCR 445 #define VR9_PMU_PWDCR ((volatile unsigned long *)(VR9_PMU+0x001C)) 446 #endif 447 448 #ifndef VR9_GPIO_P0_OUT 449 #define VR9_GPIO_P0_OUT (0xBF103000+0x10) 450 #define VR9_GPIO_P0_DIR (0xBF103000+0x18) 451 #define VR9_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) 452 #define VR9_GPIO_P0_ALTSEL1 (0xBF103000+0x20) 453 #define VR9_GPIO_P0_OD (0xBF103000+0x24) 454 #define VR9_GPIO_P0_PUDSEL (0xBF103000+0x2C) 455 #define VR9_GPIO_P0_PUDEN (0xBF103000+0x30) 456 #define VR9_GPIO_P1_OUT (0xBF103000+0x40) 457 #define VR9_GPIO_P1_DIR (0xBF103000+0x48) 458 #define VR9_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) 459 #define VR9_GPIO_P1_ALTSEL1 (0xBF103000+0x50) 460 #define VR9_GPIO_P1_OD (0xBF103000+0x54) 461 #define VR9_GPIO_P1_PUDSEL (0xBF103000+0x5C) 462 #define VR9_GPIO_P1_PUDEN (0xBF103000+0x60) 463 #endif 464 465 #define VR9_RCU_USB1CFG ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x18)) 466 #define VR9_RCU_USB2CFG ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x34)) 467 #define VR9_RCU_USB_ANA_CFG1A ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x38)) 468 #define VR9_RCU_USB_ANA_CFG1B ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x3C)) 469 #define VR9_RCU_USBRESET ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x10)) 470 #define VR9_RCU_USBRESET2 ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x48)) 471 #define VR9_USBCFG_ARB 7 // 472 #define VR9_USBCFG_HDSEL_BIT 11 // 0:host, 1:device 473 #define VR9_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end 474 #define VR9_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end 475 476// #define default_param_dma_burst_size 4 //(ALL) 477 //WA for AHB 478 #define default_param_dma_burst_size 0 //(ALL) 479 #define default_param_dma_burst_size_n 4 //(ALL) 480 481 #define default_param_speed IFXUSB_PARAM_SPEED_HIGH 482 483 #define default_param_max_transfer_size -1 //(Max, hwcfg) 484 #define default_param_max_packet_count -1 //(Max, hwcfg) 485 #define default_param_phy_utmi_width 16 486 487 #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a 488 #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a 489 #define default_param_timeout_cal_hs -1 //(NoChange) 490 #define default_param_timeout_cal_fs -1 //(NoChange) 491 492 #define default_param_data_fifo_size -1 //(Max, hwcfg) 493 494 #ifdef __IS_HOST__ 495 #define default_param_host_channels -1 //(Max, hwcfg) 496 #define default_param_rx_fifo_size 240 497 #define default_param_nperio_tx_fifo_size 240 498 #define default_param_perio_tx_fifo_size 32 499 #endif //__IS_HOST__ 500 #ifdef __IS_DEVICE__ 501#if 0 502 #define default_param_rx_fifo_size 256 503 #define default_param_tx_fifo_size_00 -1 504 #define default_param_tx_fifo_size_01 -1 505 #define default_param_tx_fifo_size_02 -1 506#else 507 #define default_param_rx_fifo_size 256 508 #define default_param_tx_fifo_size_00 32 509 #define default_param_tx_fifo_size_01 200 510 #define default_param_tx_fifo_size_02 8 511#endif 512 #define default_param_tx_fifo_size_03 -1 513 #define default_param_tx_fifo_size_04 -1 514 #define default_param_tx_fifo_size_05 -1 515 #define default_param_tx_fifo_size_06 -1 516 #define default_param_tx_fifo_size_07 -1 517 #define default_param_tx_fifo_size_08 -1 518 #define default_param_tx_fifo_size_09 -1 519 #define default_param_tx_fifo_size_10 -1 520 #define default_param_tx_fifo_size_11 -1 521 #define default_param_tx_fifo_size_12 -1 522 #define default_param_tx_fifo_size_13 -1 523 #define default_param_tx_fifo_size_14 -1 524 #define default_param_tx_fifo_size_15 -1 525 #define default_param_dma_unalgned_tx -1 526 #define default_param_dma_unalgned_rx -1 527 #define default_param_thr_ctl -1 528 #define default_param_tx_thr_length -1 529 #define default_param_rx_thr_length -1 530 #endif //__IS_DEVICE__ 531 532 #elif defined(__IS_AR10__) 533 #define IFXUSB1_IRQ 54 534 #define IFXUSB1_IOMEM_BASE 0x1E101000 535 #define IFXUSB1_FIFOMEM_BASE 0x1E120000 536 #define IFXUSB1_FIFODBG_BASE 0x1E140000 537 #define IFXUSB1_OC_IRQ 60 538 539 #define IFXUSB2_IRQ 83 540 #define IFXUSB2_IOMEM_BASE 0x1E106000 541 #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 542 #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 543 #define IFXUSB2_OC_IRQ 56 544 545 #ifndef AR10_RCU_BASE_ADDR 546 #define AR10_RCU_BASE_ADDR (0xBF203000) 547 #endif 548 #ifndef AR10_CGU 549 #define AR10_CGU (0xBF103000) 550 #endif 551 552 #ifndef AR10_CGU_IFCCR 553 #define AR10_CGU_IFCCR ((volatile unsigned long *)(AR10_CGU+ 0x0018)) 554 #endif 555 #ifndef AR10_PMU 556 #define AR10_PMU (KSEG1+0x1F102000) 557 #endif 558 #ifndef AR10_PMU_PWDCR 559 #define AR10_PMU_PWDCR ((volatile unsigned long *)(AR10_PMU+0x0044)) 560 #endif 561 562 #ifndef AR10_GPIO_P0_OUT 563 #define AR10_GPIO_P0_OUT (0xBF103000+0x10) 564 #define AR10_GPIO_P0_DIR (0xBF103000+0x18) 565 #define AR10_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) 566 #define AR10_GPIO_P0_ALTSEL1 (0xBF103000+0x20) 567 #define AR10_GPIO_P0_OD (0xBF103000+0x24) 568 #define AR10_GPIO_P0_PUDSEL (0xBF103000+0x2C) 569 #define AR10_GPIO_P0_PUDEN (0xBF103000+0x30) 570 #define AR10_GPIO_P1_OUT (0xBF103000+0x40) 571 #define AR10_GPIO_P1_DIR (0xBF103000+0x48) 572 #define AR10_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) 573 #define AR10_GPIO_P1_ALTSEL1 (0xBF103000+0x50) 574 #define AR10_GPIO_P1_OD (0xBF103000+0x54) 575 #define AR10_GPIO_P1_PUDSEL (0xBF103000+0x5C) 576 #define AR10_GPIO_P1_PUDEN (0xBF103000+0x60) 577 #endif 578 579 #define AR10_RCU_USB1CFG ((volatile unsigned long *)(AR10_RCU_BASE_ADDR + 0x18)) 580 #define AR10_RCU_USB2CFG ((volatile unsigned long *)(AR10_RCU_BASE_ADDR + 0x34)) 581 #define AR10_RCU_USB_ANA_CFG1A ((volatile unsigned long *)(AR10_RCU_BASE_ADDR + 0x38)) 582 #define AR10_RCU_USB_ANA_CFG1B ((volatile unsigned long *)(AR10_RCU_BASE_ADDR + 0x3C)) 583 584 #define AR10_RCU_USBRESET ((volatile unsigned long *)(AR10_RCU_BASE_ADDR + 0x10)) 585 586 #define AR10_USBCFG_ARB 7 // 587 #define AR10_USBCFG_HDSEL_BIT 11 // 0:host, 1:device 588 #define AR10_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end 589 #define AR10_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end 590 591// #define default_param_dma_burst_size 4 //(ALL) 592 //WA for AHB 593 #define default_param_dma_burst_size 0 //(ALL) 594 595 #define default_param_speed IFXUSB_PARAM_SPEED_HIGH 596 597 #define default_param_max_transfer_size -1 //(Max, hwcfg) 598 #define default_param_max_packet_count -1 //(Max, hwcfg) 599 #define default_param_phy_utmi_width 16 600 601 #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a 602 #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a 603 #define default_param_timeout_cal_hs -1 //(NoChange) 604 #define default_param_timeout_cal_fs -1 //(NoChange) 605 606 #define default_param_data_fifo_size -1 //(Max, hwcfg) 607 608 #ifdef __IS_HOST__ 609 #define default_param_host_channels -1 //(Max, hwcfg) 610 #define default_param_rx_fifo_size 240 611 #define default_param_nperio_tx_fifo_size 240 612 #define default_param_perio_tx_fifo_size 32 613 #endif //__IS_HOST__ 614 #ifdef __IS_DEVICE__ 615#if 0 616 #define default_param_rx_fifo_size 256 617 #define default_param_tx_fifo_size_00 -1 618 #define default_param_tx_fifo_size_01 -1 619 #define default_param_tx_fifo_size_02 -1 620#else 621 #define default_param_rx_fifo_size 256 622 #define default_param_tx_fifo_size_00 32 623 #define default_param_tx_fifo_size_01 200 624 #define default_param_tx_fifo_size_02 8 625#endif 626 #define default_param_tx_fifo_size_03 -1 627 #define default_param_tx_fifo_size_04 -1 628 #define default_param_tx_fifo_size_05 -1 629 #define default_param_tx_fifo_size_06 -1 630 #define default_param_tx_fifo_size_07 -1 631 #define default_param_tx_fifo_size_08 -1 632 #define default_param_tx_fifo_size_09 -1 633 #define default_param_tx_fifo_size_10 -1 634 #define default_param_tx_fifo_size_11 -1 635 #define default_param_tx_fifo_size_12 -1 636 #define default_param_tx_fifo_size_13 -1 637 #define default_param_tx_fifo_size_14 -1 638 #define default_param_tx_fifo_size_15 -1 639 #define default_param_dma_unalgned_tx -1 640 #define default_param_dma_unalgned_rx -1 641 #define default_param_thr_ctl -1 642 #define default_param_tx_thr_length -1 643 #define default_param_rx_thr_length -1 644 #endif //__IS_DEVICE__ 645 #else // __IS_AR10__ 646 #error "Please choose one platform!!" 647 #endif // __IS_VR9__ 648 649#else //UEIP 650 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) 651 #define IFXUSB_IRQ 54 652 #define IFXUSB_IOMEM_BASE 0x1e101000 653 #define IFXUSB_FIFOMEM_BASE 0x1e120000 654 #define IFXUSB_FIFODBG_BASE 0x1e140000 655 #define IFXUSB_OC_IRQ 151 656 657 658 #ifndef DANUBE_RCU_BASE_ADDR 659 #define DANUBE_RCU_BASE_ADDR (0xBF203000) 660 #endif 661 662 #ifndef DANUBE_CGU 663 #define DANUBE_CGU (0xBF103000) 664 #endif 665 #ifndef DANUBE_CGU_IFCCR 666 #define DANUBE_CGU_IFCCR ((volatile unsigned long *)(DANUBE_CGU+ 0x0018)) 667 #endif 668 #ifndef DANUBE_PMU 669 #define DANUBE_PMU (KSEG1+0x1F102000) 670 #endif 671 #ifndef DANUBE_PMU_PWDCR 672 #define DANUBE_PMU_PWDCR ((volatile unsigned long *)(DANUBE_PMU+0x001C)) 673 #endif 674 675 #ifndef DANUBE_GPIO_P0_OUT 676 #define DANUBE_GPIO_P0_OUT (0xBF103000+0x10) 677 #define DANUBE_GPIO_P0_DIR (0xBF103000+0x18) 678 #define DANUBE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) 679 #define DANUBE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) 680 #define DANUBE_GPIO_P0_OD (0xBF103000+0x24) 681 #define DANUBE_GPIO_P0_PUDSEL (0xBF103000+0x2C) 682 #define DANUBE_GPIO_P0_PUDEN (0xBF103000+0x30) 683 #define DANUBE_GPIO_P1_OUT (0xBF103000+0x40) 684 #define DANUBE_GPIO_P1_DIR (0xBF103000+0x48) 685 #define DANUBE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) 686 #define DANUBE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) 687 #define DANUBE_GPIO_P1_OD (0xBF103000+0x54) 688 #define DANUBE_GPIO_P1_PUDSEL (0xBF103000+0x5C) 689 #define DANUBE_GPIO_P1_PUDEN (0xBF103000+0x60) 690 #endif 691 692 693 #define DANUBE_RCU_USBCFG ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18)) 694 #define DANUBE_RCU_RESET ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10)) 695 #define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device 696 #define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end 697 #define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end 698 699 #define default_param_dma_burst_size 4 700 701 #define default_param_speed IFXUSB_PARAM_SPEED_HIGH 702 703 #define default_param_max_transfer_size -1 //(Max, hwcfg) 704 #define default_param_max_packet_count -1 //(Max, hwcfg) 705 #define default_param_phy_utmi_width 16 706 707 #define default_param_turn_around_time_hs 4 //(NoChange) 708 #define default_param_turn_around_time_fs 4 //(NoChange) 709 #define default_param_timeout_cal_hs -1 //(NoChange) 710 #define default_param_timeout_cal_fs -1 //(NoChange) 711 712 #define default_param_data_fifo_size -1 //(Max, hwcfg) 713 #ifdef __IS_HOST__ 714 #define default_param_host_channels -1 //(Max, hwcfg) 715 #define default_param_rx_fifo_size 640 716 #define default_param_nperio_tx_fifo_size 640 717 #define default_param_perio_tx_fifo_size 768 718 #endif //__IS_HOST__ 719 720 #ifdef __IS_DEVICE__ 721 #ifdef __DED_INTR__ 722 #define default_param_rx_fifo_size 1024 723 #define default_param_nperio_tx_fifo_size 1016 724 #define default_param_perio_tx_fifo_size_01 8 725 #else 726 #define default_param_rx_fifo_size 1024 727 #define default_param_nperio_tx_fifo_size 1024 728 #define default_param_perio_tx_fifo_size_01 0 729 #endif 730 #define default_param_perio_tx_fifo_size_02 0 731 #define default_param_perio_tx_fifo_size_03 0 732 #define default_param_perio_tx_fifo_size_04 0 733 #define default_param_perio_tx_fifo_size_05 0 734 #define default_param_perio_tx_fifo_size_06 0 735 #define default_param_perio_tx_fifo_size_07 0 736 #define default_param_perio_tx_fifo_size_08 0 737 #define default_param_perio_tx_fifo_size_09 0 738 #define default_param_perio_tx_fifo_size_10 0 739 #define default_param_perio_tx_fifo_size_11 0 740 #define default_param_perio_tx_fifo_size_12 0 741 #define default_param_perio_tx_fifo_size_13 0 742 #define default_param_perio_tx_fifo_size_14 0 743 #define default_param_perio_tx_fifo_size_15 0 744 #endif //__IS_DEVICE__ 745 746 #elif defined(__IS_AMAZON_SE__) 747 #include <asm/amazon_se/amazon_se.h> 748 //#include <asm/amazon_se/irq.h> 749 750 #define IFXUSB_IRQ 31 751 #define IFXUSB_IOMEM_BASE 0x1e101000 752 #define IFXUSB_FIFOMEM_BASE 0x1e120000 753 #define IFXUSB_FIFODBG_BASE 0x1e140000 754 #define IFXUSB_OC_IRQ 20 755 756 #define AMAZON_SE_RCU_USBCFG ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18)) 757 #define AMAZON_SE_RCU_RESET ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10)) 758 #define AMAZON_SE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device 759 #define AMAZON_SE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end 760 #define AMAZON_SE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end 761 762 #ifndef AMAZON_SE_GPIO_P0_OUT 763 #define AMAZON_SE_GPIO_P0_OUT (0xBF103000+0x10) 764 #define AMAZON_SE_GPIO_P0_DIR (0xBF103000+0x18) 765 #define AMAZON_SE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) 766 #define AMAZON_SE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) 767 #define AMAZON_SE_GPIO_P0_OD (0xBF103000+0x24) 768 #define AMAZON_SE_GPIO_P0_PUDSEL (0xBF103000+0x2C) 769 #define AMAZON_SE_GPIO_P0_PUDEN (0xBF103000+0x30) 770 #define AMAZON_SE_GPIO_P1_OUT (0xBF103000+0x40) 771 #define AMAZON_SE_GPIO_P1_DIR (0xBF103000+0x48) 772 #define AMAZON_SE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) 773 #define AMAZON_SE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) 774 #define AMAZON_SE_GPIO_P1_OD (0xBF103000+0x54) 775 #define AMAZON_SE_GPIO_P1_PUDSEL (0xBF103000+0x5C) 776 #define AMAZON_SE_GPIO_P1_PUDEN (0xBF103000+0x60) 777 #endif 778 779 780 #ifndef AMAZON_SE_CGU 781 #define AMAZON_SE_CGU (0xBF103000) 782 #endif 783 #ifndef AMAZON_SE_CGU_IFCCR 784 #define AMAZON_SE_CGU_IFCCR ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018)) 785 #endif 786 #ifndef AMAZON_SE_PMU 787 #define AMAZON_SE_PMU (KSEG1+0x1F102000) 788 #endif 789 #ifndef AMAZON_SE_PMU_PWDCR 790 #define AMAZON_SE_PMU_PWDCR ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C)) 791 #endif 792 793 #define default_param_dma_burst_size 4 794 795 #define default_param_speed IFXUSB_PARAM_SPEED_HIGH 796 797 #define default_param_max_transfer_size -1 //(Max, hwcfg) 798 #define default_param_max_packet_count -1 //(Max, hwcfg) 799 #define default_param_phy_utmi_width 16 800 801 #define default_param_turn_around_time_hs 4 //(NoChange) 802 #define default_param_turn_around_time_fs 4 //(NoChange) 803 #define default_param_timeout_cal_hs -1 //(NoChange) 804 #define default_param_timeout_cal_fs -1 //(NoChange) 805 806 #define default_param_data_fifo_size -1 //(Max, hwcfg) 807 808 #ifdef __IS_HOST__ 809 #define default_param_host_channels -1 //(Max, hwcfg) 810 #define default_param_rx_fifo_size 240 811 #define default_param_nperio_tx_fifo_size 240 812 #define default_param_perio_tx_fifo_size 32 813 #endif //__IS_HOST__ 814 #ifdef __IS_DEVICE__ 815 #ifdef __DED_INTR__ 816 #define default_param_rx_fifo_size 256 817 #define default_param_nperio_tx_fifo_size 248 818 #define default_param_perio_tx_fifo_size_01 8 819 #else 820 #define default_param_rx_fifo_size 256 821 #define default_param_nperio_tx_fifo_size 256 822 #define default_param_perio_tx_fifo_size_01 0 823 #endif 824 #define default_param_perio_tx_fifo_size_02 0 825 #define default_param_perio_tx_fifo_size_03 0 826 #define default_param_perio_tx_fifo_size_04 0 827 #define default_param_perio_tx_fifo_size_05 0 828 #define default_param_perio_tx_fifo_size_06 0 829 #define default_param_perio_tx_fifo_size_07 0 830 #define default_param_perio_tx_fifo_size_08 0 831 #define default_param_perio_tx_fifo_size_09 0 832 #define default_param_perio_tx_fifo_size_10 0 833 #define default_param_perio_tx_fifo_size_11 0 834 #define default_param_perio_tx_fifo_size_12 0 835 #define default_param_perio_tx_fifo_size_13 0 836 #define default_param_perio_tx_fifo_size_14 0 837 #define default_param_perio_tx_fifo_size_15 0 838 #endif //__IS_DEVICE__ 839 840 #elif defined(__IS_AR9__) 841 #define IFXUSB1_IRQ 54 842 #define IFXUSB1_IOMEM_BASE 0x1E101000 843 #define IFXUSB1_FIFOMEM_BASE 0x1E120000 844 #define IFXUSB1_FIFODBG_BASE 0x1E140000 845 846 #define IFXUSB2_IRQ 83 847 #define IFXUSB2_IOMEM_BASE 0x1E106000 848 #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 849 #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 850 851 #define IFXUSB_OC_IRQ 60 852 853 #ifndef AMAZON_S_RCU_BASE_ADDR 854 #define AMAZON_S_RCU_BASE_ADDR (0xBF203000) 855 #endif 856 857 #ifndef AMAZON_S_CGU 858 #define AMAZON_S_CGU (0xBF103000) 859 #endif 860 #ifndef AMAZON_S_CGU_IFCCR 861 #define AMAZON_S_CGU_IFCCR ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018)) 862 #endif 863 864 #ifndef AMAZON_S_PMU 865 #define AMAZON_S_PMU (KSEG1+0x1F102000) 866 #endif 867 #ifndef AMAZON_S_PMU_PWDCR 868 #define AMAZON_S_PMU_PWDCR ((volatile unsigned long *)(AMAZON_S_PMU+0x001C)) 869 #endif 870 871 #ifndef AMAZON_S_GPIO_P0_OUT 872 #define AMAZON_S_GPIO_P0_OUT (0xBF103000+0x10) 873 #define AMAZON_S_GPIO_P0_DIR (0xBF103000+0x18) 874 #define AMAZON_S_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) 875 #define AMAZON_S_GPIO_P0_ALTSEL1 (0xBF103000+0x20) 876 #define AMAZON_S_GPIO_P0_OD (0xBF103000+0x24) 877 #define AMAZON_S_GPIO_P0_PUDSEL (0xBF103000+0x2C) 878 #define AMAZON_S_GPIO_P0_PUDEN (0xBF103000+0x30) 879 #define AMAZON_S_GPIO_P1_OUT (0xBF103000+0x40) 880 #define AMAZON_S_GPIO_P1_DIR (0xBF103000+0x48) 881 #define AMAZON_S_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) 882 #define AMAZON_S_GPIO_P1_ALTSEL1 (0xBF103000+0x50) 883 #define AMAZON_S_GPIO_P1_OD (0xBF103000+0x54) 884 #define AMAZON_S_GPIO_P1_PUDSEL (0xBF103000+0x5C) 885 #define AMAZON_S_GPIO_P1_PUDEN (0xBF103000+0x60) 886 #endif 887 888 #define AMAZON_S_RCU_USB1CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18)) 889 #define AMAZON_S_RCU_USB2CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34)) 890 #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10)) 891 #define AMAZON_S_USBCFG_ARB 7 // 892 #define AMAZON_S_USBCFG_HDSEL_BIT 11 // 0:host, 1:device 893 #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end 894 #define AMAZON_S_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end 895 896 #define default_param_dma_burst_size 4 897 898 #define default_param_speed IFXUSB_PARAM_SPEED_HIGH 899 900 #define default_param_max_transfer_size -1 //(Max, hwcfg) 901 #define default_param_max_packet_count -1 //(Max, hwcfg) 902 #define default_param_phy_utmi_width 16 903 904 #define default_param_turn_around_time_hs 4 //(NoChange) 905 #define default_param_turn_around_time_fs 4 //(NoChange) 906 #define default_param_timeout_cal_hs -1 //(NoChange) 907 #define default_param_timeout_cal_fs -1 //(NoChange) 908 909 #define default_param_data_fifo_size -1 //(Max, hwcfg) 910 911 #ifdef __IS_HOST__ 912 #define default_param_host_channels -1 //(Max, hwcfg) 913 #define default_param_rx_fifo_size 240 914 #define default_param_nperio_tx_fifo_size 240 915 #define default_param_perio_tx_fifo_size 32 916 #endif //__IS_HOST__ 917 #ifdef __IS_DEVICE__ 918 #ifdef __DED_INTR__ 919 #define default_param_rx_fifo_size 256 920 #define default_param_nperio_tx_fifo_size 248 921 #define default_param_perio_tx_fifo_size_01 8 922 #else 923 #define default_param_rx_fifo_size 256 924 #define default_param_nperio_tx_fifo_size 256 925 #define default_param_perio_tx_fifo_size_01 0 926 #endif 927 #define default_param_perio_tx_fifo_size_02 0 928 #define default_param_perio_tx_fifo_size_03 0 929 #define default_param_perio_tx_fifo_size_04 0 930 #define default_param_perio_tx_fifo_size_05 0 931 #define default_param_perio_tx_fifo_size_06 0 932 #define default_param_perio_tx_fifo_size_07 0 933 #define default_param_perio_tx_fifo_size_08 0 934 #define default_param_perio_tx_fifo_size_09 0 935 #define default_param_perio_tx_fifo_size_10 0 936 #define default_param_perio_tx_fifo_size_11 0 937 #define default_param_perio_tx_fifo_size_12 0 938 #define default_param_perio_tx_fifo_size_13 0 939 #define default_param_perio_tx_fifo_size_14 0 940 #define default_param_perio_tx_fifo_size_15 0 941 #endif //__IS_DEVICE__ 942 943 #elif defined(__IS_VR9__) 944 #define IFXUSB1_IRQ 54 945 #define IFXUSB1_IOMEM_BASE 0x1E101000 946 #define IFXUSB1_FIFOMEM_BASE 0x1E120000 947 #define IFXUSB1_FIFODBG_BASE 0x1E140000 948 949 #define IFXUSB2_IRQ 83 950 #define IFXUSB2_IOMEM_BASE 0x1E106000 951 #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 952 #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 953 #define IFXUSB_OC_IRQ 68 954 955 #ifndef AMAZON_S_RCU_BASE_ADDR 956 #define AMAZON_S_RCU_BASE_ADDR (0xBF203000) 957 #endif 958 959 #ifndef AMAZON_S_CGU 960 #define AMAZON_S_CGU (0xBF103000) 961 #endif 962 #ifndef AMAZON_S_CGU_IFCCR 963 #define AMAZON_S_CGU_IFCCR ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018)) 964 #endif 965 966 #ifndef AMAZON_S_PMU 967 #define AMAZON_S_PMU (KSEG1+0x1F102000) 968 #endif 969 #ifndef AMAZON_S_PMU_PWDCR 970 #define AMAZON_S_PMU_PWDCR ((volatile unsigned long *)(AMAZON_S_PMU+0x001C)) 971 #endif 972 973 #ifndef AMAZON_S_GPIO_P0_OUT 974 #define AMAZON_S_GPIO_P0_OUT (0xBF103000+0x10) 975 #define AMAZON_S_GPIO_P0_DIR (0xBF103000+0x18) 976 #define AMAZON_S_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) 977 #define AMAZON_S_GPIO_P0_ALTSEL1 (0xBF103000+0x20) 978 #define AMAZON_S_GPIO_P0_OD (0xBF103000+0x24) 979 #define AMAZON_S_GPIO_P0_PUDSEL (0xBF103000+0x2C) 980 #define AMAZON_S_GPIO_P0_PUDEN (0xBF103000+0x30) 981 #define AMAZON_S_GPIO_P1_OUT (0xBF103000+0x40) 982 #define AMAZON_S_GPIO_P1_DIR (0xBF103000+0x48) 983 #define AMAZON_S_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) 984 #define AMAZON_S_GPIO_P1_ALTSEL1 (0xBF103000+0x50) 985 #define AMAZON_S_GPIO_P1_OD (0xBF103000+0x54) 986 #define AMAZON_S_GPIO_P1_PUDSEL (0xBF103000+0x5C) 987 #define AMAZON_S_GPIO_P1_PUDEN (0xBF103000+0x60) 988 #endif 989 990 #define AMAZON_S_RCU_USB1CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18)) 991 #define AMAZON_S_RCU_USB2CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34)) 992 #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10)) 993 #define AMAZON_S_USBCFG_ARB 7 // 994 #define AMAZON_S_USBCFG_HDSEL_BIT 11 // 0:host, 1:device 995 #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end 996 #define AMAZON_S_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end 997 998 #define default_param_dma_burst_size 4 //(ALL) 999 1000 #define default_param_speed IFXUSB_PARAM_SPEED_HIGH 1001 1002 #define default_param_max_transfer_size -1 //(Max, hwcfg) 1003 #define default_param_max_packet_count -1 //(Max, hwcfg) 1004 #define default_param_phy_utmi_width 16 1005 1006 #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a 1007 #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a 1008 #define default_param_timeout_cal_hs -1 //(NoChange) 1009 #define default_param_timeout_cal_fs -1 //(NoChange) 1010 1011 #define default_param_data_fifo_size -1 //(Max, hwcfg) 1012 1013 #ifdef __IS_HOST__ 1014 #define default_param_host_channels -1 //(Max, hwcfg) 1015 #define default_param_rx_fifo_size 240 1016 #define default_param_nperio_tx_fifo_size 240 1017 #define default_param_perio_tx_fifo_size 32 1018 #endif //__IS_HOST__ 1019 #ifdef __IS_DEVICE__ 1020 #define default_param_rx_fifo_size 256 1021 #define default_param_tx_fifo_size_00 -1 1022 #define default_param_tx_fifo_size_01 -1 1023 #define default_param_tx_fifo_size_02 -1 1024 #define default_param_tx_fifo_size_03 -1 1025 #define default_param_tx_fifo_size_04 -1 1026 #define default_param_tx_fifo_size_05 -1 1027 #define default_param_tx_fifo_size_06 -1 1028 #define default_param_tx_fifo_size_07 -1 1029 #define default_param_tx_fifo_size_08 -1 1030 #define default_param_tx_fifo_size_09 -1 1031 #define default_param_tx_fifo_size_10 -1 1032 #define default_param_tx_fifo_size_11 -1 1033 #define default_param_tx_fifo_size_12 -1 1034 #define default_param_tx_fifo_size_13 -1 1035 #define default_param_tx_fifo_size_14 -1 1036 #define default_param_tx_fifo_size_15 -1 1037 #define default_param_dma_unalgned_tx -1 1038 #define default_param_dma_unalgned_rx -1 1039 #define default_param_thr_ctl -1 1040 #define default_param_tx_thr_length -1 1041 #define default_param_rx_thr_length -1 1042 #endif //__IS_DEVICE__ 1043 #else // __IS_VR9__ 1044 #error "Please choose one platform!!" 1045 #endif // __IS_VR9__ 1046#endif //UEIP 1047 1048/*@}*//*IFXUSB_PLATEFORM_MEM_ADDR*/ 1049 1050///////////////////////////////////////////////////////////////////////// 1051 1052#ifdef __IS_HOST__ 1053 #if defined(CONFIG_USB_HOST_IFX_FORCE_USB11) || defined(__FORCE_USB11__) 1054 #undef default_param_speed 1055 #define default_param_speed IFXUSB_PARAM_SPEED_FULL 1056 #endif 1057#endif 1058#ifdef __IS_DEVICE__ 1059 #if !defined(CONFIG_USB_GADGET_DUALSPEED) || defined(__FORCE_USB11__) 1060 #undef default_param_speed 1061 #define default_param_speed IFXUSB_PARAM_SPEED_FULL 1062 #endif 1063#endif 1064 1065///////////////////////////////////////////////////////////////////////// 1066 1067static __inline__ void UDELAY( const uint32_t _usecs ) 1068{ 1069 udelay( _usecs ); 1070} 1071 1072static __inline__ void MDELAY( const uint32_t _msecs ) 1073{ 1074 mdelay( _msecs ); 1075} 1076 1077static __inline__ void SPIN_LOCK( spinlock_t *_lock ) 1078{ 1079 spin_lock(_lock); 1080} 1081 1082static __inline__ void SPIN_UNLOCK( spinlock_t *_lock ) 1083{ 1084 spin_unlock(_lock); 1085} 1086 1087#define SPIN_LOCK_IRQSAVE( _l, _f ) \ 1088 { \ 1089 spin_lock_irqsave(_l,_f); \ 1090 } 1091 1092#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) \ 1093 { \ 1094 spin_unlock_irqrestore(_l,_f); \ 1095 } 1096 1097///////////////////////////////////////////////////////////////////////// 1098/*! 1099 \addtogroup IFXUSB_DBG_ROUTINE 1100 */ 1101/*@{*/ 1102#ifdef __IS_HOST__ 1103 extern uint32_t h_dbg_lvl; 1104#endif 1105 1106#ifdef __IS_DEVICE__ 1107 extern uint32_t d_dbg_lvl; 1108#endif 1109 1110/*! \brief When debug level has the DBG_CIL bit set, display CIL Debug messages. */ 1111#define DBG_CIL (0x2) 1112/*! \brief When debug level has the DBG_CILV bit set, display CIL Verbose debug messages */ 1113#define DBG_CILV (0x20) 1114/*! \brief When debug level has the DBG_PCD bit set, display PCD (Device) debug messages */ 1115#define DBG_PCD (0x4) 1116/*! \brief When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug messages */ 1117#define DBG_PCDV (0x40) 1118/*! \brief When debug level has the DBG_HCD bit set, display Host debug messages */ 1119#define DBG_HCD (0x8) 1120/*! \brief When debug level has the DBG_HCDV bit set, display Verbose Host debug messages */ 1121#define DBG_HCDV (0x80) 1122/*! \brief When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host mode. */ 1123#define DBG_HCD_URB (0x800) 1124/*! \brief When debug level has any bit set, display debug messages */ 1125#define DBG_ANY (0xFF) 1126/*! \brief All debug messages off */ 1127#define DBG_OFF 0 1128 1129#define DBG_ENTRY (0x8000) 1130 1131#define IFXUSB "IFXUSB: " 1132 1133/*! 1134 \fn inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) 1135 \brief Set the Debug Level variable. 1136 \param _new 32-bit mask of debug level. 1137 \return previous debug level 1138 */ 1139static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) 1140{ 1141 #ifdef __IS_HOST__ 1142 uint32_t old = h_dbg_lvl; 1143 h_dbg_lvl = _new; 1144 #endif 1145 1146 #ifdef __IS_DEVICE__ 1147 uint32_t old = d_dbg_lvl; 1148 d_dbg_lvl = _new; 1149 #endif 1150 return old; 1151} 1152 1153#ifdef __DEBUG__ 1154 #ifdef __IS_HOST__ 1155 # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&h_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0) 1156 # define CHK_DEBUG_LEVEL(level) ((level) & h_dbg_lvl) 1157 #endif 1158 1159 #ifdef __IS_DEVICE__ 1160 # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&d_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0) 1161 # define CHK_DEBUG_LEVEL(level) ((level) & d_dbg_lvl) 1162 #endif 1163 1164 # define IFX_DEBUGP(x...) IFX_DEBUGPL(DBG_ANY, x ) 1165#else 1166 # define IFX_DEBUGPL(lvl, x...) do{}while(0) 1167 # define IFX_DEBUGP(x...) 1168 # define CHK_DEBUG_LEVEL(level) (0) 1169#endif //__DEBUG__ 1170 1171/* Print an Error message. */ 1172#define IFX_ERROR(x...) printk( KERN_ERR IFXUSB x ) 1173/* Print a Warning message. */ 1174#define IFX_WARN(x...) printk( KERN_WARNING IFXUSB x ) 1175/* Print a notice (normal but significant message). */ 1176#define IFX_NOTICE(x...) printk( KERN_NOTICE IFXUSB x ) 1177/* Basic message printing. */ 1178#define IFX_PRINT(x...) printk( KERN_INFO IFXUSB x ) 1179 1180/*@}*//*IFXUSB_DBG_ROUTINE*/ 1181 1182 1183#endif //__IFXUSB_PLAT_H__ 1184 1185