1/****************************************************************************** 2** 3** FILE NAME : ifxmips_atm_ppe_common.h 4** PROJECT : UEIP 5** MODULES : ATM (ADSL) 6** 7** DATE : 1 AUG 2005 8** AUTHOR : Xu Liang 9** DESCRIPTION : ATM Driver (PPE Registers) 10** COPYRIGHT : Copyright (c) 2006 11** Infineon Technologies AG 12** Am Campeon 1-12, 85579 Neubiberg, Germany 13** 14** This program is free software; you can redistribute it and/or modify 15** it under the terms of the GNU General Public License as published by 16** the Free Software Foundation; either version 2 of the License, or 17** (at your option) any later version. 18** 19** HISTORY 20** $Date $Author $Comment 21** 4 AUG 2005 Xu Liang Initiate Version 22** 23 OCT 2006 Xu Liang Add GPL header. 23** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) 24*******************************************************************************/ 25 26 27 28#ifndef IFXMIPS_ATM_PPE_COMMON_H 29#define IFXMIPS_ATM_PPE_COMMON_H 30 31 32 33#if defined(CONFIG_DANUBE) 34 #include "ifxmips_atm_ppe_danube.h" 35#elif defined(CONFIG_AMAZON_SE) 36 #include "ifxmips_atm_ppe_amazon_se.h" 37#elif defined(CONFIG_AR9) 38 #include "ifxmips_atm_ppe_ar9.h" 39#elif defined(CONFIG_VR9) 40 #include "ifxmips_atm_ppe_vr9.h" 41#else 42 #error Platform is not specified! 43#endif 44 45 46 47/* 48 * Code/Data Memory (CDM) Interface Configuration Register 49 */ 50#define CDM_CFG PPE_REG_ADDR(0x0100) 51 52#define CDM_CFG_RAM1 GET_BITS(*CDM_CFG, 3, 2) 53#define CDM_CFG_RAM0 (*CDM_CFG & (1 << 1)) 54 55#define CDM_CFG_RAM1_SET(value) SET_BITS(0, 3, 2, value) 56#define CDM_CFG_RAM0_SET(value) ((value) ? (1 << 1) : 0) 57 58/* 59 * QSB Internal Cell Delay Variation Register 60 */ 61#define QSB_ICDV QSB_CONF_REG_ADDR(0x0007) 62 63#define QSB_ICDV_TAU GET_BITS(*QSB_ICDV, 5, 0) 64 65#define QSB_ICDV_TAU_SET(value) SET_BITS(0, 5, 0, value) 66 67/* 68 * QSB Scheduler Burst Limit Register 69 */ 70#define QSB_SBL QSB_CONF_REG_ADDR(0x0009) 71 72#define QSB_SBL_SBL GET_BITS(*QSB_SBL, 3, 0) 73 74#define QSB_SBL_SBL_SET(value) SET_BITS(0, 3, 0, value) 75 76/* 77 * QSB Configuration Register 78 */ 79#define QSB_CFG QSB_CONF_REG_ADDR(0x000A) 80 81#define QSB_CFG_TSTEPC GET_BITS(*QSB_CFG, 1, 0) 82 83#define QSB_CFG_TSTEPC_SET(value) SET_BITS(0, 1, 0, value) 84 85/* 86 * QSB RAM Transfer Table Register 87 */ 88#define QSB_RTM QSB_CONF_REG_ADDR(0x000B) 89 90#define QSB_RTM_DM (*QSB_RTM) 91 92#define QSB_RTM_DM_SET(value) ((value) & 0xFFFFFFFF) 93 94/* 95 * QSB RAM Transfer Data Register 96 */ 97#define QSB_RTD QSB_CONF_REG_ADDR(0x000C) 98 99#define QSB_RTD_TTV (*QSB_RTD) 100 101#define QSB_RTD_TTV_SET(value) ((value) & 0xFFFFFFFF) 102 103/* 104 * QSB RAM Access Register 105 */ 106#define QSB_RAMAC QSB_CONF_REG_ADDR(0x000D) 107 108#define QSB_RAMAC_RW (*QSB_RAMAC & (1 << 31)) 109#define QSB_RAMAC_TSEL GET_BITS(*QSB_RAMAC, 27, 24) 110#define QSB_RAMAC_LH (*QSB_RAMAC & (1 << 16)) 111#define QSB_RAMAC_TESEL GET_BITS(*QSB_RAMAC, 9, 0) 112 113#define QSB_RAMAC_RW_SET(value) ((value) ? (1 << 31) : 0) 114#define QSB_RAMAC_TSEL_SET(value) SET_BITS(0, 27, 24, value) 115#define QSB_RAMAC_LH_SET(value) ((value) ? (1 << 16) : 0) 116#define QSB_RAMAC_TESEL_SET(value) SET_BITS(0, 9, 0, value) 117 118/* 119 * QSB Queue Scheduling and Shaping Definitions 120 */ 121#define QSB_WFQ_NONUBR_MAX 0x3f00 122#define QSB_WFQ_UBR_BYPASS 0x3fff 123#define QSB_TP_TS_MAX 65472 124#define QSB_TAUS_MAX 64512 125#define QSB_GCR_MIN 18 126 127/* 128 * QSB Constant 129 */ 130#define QSB_RAMAC_RW_READ 0 131#define QSB_RAMAC_RW_WRITE 1 132 133#define QSB_RAMAC_TSEL_QPT 0x01 134#define QSB_RAMAC_TSEL_SCT 0x02 135#define QSB_RAMAC_TSEL_SPT 0x03 136#define QSB_RAMAC_TSEL_VBR 0x08 137 138#define QSB_RAMAC_LH_LOW 0 139#define QSB_RAMAC_LH_HIGH 1 140 141#define QSB_QPT_SET_MASK 0x0 142#define QSB_QVPT_SET_MASK 0x0 143#define QSB_SET_SCT_MASK 0x0 144#define QSB_SET_SPT_MASK 0x0 145#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF 146 147#define QSB_SPT_SBV_VALID (1 << 31) 148#define QSB_SPT_PN_SET(value) (((value) & 0x01) ? (1 << 16) : 0) 149#define QSB_SPT_INTRATE_SET(value) SET_BITS(0, 13, 0, value) 150 151/* 152 * QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry 153 */ 154#if defined(__BIG_ENDIAN) 155 union qsb_queue_parameter_table { 156 struct { 157 unsigned int res1 :1; 158 unsigned int vbr :1; 159 unsigned int wfqf :14; 160 unsigned int tp :16; 161 } bit; 162 u32 dword; 163 }; 164 165 union qsb_queue_vbr_parameter_table { 166 struct { 167 unsigned int taus :16; 168 unsigned int ts :16; 169 } bit; 170 u32 dword; 171 }; 172#else 173 union qsb_queue_parameter_table { 174 struct { 175 unsigned int tp :16; 176 unsigned int wfqf :14; 177 unsigned int vbr :1; 178 unsigned int res1 :1; 179 } bit; 180 u32 dword; 181 }; 182 183 union qsb_queue_vbr_parameter_table { 184 struct { 185 unsigned int ts :16; 186 unsigned int taus :16; 187 } bit; 188 u32 dword; 189 }; 190#endif // defined(__BIG_ENDIAN) 191 192/* 193 * Mailbox IGU0 Registers 194 */ 195#define MBOX_IGU0_ISRS PPE_REG_ADDR(0x0200) 196#define MBOX_IGU0_ISRC PPE_REG_ADDR(0x0201) 197#define MBOX_IGU0_ISR PPE_REG_ADDR(0x0202) 198#define MBOX_IGU0_IER PPE_REG_ADDR(0x0203) 199 200#define MBOX_IGU0_ISRS_SET(n) (1 << (n)) 201#define MBOX_IGU0_ISRC_CLEAR(n) (1 << (n)) 202#define MBOX_IGU0_ISR_ISR(n) (*MBOX_IGU0_ISR & (1 << (n))) 203#define MBOX_IGU0_IER_EN(n) (*MBOX_IGU0_IER & (1 << (n))) 204#define MBOX_IGU0_IER_EN_SET(n) (1 << (n)) 205 206/* 207 * Mailbox IGU1 Registers 208 */ 209#define MBOX_IGU1_ISRS PPE_REG_ADDR(0x0204) 210#define MBOX_IGU1_ISRC PPE_REG_ADDR(0x0205) 211#define MBOX_IGU1_ISR PPE_REG_ADDR(0x0206) 212#define MBOX_IGU1_IER PPE_REG_ADDR(0x0207) 213 214#define MBOX_IGU1_ISRS_SET(n) (1 << (n)) 215#define MBOX_IGU1_ISRC_CLEAR(n) (1 << (n)) 216#define MBOX_IGU1_ISR_ISR(n) (*MBOX_IGU1_ISR & (1 << (n))) 217#define MBOX_IGU1_IER_EN(n) (*MBOX_IGU1_IER & (1 << (n))) 218#define MBOX_IGU1_IER_EN_SET(n) (1 << (n)) 219 220/* 221 * Mailbox IGU3 Registers 222 */ 223#define MBOX_IGU3_ISRS PPE_REG_ADDR(0x0214) 224#define MBOX_IGU3_ISRC PPE_REG_ADDR(0x0215) 225#define MBOX_IGU3_ISR PPE_REG_ADDR(0x0216) 226#define MBOX_IGU3_IER PPE_REG_ADDR(0x0217) 227 228#define MBOX_IGU3_ISRS_SET(n) (1 << (n)) 229#define MBOX_IGU3_ISRC_CLEAR(n) (1 << (n)) 230#define MBOX_IGU3_ISR_ISR(n) (*MBOX_IGU3_ISR & (1 << (n))) 231#define MBOX_IGU3_IER_EN(n) (*MBOX_IGU3_IER & (1 << (n))) 232#define MBOX_IGU3_IER_EN_SET(n) (1 << (n)) 233 234/* 235 * RTHA/TTHA Registers 236 */ 237#define RFBI_CFG PPE_REG_ADDR(0x0400) 238#define RBA_CFG0 PPE_REG_ADDR(0x0404) 239#define RBA_CFG1 PPE_REG_ADDR(0x0405) 240#define RCA_CFG0 PPE_REG_ADDR(0x0408) 241#define RCA_CFG1 PPE_REG_ADDR(0x0409) 242#define RDES_CFG0 PPE_REG_ADDR(0x040C) 243#define RDES_CFG1 PPE_REG_ADDR(0x040D) 244#define SFSM_STATE0 PPE_REG_ADDR(0x0410) 245#define SFSM_STATE1 PPE_REG_ADDR(0x0411) 246#define SFSM_DBA0 PPE_REG_ADDR(0x0412) 247#define SFSM_DBA1 PPE_REG_ADDR(0x0413) 248#define SFSM_CBA0 PPE_REG_ADDR(0x0414) 249#define SFSM_CBA1 PPE_REG_ADDR(0x0415) 250#define SFSM_CFG0 PPE_REG_ADDR(0x0416) 251#define SFSM_CFG1 PPE_REG_ADDR(0x0417) 252#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C) 253#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D) 254#define FFSM_DBA0 PPE_REG_ADDR(0x0508) 255#define FFSM_DBA1 PPE_REG_ADDR(0x0509) 256#define FFSM_CFG0 PPE_REG_ADDR(0x050A) 257#define FFSM_CFG1 PPE_REG_ADDR(0x050B) 258#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E) 259#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F) 260#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514) 261#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515) 262 263/* 264 * PPE TC Logic Registers (partial) 265 */ 266#define DREG_A_VERSION PPE_REG_ADDR(0x0D00) 267#define DREG_A_CFG PPE_REG_ADDR(0x0D01) 268#define DREG_AT_CTRL PPE_REG_ADDR(0x0D02) 269#define DREG_AT_CB_CFG0 PPE_REG_ADDR(0x0D03) 270#define DREG_AT_CB_CFG1 PPE_REG_ADDR(0x0D04) 271#define DREG_AR_CTRL PPE_REG_ADDR(0x0D08) 272#define DREG_AR_CB_CFG0 PPE_REG_ADDR(0x0D09) 273#define DREG_AR_CB_CFG1 PPE_REG_ADDR(0x0D0A) 274#define DREG_A_UTPCFG PPE_REG_ADDR(0x0D0E) 275#define DREG_A_STATUS PPE_REG_ADDR(0x0D0F) 276#define DREG_AT_CFG0 PPE_REG_ADDR(0x0D20) 277#define DREG_AT_CFG1 PPE_REG_ADDR(0x0D21) 278#define DREG_AT_FB_SIZE0 PPE_REG_ADDR(0x0D22) 279#define DREG_AT_FB_SIZE1 PPE_REG_ADDR(0x0D23) 280#define DREG_AT_CELL0 PPE_REG_ADDR(0x0D24) 281#define DREG_AT_CELL1 PPE_REG_ADDR(0x0D25) 282#define DREG_AT_IDLE_CNT0 PPE_REG_ADDR(0x0D26) 283#define DREG_AT_IDLE_CNT1 PPE_REG_ADDR(0x0D27) 284#define DREG_AT_IDLE0 PPE_REG_ADDR(0x0D28) 285#define DREG_AT_IDLE1 PPE_REG_ADDR(0x0D29) 286#define DREG_AR_CFG0 PPE_REG_ADDR(0x0D60) 287#define DREG_AR_CFG1 PPE_REG_ADDR(0x0D61) 288#define DREG_AR_CELL0 PPE_REG_ADDR(0x0D68) 289#define DREG_AR_CELL1 PPE_REG_ADDR(0x0D69) 290#define DREG_AR_IDLE_CNT0 PPE_REG_ADDR(0x0D6A) 291#define DREG_AR_IDLE_CNT1 PPE_REG_ADDR(0x0D6B) 292#define DREG_AR_AIIDLE_CNT0 PPE_REG_ADDR(0x0D6C) 293#define DREG_AR_AIIDLE_CNT1 PPE_REG_ADDR(0x0D6D) 294#define DREG_AR_BE_CNT0 PPE_REG_ADDR(0x0D6E) 295#define DREG_AR_BE_CNT1 PPE_REG_ADDR(0x0D6F) 296#define DREG_AR_HEC_CNT0 PPE_REG_ADDR(0x0D70) 297#define DREG_AR_HEC_CNT1 PPE_REG_ADDR(0x0D71) 298#define DREG_AR_IDLE0 PPE_REG_ADDR(0x0D74) 299#define DREG_AR_IDLE1 PPE_REG_ADDR(0x0D75) 300#define DREG_AR_CVN_CNT0 PPE_REG_ADDR(0x0DA4) 301#define DREG_AR_CVN_CNT1 PPE_REG_ADDR(0x0DA5) 302#define DREG_AR_CVNP_CNT0 PPE_REG_ADDR(0x0DA6) 303#define DREG_AR_CVNP_CNT1 PPE_REG_ADDR(0x0DA7) 304#define DREG_B0_LADR PPE_REG_ADDR(0x0DA8) 305#define DREG_B1_LADR PPE_REG_ADDR(0x0DA9) 306 307#define SFSM_DBA(i) ( (SFSM_dba * ) PPE_REG_ADDR(0x0412 + (i))) 308#define SFSM_CBA(i) ( (SFSM_cba * ) PPE_REG_ADDR(0x0414 + (i))) 309#define SFSM_CFG(i) ( (SFSM_cfg * ) PPE_REG_ADDR(0x0416 + (i))) 310#define SFSM_PGCNT(i) ( (SFSM_pgcnt * ) PPE_REG_ADDR(0x041C + (i))) 311 312#define FFSM_DBA(i) ( (FFSM_dba * ) PPE_REG_ADDR(0x0508 + (i))) 313#define FFSM_CFG(i) ( (FFSM_cfg * ) PPE_REG_ADDR(0x050A + (i))) 314#define FFSM_PGCNT(i) ( (FFSM_pgcnt * ) PPE_REG_ADDR(0x0514 + (i))) 315 316typedef struct { 317 unsigned int res : 19; 318 unsigned int dbase : 13; 319} SFSM_dba; 320 321typedef struct { 322 unsigned int res : 19; 323 unsigned int cbase : 13; 324} SFSM_cba; 325 326typedef struct { 327 unsigned int res : 15; 328 unsigned int endian : 1; 329 unsigned int idlekeep: 1; 330 unsigned int sen : 1; 331 unsigned int res1 : 8; 332 unsigned int pnum : 6; 333} SFSM_cfg; 334 335typedef struct { 336 unsigned int res : 17; 337 unsigned int pptr : 6; 338 unsigned int dcmd : 1; 339 unsigned int res1 : 2; 340 unsigned int upage : 6; 341} SFSM_pgcnt; 342 343typedef struct { 344 unsigned int res : 19; 345 unsigned int dbase : 13; 346} FFSM_dba; 347 348typedef struct { 349 unsigned int res : 12; 350 unsigned int rstptr : 1; 351 unsigned int clvpage : 1; 352 unsigned int fidle : 1; 353 unsigned int endian : 1; 354 unsigned int res1 : 10; 355 unsigned int pnum : 6; 356} FFSM_cfg; 357 358typedef struct { 359 unsigned int res : 17; 360 unsigned int ival : 6; 361 unsigned int icmd : 1; 362 unsigned int res1 : 2; 363 unsigned int vpage : 6; 364} FFSM_pgcnt; 365 366 367 368#endif // IFXMIPS_ATM_PPE_COMMON_H 369