1/****************************************************************************** 2 3 Copyright (c) 2009 4 Infineon Technologies AG 5 Am Campeon 1-12; 81726 Munich, Germany 6 7 For licensing information, see the file 'LICENSE' in the root folder of 8 this software module. 9 10******************************************************************************/ 11 12#ifndef IFXMIPS_MEI_H 13#define IFXMIPS_MEI_H 14 15//#define CONFIG_AMAZON_SE 1 16//#define CONFIG_DANUBE 1 17//#define CONFIG_AR9 1 18 19#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9) 20#error Platform undefined!!! 21#endif 22 23#ifdef IFX_MEI_BSP 24/** This is the character datatype. */ 25typedef char DSL_char_t; 26/** This is the unsigned 8-bit datatype. */ 27typedef unsigned char DSL_uint8_t; 28/** This is the signed 8-bit datatype. */ 29typedef signed char DSL_int8_t; 30/** This is the unsigned 16-bit datatype. */ 31typedef unsigned short DSL_uint16_t; 32/** This is the signed 16-bit datatype. */ 33typedef signed short DSL_int16_t; 34/** This is the unsigned 32-bit datatype. */ 35typedef unsigned long DSL_uint32_t; 36/** This is the signed 32-bit datatype. */ 37typedef signed long DSL_int32_t; 38/** This is the float datatype. */ 39typedef float DSL_float_t; 40/** This is the void datatype. */ 41typedef void DSL_void_t; 42/** integer type, width is depending on processor arch */ 43typedef int DSL_int_t; 44/** unsigned integer type, width is depending on processor arch */ 45typedef unsigned int DSL_uint_t; 46typedef struct file DSL_DRV_file_t; 47typedef struct inode DSL_DRV_inode_t; 48 49/** 50 * Defines all possible CMV groups 51 * */ 52typedef enum { 53 DSL_CMV_GROUP_CNTL = 1, 54 DSL_CMV_GROUP_STAT = 2, 55 DSL_CMV_GROUP_INFO = 3, 56 DSL_CMV_GROUP_TEST = 4, 57 DSL_CMV_GROUP_OPTN = 5, 58 DSL_CMV_GROUP_RATE = 6, 59 DSL_CMV_GROUP_PLAM = 7, 60 DSL_CMV_GROUP_CNFG = 8 61} DSL_CmvGroup_t; 62/** 63 * Defines all opcode types 64 * */ 65typedef enum { 66 H2D_CMV_READ = 0x00, 67 H2D_CMV_WRITE = 0x04, 68 H2D_CMV_INDICATE_REPLY = 0x10, 69 H2D_ERROR_OPCODE_UNKNOWN =0x20, 70 H2D_ERROR_CMV_UNKNOWN =0x30, 71 72 D2H_CMV_READ_REPLY =0x01, 73 D2H_CMV_WRITE_REPLY = 0x05, 74 D2H_CMV_INDICATE = 0x11, 75 D2H_ERROR_OPCODE_UNKNOWN = 0x21, 76 D2H_ERROR_CMV_UNKNOWN = 0x31, 77 D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41, 78 D2H_ERROR_CMV_WRITE_ONLY = 0x51, 79 D2H_ERROR_CMV_READ_ONLY = 0x61, 80 81 H2D_DEBUG_READ_DM = 0x02, 82 H2D_DEBUG_READ_PM = 0x06, 83 H2D_DEBUG_WRITE_DM = 0x0a, 84 H2D_DEBUG_WRITE_PM = 0x0e, 85 86 D2H_DEBUG_READ_DM_REPLY = 0x03, 87 D2H_DEBUG_READ_FM_REPLY = 0x07, 88 D2H_DEBUG_WRITE_DM_REPLY = 0x0b, 89 D2H_DEBUG_WRITE_FM_REPLY = 0x0f, 90 D2H_ERROR_ADDR_UNKNOWN = 0x33, 91 92 D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1 93} DSL_CmvOpcode_t; 94 95/* mutex macros */ 96#define MEI_MUTEX_INIT(id,flag) \ 97 sema_init(&id,flag) 98#define MEI_MUTEX_LOCK(id) \ 99 down_interruptible(&id) 100#define MEI_MUTEX_UNLOCK(id) \ 101 up(&id) 102#define MEI_WAIT(ms) \ 103 {\ 104 set_current_state(TASK_INTERRUPTIBLE);\ 105 schedule_timeout(ms);\ 106 } 107#define MEI_INIT_WAKELIST(name,queue) \ 108 init_waitqueue_head(&queue) 109 110static inline long 111ugly_hack_sleep_on_timeout(wait_queue_head_t *q, long timeout) 112{ 113 unsigned long flags; 114 wait_queue_t wait; 115 116 init_waitqueue_entry(&wait, current); 117 118 __set_current_state(TASK_INTERRUPTIBLE); 119 spin_lock_irqsave(&q->lock, flags); 120 __add_wait_queue(q, &wait); 121 spin_unlock(&q->lock); 122 123 timeout = schedule_timeout(timeout); 124 125 spin_lock_irq(&q->lock); 126 __remove_wait_queue(q, &wait); 127 spin_unlock_irqrestore(&q->lock, flags); 128 129 return timeout; 130} 131 132/* wait for an event, timeout is measured in ms */ 133#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\ 134 ugly_hack_sleep_on_timeout(&ev, timeout * HZ / 1000) 135#define MEI_WAKEUP_EVENT(ev)\ 136 wake_up_interruptible(&ev) 137#endif /* IFX_MEI_BSP */ 138 139/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ 140#define ME_DX_DATA (0x0000) 141#define ME_VERSION (0x0004) 142#define ME_ARC_GP_STAT (0x0008) 143#define ME_DX_STAT (0x000C) 144#define ME_DX_AD (0x0010) 145#define ME_DX_MWS (0x0014) 146#define ME_ME2ARC_INT (0x0018) 147#define ME_ARC2ME_STAT (0x001C) 148#define ME_ARC2ME_MASK (0x0020) 149#define ME_DBG_WR_AD (0x0024) 150#define ME_DBG_RD_AD (0x0028) 151#define ME_DBG_DATA (0x002C) 152#define ME_DBG_DECODE (0x0030) 153#define ME_CONFIG (0x0034) 154#define ME_RST_CTRL (0x0038) 155#define ME_DBG_MASTER (0x003C) 156#define ME_CLK_CTRL (0x0040) 157#define ME_BIST_CTRL (0x0044) 158#define ME_BIST_STAT (0x0048) 159#define ME_XDATA_BASE_SH (0x004c) 160#define ME_XDATA_BASE (0x0050) 161#define ME_XMEM_BAR_BASE (0x0054) 162#define ME_XMEM_BAR0 (0x0054) 163#define ME_XMEM_BAR1 (0x0058) 164#define ME_XMEM_BAR2 (0x005C) 165#define ME_XMEM_BAR3 (0x0060) 166#define ME_XMEM_BAR4 (0x0064) 167#define ME_XMEM_BAR5 (0x0068) 168#define ME_XMEM_BAR6 (0x006C) 169#define ME_XMEM_BAR7 (0x0070) 170#define ME_XMEM_BAR8 (0x0074) 171#define ME_XMEM_BAR9 (0x0078) 172#define ME_XMEM_BAR10 (0x007C) 173#define ME_XMEM_BAR11 (0x0080) 174#define ME_XMEM_BAR12 (0x0084) 175#define ME_XMEM_BAR13 (0x0088) 176#define ME_XMEM_BAR14 (0x008C) 177#define ME_XMEM_BAR15 (0x0090) 178#define ME_XMEM_BAR16 (0x0094) 179 180#define WHILE_DELAY 20000 181/* 182** Define where in ME Processor's memory map the Stratify chip lives 183*/ 184 185#define MAXSWAPSIZE (8 * 1024) //8k *(32bits) 186 187// Mailboxes 188#define MSG_LENGTH 16 // x16 bits 189#define YES_REPLY 1 190#define NO_REPLY 0 191 192#define CMV_TIMEOUT 1000 //jiffies 193 194// Block size per BAR 195#define SDRAM_SEGMENT_SIZE (64*1024) 196// Number of Bar registers 197#define MAX_BAR_REGISTERS (17) 198 199#define XDATA_REGISTER (15) 200 201// ARC register addresss 202#define ARC_STATUS 0x0 203#define ARC_LP_START 0x2 204#define ARC_LP_END 0x3 205#define ARC_DEBUG 0x5 206#define ARC_INT_MASK 0x10A 207 208#define IRAM0_BASE (0x00000) 209#define IRAM1_BASE (0x04000) 210#if defined(CONFIG_DANUBE) 211#define BRAM_BASE (0x0A000) 212#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9) 213#define BRAM_BASE (0x08000) 214#endif 215#define XRAM_BASE (0x18000) 216#define YRAM_BASE (0x1A000) 217#define EXT_MEM_BASE (0x80000) 218#define ARC_GPIO_CTRL (0xC030) 219#define ARC_GPIO_DATA (0xC034) 220 221#define IRAM0_SIZE (16*1024) 222#define IRAM1_SIZE (16*1024) 223#define BRAM_SIZE (12*1024) 224#define XRAM_SIZE (8*1024) 225#define YRAM_SIZE (8*1024) 226#define EXT_MEM_SIZE (1536*1024) 227 228#define ADSL_BASE (0x20000) 229#define CRI_BASE (ADSL_BASE + 0x11F00) 230#define CRI_CCR0 (CRI_BASE + 0x00) 231#define CRI_RST (CRI_BASE + 0x04*4) 232#define ADSL_DILV_BASE (ADSL_BASE+0x20000) 233 234// 235#define IRAM0_ADDR_BIT_MASK 0xFFF 236#define IRAM1_ADDR_BIT_MASK 0xFFF 237#define BRAM_ADDR_BIT_MASK 0xFFF 238#define RX_DILV_ADDR_BIT_MASK 0x1FFF 239 240/*** Bit definitions ***/ 241#define ARC_AUX_HALT (1 << 25) 242#define ARC_DEBUG_HALT (1 << 1) 243#define FALSE 0 244#define TRUE 1 245#define BIT0 (1<<0) 246#define BIT1 (1<<1) 247#define BIT2 (1<<2) 248#define BIT3 (1<<3) 249#define BIT4 (1<<4) 250#define BIT5 (1<<5) 251#define BIT6 (1<<6) 252#define BIT7 (1<<7) 253#define BIT8 (1<<8) 254#define BIT9 (1<<9) 255#define BIT10 (1<<10) 256#define BIT11 (1<<11) 257#define BIT12 (1<<12) 258#define BIT13 (1<<13) 259#define BIT14 (1<<14) 260#define BIT15 (1<<15) 261#define BIT16 (1<<16) 262#define BIT17 (1<<17) 263#define BIT18 (1<<18) 264#define BIT19 (1<<19) 265#define BIT20 (1<<20) 266#define BIT21 (1<<21) 267#define BIT22 (1<<22) 268#define BIT23 (1<<23) 269#define BIT24 (1<<24) 270#define BIT25 (1<<25) 271#define BIT26 (1<<26) 272#define BIT27 (1<<27) 273#define BIT28 (1<<28) 274#define BIT29 (1<<29) 275#define BIT30 (1<<30) 276#define BIT31 (1<<31) 277 278// CRI_CCR0 Register definitions 279#define CLK_2M_MODE_ENABLE BIT6 280#define ACL_CLK_MODE_ENABLE BIT4 281#define FDF_CLK_MODE_ENABLE BIT2 282#define STM_CLK_MODE_ENABLE BIT0 283 284// CRI_RST Register definitions 285#define FDF_SRST BIT3 286#define MTE_SRST BIT2 287#define FCI_SRST BIT1 288#define AAI_SRST BIT0 289 290// MEI_TO_ARC_INTERRUPT Register definitions 291#define MEI_TO_ARC_INT1 BIT3 292#define MEI_TO_ARC_INT0 BIT2 293#define MEI_TO_ARC_CS_DONE BIT1 //need to check 294#define MEI_TO_ARC_MSGAV BIT0 295 296// ARC_TO_MEI_INTERRUPT Register definitions 297#define ARC_TO_MEI_INT1 BIT8 298#define ARC_TO_MEI_INT0 BIT7 299#define ARC_TO_MEI_CS_REQ BIT6 300#define ARC_TO_MEI_DBG_DONE BIT5 301#define ARC_TO_MEI_MSGACK BIT4 302#define ARC_TO_MEI_NO_ACCESS BIT3 303#define ARC_TO_MEI_CHECK_AAITX BIT2 304#define ARC_TO_MEI_CHECK_AAIRX BIT1 305#define ARC_TO_MEI_MSGAV BIT0 306 307// ARC_TO_MEI_INTERRUPT_MASK Register definitions 308#define GP_INT1_EN BIT8 309#define GP_INT0_EN BIT7 310#define CS_REQ_EN BIT6 311#define DBG_DONE_EN BIT5 312#define MSGACK_EN BIT4 313#define NO_ACC_EN BIT3 314#define AAITX_EN BIT2 315#define AAIRX_EN BIT1 316#define MSGAV_EN BIT0 317 318#define MEI_SOFT_RESET BIT0 319 320#define HOST_MSTR BIT0 321 322#define JTAG_MASTER_MODE 0x0 323#define MEI_MASTER_MODE HOST_MSTR 324 325// MEI_DEBUG_DECODE Register definitions 326#define MEI_DEBUG_DEC_MASK (0x3) 327#define MEI_DEBUG_DEC_AUX_MASK (0x0) 328#define ME_DBG_DECODE_DMP1_MASK (0x1) 329#define MEI_DEBUG_DEC_DMP2_MASK (0x2) 330#define MEI_DEBUG_DEC_CORE_MASK (0x3) 331 332#define AUX_STATUS (0x0) 333#define AUX_ARC_GPIO_CTRL (0x10C) 334#define AUX_ARC_GPIO_DATA (0x10D) 335// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate 336// page swap requests. 337#if defined(CONFIG_DANUBE) 338#define OMBOX_BASE 0xDF80 339#define ARC_TO_MEI_MAILBOX 0xDFA0 340#define IMBOX_BASE 0xDFC0 341#define MEI_TO_ARC_MAILBOX 0xDFD0 342#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9) 343#define OMBOX_BASE 0xAF80 344#define ARC_TO_MEI_MAILBOX 0xAFA0 345#define IMBOX_BASE 0xAFC0 346#define MEI_TO_ARC_MAILBOX 0xAFD0 347#endif 348 349#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C) 350#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C) 351#define OMBOX1 (OMBOX_BASE+0x4) 352 353// Codeswap request messages are indicated by setting BIT31 354#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000) 355 356// Clear Eoc messages received are indicated by setting BIT17 357#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000) 358#define OMB_REBOOT_INTERRUPT_CODE (1 << 18) 359 360/* 361** Swap page header 362*/ 363// Page must be loaded at boot time if size field has BIT31 set 364#define BOOT_FLAG (BIT31) 365#define BOOT_FLAG_MASK ~BOOT_FLAG 366 367#define FREE_RELOAD 1 368#define FREE_SHOWTIME 2 369#define FREE_ALL 3 370 371// marcos 372#define IFX_MEI_WRITE_REGISTER_L(data,addr) *((volatile u32*)(addr)) = (u32)(data) 373#define IFX_MEI_READ_REGISTER_L(addr) (*((volatile u32*)(addr))) 374#define SET_BIT(reg, mask) reg |= (mask) 375#define CLEAR_BIT(reg, mask) reg &= (~mask) 376#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) 377//#define SET_BITS(reg, mask) SET_BIT(reg, mask) 378#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} 379 380#define ALIGN_SIZE ( 1L<<10 ) //1K size align 381#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) ) 382 383// swap marco 384#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);} 385#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);} 386 387 388#ifdef CONFIG_PROC_FS 389typedef struct reg_entry 390{ 391 int *flag; 392 char name[30]; /* big enough to hold names */ 393 char description[100]; /* big enough to hold description */ 394 unsigned short low_ino; 395} reg_entry_t; 396#endif 397// Swap page header describes size in 32-bit words, load location, and image offset 398// for program and/or data segments 399typedef struct _arc_swp_page_hdr { 400 u32 p_offset; //Offset bytes of progseg from beginning of image 401 u32 p_dest; //Destination addr of progseg on processor 402 u32 p_size; //Size in 32-bitwords of program segment 403 u32 d_offset; //Offset bytes of dataseg from beginning of image 404 u32 d_dest; //Destination addr of dataseg on processor 405 u32 d_size; //Size in 32-bitwords of data segment 406} ARC_SWP_PAGE_HDR; 407 408/* 409** Swap image header 410*/ 411#define GET_PROG 0 // Flag used for program mem segment 412#define GET_DATA 1 // Flag used for data mem segment 413 414// Image header contains size of image, checksum for image, and count of 415// page headers. Following that are 'count' page headers followed by 416// the code and/or data segments to be loaded 417typedef struct _arc_img_hdr { 418 u32 size; // Size of binary image in bytes 419 u32 checksum; // Checksum for image 420 u32 count; // Count of swp pages in image 421 ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy 422} ARC_IMG_HDR; 423 424typedef struct smmu_mem_info { 425 int type; 426 int boot; 427 unsigned long nCopy; 428 unsigned long size; 429 unsigned char *address; 430 unsigned char *org_address; 431} smmu_mem_info_t; 432 433#ifdef __KERNEL__ 434typedef struct ifx_mei_device_private { 435 int modem_ready; 436 int arcmsgav; 437 int cmv_reply; 438 int cmv_waiting; 439 // Mei to ARC CMV count, reply count, ARC Indicator count 440 int modem_ready_cnt; 441 int cmv_count; 442 int reply_count; 443 unsigned long image_size; 444 int nBar; 445 u16 Recent_indicator[MSG_LENGTH]; 446 447 u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4))); 448 449 smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS]; 450 ARC_IMG_HDR *img_hdr; 451 // to wait for arc cmv reply, sleep on wait_queue_arcmsgav; 452 wait_queue_head_t wait_queue_arcmsgav; 453 wait_queue_head_t wait_queue_modemready; 454 struct semaphore mei_cmv_sema; 455} ifx_mei_device_private_t; 456#endif 457typedef struct winhost_message { 458 union { 459 u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4))); 460 u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4))); 461 } msg; 462} DSL_DEV_WinHost_Message_t; 463/******************************************************************************************************** 464 * DSL CPE API Driver Stack Interface Definitions 465 * *****************************************************************************************************/ 466/** IOCTL codes for bsp driver */ 467#define DSL_IOC_MEI_BSP_MAGIC 's' 468 469#define DSL_FIO_BSP_DSL_START _IO (DSL_IOC_MEI_BSP_MAGIC, 0) 470#define DSL_FIO_BSP_RUN _IO (DSL_IOC_MEI_BSP_MAGIC, 1) 471#define DSL_FIO_BSP_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 2) 472#define DSL_FIO_BSP_RESET _IO (DSL_IOC_MEI_BSP_MAGIC, 3) 473#define DSL_FIO_BSP_REBOOT _IO (DSL_IOC_MEI_BSP_MAGIC, 4) 474#define DSL_FIO_BSP_HALT _IO (DSL_IOC_MEI_BSP_MAGIC, 5) 475#define DSL_FIO_BSP_BOOTDOWNLOAD _IO (DSL_IOC_MEI_BSP_MAGIC, 6) 476#define DSL_FIO_BSP_JTAG_ENABLE _IO (DSL_IOC_MEI_BSP_MAGIC, 7) 477#define DSL_FIO_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 8) 478#define DSL_FIO_ARC_MUX_TEST _IO (DSL_IOC_MEI_BSP_MAGIC, 9) 479#define DSL_FIO_BSP_REMOTE _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32) 480#define DSL_FIO_BSP_GET_BASE_ADDRESS _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32) 481#define DSL_FIO_BSP_IS_MODEM_READY _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32) 482#define DSL_FIO_BSP_GET_VERSION _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t) 483#define DSL_FIO_BSP_CMV_WINHOST _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t) 484#define DSL_FIO_BSP_CMV_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t) 485#define DSL_FIO_BSP_CMV_WRITE _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t) 486#define DSL_FIO_BSP_DEBUG_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t) 487#define DSL_FIO_BSP_DEBUG_WRITE _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t) 488#define DSL_FIO_BSP_GET_CHIP_INFO _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t) 489 490#define DSL_DEV_MEIDEBUG_BUFFER_SIZES 512 491 492typedef struct DSL_DEV_MeiDebug 493{ 494 DSL_uint32_t iAddress; 495 DSL_uint32_t iCount; 496 DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES]; 497} DSL_DEV_MeiDebug_t; /* meidebug */ 498 499/** 500 * Structure is used for debug access only. 501 * Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */ 502typedef struct struct_meireg 503{ 504 /* 505 * Specifies that address for debug access */ 506 unsigned long iAddress; 507 /* 508 * Specifies the pointer to the data that has to be written or returns a 509 * pointer to the data that has been read out*/ 510 unsigned long iData; 511} DSL_DEV_MeiReg_t; /* meireg */ 512 513typedef struct DSL_DEV_Device 514{ 515 DSL_int_t nInUse; /* modem state, update by bsp driver, */ 516 DSL_void_t *pPriv; 517 DSL_uint32_t base_address; /* mei base address */ 518 DSL_int_t nIrq[2]; /* irq number */ 519#define IFX_DFEIR 0 520#define IFX_DYING_GASP 1 521 DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */ 522#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)) 523 struct module *owner; 524#endif 525} DSL_DEV_Device_t; /* ifx_adsl_device_t */ 526 527#define DSL_DEV_PRIVATE(dev) ((ifx_mei_device_private_t*)(dev->pPriv)) 528 529typedef struct DSL_DEV_Version /* ifx_adsl_bsp_version */ 530{ 531 unsigned long major; 532 unsigned long minor; 533 unsigned long revision; 534} DSL_DEV_Version_t; /* ifx_adsl_bsp_version_t */ 535 536typedef struct DSL_DEV_ChipInfo 537{ 538 unsigned long major; 539 unsigned long minor; 540} DSL_DEV_HwVersion_t; 541 542typedef struct 543{ 544 DSL_uint8_t dummy; 545} DSL_DEV_DeviceConfig_t; 546 547/** error code definitions */ 548typedef enum DSL_DEV_MeiError 549{ 550 DSL_DEV_MEI_ERR_SUCCESS = 0, 551 DSL_DEV_MEI_ERR_FAILURE = -1, 552 DSL_DEV_MEI_ERR_MAILBOX_FULL = -2, 553 DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3, 554 DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4 555} DSL_DEV_MeiError_t; /* MEI_ERROR */ 556 557typedef enum { 558 DSL_BSP_MEMORY_READ=0, 559 DSL_BSP_MEMORY_WRITE, 560} DSL_BSP_MemoryAccessType_t; /* ifx_adsl_memory_access_type_t */ 561 562typedef enum 563{ 564 DSL_LED_LINK_ID=0, 565 DSL_LED_DATA_ID 566} DSL_DEV_LedId_t; /* ifx_adsl_led_id_t */ 567 568typedef enum 569{ 570 DSL_LED_LINK_TYPE=0, 571 DSL_LED_DATA_TYPE 572} DSL_DEV_LedType_t; /* ifx_adsl_led_type_t */ 573 574typedef enum 575{ 576 DSL_LED_HD_CPU=0, 577 DSL_LED_HD_FW 578} DSL_DEV_LedHandler_t; /* ifx_adsl_led_handler_t */ 579 580typedef enum { 581 DSL_LED_ON=0, 582 DSL_LED_OFF, 583 DSL_LED_FLASH, 584} DSL_DEV_LedMode_t; /* ifx_adsl_led_mode_t */ 585 586typedef enum { 587 DSL_CPU_HALT=0, 588 DSL_CPU_RUN, 589 DSL_CPU_RESET, 590} DSL_DEV_CpuMode_t; /* ifx_adsl_cpu_mode_t */ 591 592#if 0 593typedef enum { 594 DSL_BSP_EVENT_DYING_GASP = 0, 595 DSL_BSP_EVENT_CEOC_IRQ, 596} DSL_BSP_Event_id_t; /* ifx_adsl_event_id_t */ 597 598typedef union DSL_BSP_CB_Param 599{ 600 DSL_uint32_t nIrqMessage; 601} DSL_BSP_CB_Param_t; /* ifx_adsl_cbparam_t */ 602 603typedef struct DSL_BSP_CB_Event 604{ 605 DSL_BSP_Event_id_t nID; 606 DSL_DEV_Device_t *pDev; 607 DSL_BSP_CB_Param_t *pParam; 608} DSL_BSP_CB_Event_t; /* ifx_adsl_cb_event_t */ 609#endif 610 611/* external functions (from the BSP Driver) */ 612extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int); 613extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *); 614extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *); 615extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long); 616extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *); 617extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t); 618extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t); 619extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void)); 620extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t); 621extern volatile DSL_DEV_Device_t *adsl_dev; 622 623/** 624 * Dummy structure by now to show mechanism of extended data that will be 625 * provided within event callback itself. 626 * */ 627typedef struct 628{ 629 /** 630 * Dummy value */ 631 DSL_uint32_t nDummy1; 632} DSL_BSP_CB_Event1DataDummy_t; 633 634/** 635 * Dummy structure by now to show mechanism of extended data that will be 636 * provided within event callback itself. 637 * */ 638typedef struct 639{ 640 /** 641 * Dummy value */ 642 DSL_uint32_t nDummy2; 643} DSL_BSP_CB_Event2DataDummy_t; 644 645/** 646 * encapsulate all data structures that are necessary for status event 647 * callbacks. 648 * */ 649typedef union 650{ 651 DSL_BSP_CB_Event1DataDummy_t dataEvent1; 652 DSL_BSP_CB_Event2DataDummy_t dataEvent2; 653} DSL_BSP_CB_DATA_Union_t; 654 655 656typedef enum 657{ 658 /** 659 * Informs the upper layer driver (DSL CPE API) about a reboot request from the 660 * firmware. 661 * \note This event does NOT include any additional data. 662 * More detailed information upon reboot reason has to be requested from 663 * upper layer software via CMV (INFO 109) if necessary. */ 664 DSL_BSP_CB_FIRST = 0, 665 DSL_BSP_CB_DYING_GASP, 666 DSL_BSP_CB_CEOC_IRQ, 667 DSL_BSP_CB_FIRMWARE_REBOOT, 668 /** 669 * Delimiter only */ 670 DSL_BSP_CB_LAST 671} DSL_BSP_CB_Type_t; 672 673/** 674 * Specifies the common event type that has to be used for registering and 675 * signalling of interrupts/autonomous status events from MEI BSP Driver. 676 * 677 * \param pDev 678 * Context pointer from MEI BSP Driver. 679 * 680 * \param IFX_ADSL_BSP_CallbackType_t 681 * Specifies the event callback type (reason of callback). Regrading to the 682 * setting of this value the data which is included in the following union 683 * might have different meanings. 684 * Please refer to the description of the union to get information about the 685 * meaning of the included data. 686 * 687 * \param pData 688 * Data according to \ref DSL_BSP_CB_DATA_Union_t. 689 * If this pointer is NULL there is no additional data available. 690 * 691 * \return depending on event 692 */ 693typedef int (*DSL_BSP_EventCallback_t) 694( 695 DSL_DEV_Device_t *pDev, 696 DSL_BSP_CB_Type_t nCallbackType, 697 DSL_BSP_CB_DATA_Union_t *pData 698); 699 700typedef struct { 701 DSL_BSP_EventCallback_t function; 702 DSL_BSP_CB_Type_t event; 703 DSL_BSP_CB_DATA_Union_t *pData; 704} DSL_BSP_EventCallBack_t; 705 706extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *); 707extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *); 708 709/** Modem states */ 710#define DSL_DEV_STAT_InitState 0x0000 711#define DSL_DEV_STAT_ReadyState 0x0001 712#define DSL_DEV_STAT_FailState 0x0002 713#define DSL_DEV_STAT_IdleState 0x0003 714#define DSL_DEV_STAT_QuietState 0x0004 715#define DSL_DEV_STAT_GhsState 0x0005 716#define DSL_DEV_STAT_FullInitState 0x0006 717#define DSL_DEV_STAT_ShowTimeState 0x0007 718#define DSL_DEV_STAT_FastRetrainState 0x0008 719#define DSL_DEV_STAT_LoopDiagMode 0x0009 720#define DSL_DEV_STAT_ShortInit 0x000A /* Bis short initialization */ 721 722#define DSL_DEV_STAT_CODESWAP_COMPLETE 0x0002 723 724#endif //IFXMIPS_MEI_H 725