mach_vm_dep.c revision 1859:b32ad9e8c53a
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26/* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 27/* All Rights Reserved */ 28 29/* 30 * Portions of this source code were derived from Berkeley 4.3 BSD 31 * under license from the Regents of the University of California. 32 */ 33 34#pragma ident "%Z%%M% %I% %E% SMI" 35 36/* 37 * UNIX machine dependent virtual memory support. 38 */ 39 40#include <sys/vm.h> 41#include <sys/exec.h> 42#include <sys/cmn_err.h> 43#include <sys/cpu_module.h> 44#include <sys/cpu.h> 45#include <sys/elf_SPARC.h> 46#include <sys/archsystm.h> 47#include <vm/hat_sfmmu.h> 48#include <sys/memnode.h> 49#include <sys/mem_cage.h> 50#include <vm/vm_dep.h> 51#include <sys/error.h> 52#include <sys/machsystm.h> 53#include <vm/seg_kmem.h> 54 55uint_t page_colors = 0; 56uint_t page_colors_mask = 0; 57uint_t page_coloring_shift = 0; 58int consistent_coloring; 59 60uint_t mmu_page_sizes = MMU_PAGE_SIZES; 61uint_t max_mmu_page_sizes = MMU_PAGE_SIZES; 62uint_t mmu_hashcnt = MAX_HASHCNT; 63uint_t max_mmu_hashcnt = MAX_HASHCNT; 64size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 65 66/* 67 * A bitmask of the page sizes supported by hardware based upon szc. 68 * The base pagesize (p_szc == 0) must always be supported by the hardware. 69 */ 70int mmu_exported_pagesize_mask; 71uint_t mmu_exported_page_sizes; 72 73uint_t szc_2_userszc[MMU_PAGE_SIZES]; 74uint_t userszc_2_szc[MMU_PAGE_SIZES]; 75 76extern uint_t vac_colors_mask; 77extern int vac_shift; 78 79hw_pagesize_t hw_page_array[] = { 80 {MMU_PAGESIZE, MMU_PAGESHIFT, MMU_PAGESIZE >> MMU_PAGESHIFT}, 81 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, MMU_PAGESIZE64K >> MMU_PAGESHIFT}, 82 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 83 MMU_PAGESIZE512K >> MMU_PAGESHIFT}, 84 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, MMU_PAGESIZE4M >> MMU_PAGESHIFT}, 85 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, MMU_PAGESIZE32M >> MMU_PAGESHIFT}, 86 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 87 MMU_PAGESIZE256M >> MMU_PAGESHIFT}, 88 {0, 0, 0} 89}; 90 91/* 92 * Enable usage of 64k/4M pages for text and 64k pages for initdata for 93 * all sun4v platforms. These variables can be overwritten by the platmod 94 * or the CPU module. User can also change the setting via /etc/system. 95 */ 96 97int use_text_pgsz64k = 1; 98int use_text_pgsz4m = 1; 99int use_initdata_pgsz64k = 1; 100 101/* 102 * disable_text_largepages and disable_initdata_largepages bitmaks reflect 103 * both unconfigured and undesirable page sizes. Current implementation 104 * supports 64K and 4M page sizes for text and only 64K for data. Rest of 105 * the page sizes are not currently supported, hence disabled below. In 106 * future, when support is added for any other page size, it should be 107 * reflected below. 108 * 109 * Note that these bitmask can be set in platform or CPU specific code to 110 * disable page sizes that should not be used. These variables normally 111 * shouldn't be changed via /etc/system. 112 * 113 * These bitmasks are also updated within hat_init to reflect unsupported 114 * page sizes on a sun4v processor per mmu_exported_pagesize_mask global 115 * variable. 116 */ 117 118int disable_text_largepages = 119 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M) | (1 << TTE2G) | 120 (1 << TTE16G); 121int disable_initdata_largepages = 122 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE32M) | (1 << TTE256M) | 123 (1 << TTE2G) | (1 << TTE16G); 124 125/* 126 * Minimum segment size tunables before 64K or 4M large pages 127 * should be used to map it. 128 */ 129size_t text_pgsz64k_minsize = MMU_PAGESIZE64K; 130size_t text_pgsz4m_minsize = MMU_PAGESIZE4M; 131size_t initdata_pgsz64k_minsize = MMU_PAGESIZE64K; 132 133/* 134 * map_addr_proc() is the routine called when the system is to 135 * choose an address for the user. We will pick an address 136 * range which is just below the current stack limit. The 137 * algorithm used for cache consistency on machines with virtual 138 * address caches is such that offset 0 in the vnode is always 139 * on a shm_alignment'ed aligned address. Unfortunately, this 140 * means that vnodes which are demand paged will not be mapped 141 * cache consistently with the executable images. When the 142 * cache alignment for a given object is inconsistent, the 143 * lower level code must manage the translations so that this 144 * is not seen here (at the cost of efficiency, of course). 145 * 146 * addrp is a value/result parameter. 147 * On input it is a hint from the user to be used in a completely 148 * machine dependent fashion. For MAP_ALIGN, addrp contains the 149 * minimal alignment. 150 * 151 * On output it is NULL if no address can be found in the current 152 * processes address space or else an address that is currently 153 * not mapped for len bytes with a page of red zone on either side. 154 * If vacalign is true, then the selected address will obey the alignment 155 * constraints of a vac machine based on the given off value. 156 */ 157/*ARGSUSED3*/ 158void 159map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign, 160 caddr_t userlimit, struct proc *p, uint_t flags) 161{ 162 struct as *as = p->p_as; 163 caddr_t addr; 164 caddr_t base; 165 size_t slen; 166 uintptr_t align_amount; 167 int allow_largepage_alignment = 1; 168 169 base = p->p_brkbase; 170 if (userlimit < as->a_userlimit) { 171 /* 172 * This happens when a program wants to map something in 173 * a range that's accessible to a program in a smaller 174 * address space. For example, a 64-bit program might 175 * be calling mmap32(2) to guarantee that the returned 176 * address is below 4Gbytes. 177 */ 178 ASSERT(userlimit > base); 179 slen = userlimit - base; 180 } else { 181 slen = p->p_usrstack - base - (((size_t)rctl_enforced_value( 182 rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET) 183 & PAGEMASK); 184 } 185 len = (len + PAGEOFFSET) & PAGEMASK; 186 187 /* 188 * Redzone for each side of the request. This is done to leave 189 * one page unmapped between segments. This is not required, but 190 * it's useful for the user because if their program strays across 191 * a segment boundary, it will catch a fault immediately making 192 * debugging a little easier. 193 */ 194 len += (2 * PAGESIZE); 195 196 /* 197 * If the request is larger than the size of a particular 198 * mmu level, then we use that level to map the request. 199 * But this requires that both the virtual and the physical 200 * addresses be aligned with respect to that level, so we 201 * do the virtual bit of nastiness here. 202 * 203 * For 32-bit processes, only those which have specified 204 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise 205 * we can potentially waste up to 256MB of the 4G process address 206 * space just for alignment. 207 * 208 * XXXQ Should iterate trough hw_page_array here to catch 209 * all supported pagesizes 210 */ 211 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 || 212 ((uintptr_t)*addrp) != 0)) { 213 allow_largepage_alignment = 0; 214 } 215 if ((mmu_page_sizes == max_mmu_page_sizes) && 216 allow_largepage_alignment && 217 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */ 218 align_amount = MMU_PAGESIZE256M; 219 } else if ((mmu_page_sizes == max_mmu_page_sizes) && 220 allow_largepage_alignment && 221 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */ 222 align_amount = MMU_PAGESIZE32M; 223 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */ 224 align_amount = MMU_PAGESIZE4M; 225 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */ 226 align_amount = MMU_PAGESIZE512K; 227 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */ 228 align_amount = MMU_PAGESIZE64K; 229 } else { 230 /* 231 * Align virtual addresses on a 64K boundary to ensure 232 * that ELF shared libraries are mapped with the appropriate 233 * alignment constraints by the run-time linker. 234 */ 235 align_amount = ELF_SPARC_MAXPGSZ; 236 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) && 237 ((uintptr_t)*addrp < align_amount)) 238 align_amount = (uintptr_t)*addrp; 239 } 240 241 /* 242 * 64-bit processes require 1024K alignment of ELF shared libraries. 243 */ 244 if (p->p_model == DATAMODEL_LP64) 245 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ); 246#ifdef VAC 247 if (vac && vacalign && (align_amount < shm_alignment)) 248 align_amount = shm_alignment; 249#endif 250 251 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) { 252 align_amount = (uintptr_t)*addrp; 253 } 254 len += align_amount; 255 256 /* 257 * Look for a large enough hole starting below the stack limit. 258 * After finding it, use the upper part. Addition of PAGESIZE is 259 * for the redzone as described above. 260 */ 261 as_purge(as); 262 if (as_gap(as, len, &base, &slen, AH_HI, NULL) == 0) { 263 caddr_t as_addr; 264 265 addr = base + slen - len + PAGESIZE; 266 as_addr = addr; 267 /* 268 * Round address DOWN to the alignment amount, 269 * add the offset, and if this address is less 270 * than the original address, add alignment amount. 271 */ 272 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l))); 273 addr += (long)(off & (align_amount - 1l)); 274 if (addr < as_addr) { 275 addr += align_amount; 276 } 277 278 ASSERT(addr <= (as_addr + align_amount)); 279 ASSERT(((uintptr_t)addr & (align_amount - 1l)) == 280 ((uintptr_t)(off & (align_amount - 1l)))); 281 *addrp = addr; 282 283 } else { 284 *addrp = NULL; /* no more virtual space */ 285 } 286} 287 288/* Auto large page tunables. */ 289int auto_lpg_tlb_threshold = 32; 290int auto_lpg_minszc = TTE64K; 291int auto_lpg_maxszc = TTE256M; 292size_t auto_lpg_heap_default = MMU_PAGESIZE64K; 293size_t auto_lpg_stack_default = MMU_PAGESIZE64K; 294size_t auto_lpg_va_default = MMU_PAGESIZE64K; 295size_t auto_lpg_remap_threshold = 0; /* always remap */ 296/* 297 * Number of pages in 1 GB. Don't enable automatic large pages if we have 298 * fewer than this many pages. 299 */ 300pgcnt_t auto_lpg_min_physmem = 1 << (30 - MMU_PAGESHIFT); 301 302size_t 303map_pgsz(int maptype, struct proc *p, caddr_t addr, size_t len, int *remap) 304{ 305 uint_t n; 306 size_t pgsz = 0; 307 308 if (remap) 309 *remap = (len > auto_lpg_remap_threshold); 310 311 switch (maptype) { 312 case MAPPGSZ_ISM: 313 n = hat_preferred_pgsz(p->p_as->a_hat, addr, len, maptype); 314 pgsz = hw_page_array[n].hp_size; 315 break; 316 317 case MAPPGSZ_VA: 318 n = hat_preferred_pgsz(p->p_as->a_hat, addr, len, maptype); 319 pgsz = hw_page_array[n].hp_size; 320 if ((pgsz <= MMU_PAGESIZE) || 321 !IS_P2ALIGNED(addr, pgsz) || !IS_P2ALIGNED(len, pgsz)) 322 pgsz = map_pgszva(p, addr, len); 323 break; 324 325 case MAPPGSZ_STK: 326 pgsz = map_pgszstk(p, addr, len); 327 break; 328 329 case MAPPGSZ_HEAP: 330 pgsz = map_pgszheap(p, addr, len); 331 break; 332 } 333 return (pgsz); 334} 335 336/* 337 * Platform-dependent page scrub call. 338 * We call hypervisor to scrub the page. 339 */ 340void 341pagescrub(page_t *pp, uint_t off, uint_t len) 342{ 343 uint64_t pa, length; 344 345 pa = (uint64_t)(pp->p_pagenum << MMU_PAGESHIFT + off); 346 length = (uint64_t)len; 347 348 (void) mem_scrub(pa, length); 349} 350 351void 352sync_data_memory(caddr_t va, size_t len) 353{ 354 /* Call memory sync function */ 355 mem_sync(va, len); 356} 357 358size_t 359mmu_get_kernel_lpsize(size_t lpsize) 360{ 361 extern int mmu_exported_pagesize_mask; 362 uint_t tte; 363 364 if (lpsize == 0) { 365 /* no setting for segkmem_lpsize in /etc/system: use default */ 366 if (mmu_exported_pagesize_mask & (1 << TTE256M)) { 367 lpsize = MMU_PAGESIZE256M; 368 } else if (mmu_exported_pagesize_mask & (1 << TTE4M)) { 369 lpsize = MMU_PAGESIZE4M; 370 } else if (mmu_exported_pagesize_mask & (1 << TTE64K)) { 371 lpsize = MMU_PAGESIZE64K; 372 } else { 373 lpsize = MMU_PAGESIZE; 374 } 375 376 return (lpsize); 377 } 378 379 for (tte = TTE8K; tte <= TTE256M; tte++) { 380 381 if ((mmu_exported_pagesize_mask & (1 << tte)) == 0) 382 continue; 383 384 if (lpsize == TTEBYTES(tte)) 385 return (lpsize); 386 } 387 388 lpsize = TTEBYTES(TTE8K); 389 return (lpsize); 390} 391 392void 393mmu_init_kcontext() 394{ 395} 396 397/*ARGSUSED*/ 398void 399mmu_init_kernel_pgsz(struct hat *hat) 400{ 401} 402 403#define QUANTUM_SIZE 64 404 405static vmem_t *contig_mem_slab_arena; 406static vmem_t *contig_mem_arena; 407 408uint_t contig_mem_slab_size = MMU_PAGESIZE4M; 409 410static void * 411contig_mem_span_alloc(vmem_t *vmp, size_t size, int vmflag) 412{ 413 page_t *ppl; 414 page_t *rootpp; 415 caddr_t addr = NULL; 416 pgcnt_t npages = btopr(size); 417 page_t **ppa; 418 int pgflags; 419 int i = 0; 420 421 422 /* 423 * The import request should be at least 424 * contig_mem_slab_size because that is the 425 * slab arena's quantum. The size can be 426 * further restricted since contiguous 427 * allocations larger than contig_mem_slab_size 428 * are not supported here. 429 */ 430 ASSERT(size == contig_mem_slab_size); 431 432 if ((addr = vmem_xalloc(vmp, size, size, 0, 0, 433 NULL, NULL, vmflag)) == NULL) { 434 return (NULL); 435 } 436 437 /* The address should be slab-size aligned. */ 438 ASSERT(((uintptr_t)addr & (contig_mem_slab_size - 1)) == 0); 439 440 if (page_resv(npages, vmflag & VM_KMFLAGS) == 0) { 441 vmem_xfree(vmp, addr, size); 442 return (NULL); 443 } 444 445 pgflags = PG_EXCL; 446 if ((vmflag & VM_NOSLEEP) == 0) 447 pgflags |= PG_WAIT; 448 if (vmflag & VM_PANIC) 449 pgflags |= PG_PANIC; 450 if (vmflag & VM_PUSHPAGE) 451 pgflags |= PG_PUSHPAGE; 452 453 ppl = page_create_va_large(&kvp, (u_offset_t)(uintptr_t)addr, size, 454 pgflags, &kvseg, addr, NULL); 455 456 if (ppl == NULL) { 457 vmem_xfree(vmp, addr, size); 458 page_unresv(npages); 459 return (NULL); 460 } 461 462 rootpp = ppl; 463 ppa = kmem_zalloc(npages * sizeof (page_t *), KM_SLEEP); 464 while (ppl != NULL) { 465 page_t *pp = ppl; 466 ppa[i++] = pp; 467 page_sub(&ppl, pp); 468 ASSERT(page_iolock_assert(pp)); 469 page_io_unlock(pp); 470 } 471 472 /* 473 * Load the locked entry. It's OK to preload the entry into 474 * the TSB since we now support large mappings in the kernel TSB. 475 */ 476 hat_memload_array(kas.a_hat, (caddr_t)rootpp->p_offset, size, 477 ppa, (PROT_ALL & ~PROT_USER) | HAT_NOSYNC, HAT_LOAD_LOCK); 478 479 for (--i; i >= 0; --i) { 480 (void) page_pp_lock(ppa[i], 0, 1); 481 page_unlock(ppa[i]); 482 } 483 484 kmem_free(ppa, npages * sizeof (page_t *)); 485 return (addr); 486} 487 488void 489contig_mem_span_free(vmem_t *vmp, void *inaddr, size_t size) 490{ 491 page_t *pp; 492 caddr_t addr = inaddr; 493 caddr_t eaddr; 494 pgcnt_t npages = btopr(size); 495 pgcnt_t pgs_left = npages; 496 page_t *rootpp = NULL; 497 498 ASSERT(((uintptr_t)addr & (contig_mem_slab_size - 1)) == 0); 499 500 hat_unload(kas.a_hat, addr, size, HAT_UNLOAD_UNLOCK); 501 502 for (eaddr = addr + size; addr < eaddr; addr += PAGESIZE) { 503 pp = page_lookup(&kvp, (u_offset_t)(uintptr_t)addr, SE_EXCL); 504 if (pp == NULL) 505 panic("contig_mem_span_free: page not found"); 506 507 ASSERT(PAGE_EXCL(pp)); 508 page_pp_unlock(pp, 0, 1); 509 510 if (rootpp == NULL) 511 rootpp = pp; 512 if (--pgs_left == 0) { 513 /* 514 * similar logic to segspt_free_pages, but we know we 515 * have one large page. 516 */ 517 page_destroy_pages(rootpp); 518 } 519 } 520 page_unresv(npages); 521 522 if (vmp != NULL) 523 vmem_xfree(vmp, inaddr, size); 524} 525 526static void * 527contig_vmem_xalloc_aligned_wrapper(vmem_t *vmp, size_t size, int vmflag) 528{ 529 return (vmem_xalloc(vmp, size, size, 0, 0, NULL, NULL, vmflag)); 530} 531 532/* 533 * conting_mem_alloc_align allocates real contiguous memory with the specified 534 * alignment upto contig_mem_slab_size. The alignment must be a power of 2. 535 */ 536void * 537contig_mem_alloc_align(size_t size, size_t align) 538{ 539 ASSERT(align <= contig_mem_slab_size); 540 541 if ((align & (align - 1)) != 0) 542 return (NULL); 543 544 return (vmem_xalloc(contig_mem_arena, size, align, 0, 0, 545 NULL, NULL, VM_NOSLEEP)); 546} 547 548/* 549 * Allocates size aligned contiguous memory upto contig_mem_slab_size. 550 * Size must be a power of 2. 551 */ 552void * 553contig_mem_alloc(size_t size) 554{ 555 ASSERT((size & (size - 1)) == 0); 556 return (contig_mem_alloc_align(size, size)); 557} 558 559void 560contig_mem_free(void *vaddr, size_t size) 561{ 562 vmem_xfree(contig_mem_arena, vaddr, size); 563} 564 565/* 566 * We create a set of stacked vmem arenas to enable us to 567 * allocate large >PAGESIZE chucks of contiguous Real Address space 568 * This is what the Dynamics TSB support does for TSBs. 569 * The contig_mem_arena import functions are exactly the same as the 570 * TSB kmem_default arena import functions. 571 */ 572void 573contig_mem_init(void) 574{ 575 576 contig_mem_slab_arena = vmem_create("contig_mem_slab_arena", NULL, 0, 577 contig_mem_slab_size, contig_vmem_xalloc_aligned_wrapper, 578 vmem_xfree, heap_arena, 0, VM_SLEEP); 579 580 contig_mem_arena = vmem_create("contig_mem_arena", NULL, 0, 581 QUANTUM_SIZE, contig_mem_span_alloc, contig_mem_span_free, 582 contig_mem_slab_arena, 0, VM_SLEEP | VM_BESTFIT); 583 584} 585