niagara2regs.h revision 5631:86330280b9fd
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_NIAGARA2REGS_H 27#define _SYS_NIAGARA2REGS_H 28 29#pragma ident "%Z%%M% %I% %E% SMI" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35#define MB(n) ((n) * 1024 * 1024) 36 37#define L2CACHE_SIZE MB(4) 38#define L2CACHE_LINESIZE 64 39#define L2CACHE_ASSOCIATIVITY 16 40 41#define NIAGARA2_HSVC_MAJOR 1 42#define NIAGARA2_HSVC_MINOR 0 43 44#define VFALLS_HSVC_MAJOR 1 45#define VFALLS_HSVC_MINOR 0 46 47/* PIC overflow range is -16 to -1 */ 48#define PIC_IN_OV_RANGE(x) (((uint32_t)x >= 0xfffffff0) ? 1 : 0) 49 50/* 51 * Niagara2 SPARC Performance Instrumentation Counter 52 */ 53#define PIC0_MASK (((uint64_t)1 << 32) - 1) /* pic0 in bits 31:0 */ 54#define PIC1_SHIFT 32 /* pic1 in bits 64:32 */ 55 56/* 57 * Niagara2 SPARC Performance Control Register 58 */ 59#define CPC_NIAGARA2_PCR_PRIV_SHIFT 0 60#define CPC_NIAGARA2_PCR_ST_SHIFT 1 61#define CPC_NIAGARA2_PCR_UT_SHIFT 2 62 63#define CPC_NIAGARA2_PCR_HT_SHIFT 3 64#define CPC_NIAGARA2_PCR_HT (1ull << CPC_NIAGARA2_PCR_HT_SHIFT) 65 66#define CPC_NIAGARA2_PCR_TOE0_SHIFT 4 67#define CPC_NIAGARA2_PCR_TOE1_SHIFT 5 68#define CPC_NIAGARA2_PCR_TOE0 (1ull << CPC_NIAGARA2_PCR_TOE0_SHIFT) 69#define CPC_NIAGARA2_PCR_TOE1 (1ull << CPC_NIAGARA2_PCR_TOE1_SHIFT) 70 71#define CPC_NIAGARA2_PCR_PIC0_SHIFT 6 72#define CPC_NIAGARA2_PCR_PIC1_SHIFT 19 73#define CPC_NIAGARA2_PCR_PIC0_MASK UINT64_C(0xfff) 74#define CPC_NIAGARA2_PCR_PIC1_MASK UINT64_C(0xfff) 75 76#define CPC_NIAGARA2_PCR_OV0_SHIFT 18 77#define CPC_NIAGARA2_PCR_OV1_SHIFT 30 78#define CPC_NIAGARA2_PCR_OV0_MASK UINT64_C(0x40000) 79#define CPC_NIAGARA2_PCR_OV1_MASK UINT64_C(0x80000000) 80 81#define CPC_NIAGARA2_PCR_HOLDOV0_SHIFT 62 82#define CPC_NIAGARA2_PCR_HOLDOV1_SHIFT 63 83#define CPC_NIAGARA2_PCR_HOLDOV0 (1ull << CPC_NIAGARA2_PCR_HOLDOV0_SHIFT) 84#define CPC_NIAGARA2_PCR_HOLDOV1 (1ull << CPC_NIAGARA2_PCR_HOLDOV1_SHIFT) 85 86/* 87 * Hypervisor FAST_TRAP API function numbers to get/set DRAM 88 * performance counters for Niagara2 89 */ 90#define HV_NIAGARA2_GETPERF 0x104 91#define HV_NIAGARA2_SETPERF 0x105 92 93/* 94 * Hypervisor FAST_TRAP API function numbers to get/set DRAM 95 * performance counters for Victoria Falls 96 */ 97#define HV_VFALLS_GETPERF 0x106 98#define HV_VFALLS_SETPERF 0x107 99 100/* 101 * Niagara2 DRAM performance counters 102 */ 103#define NIAGARA_DRAM_PIC0_SEL_SHIFT 0x4 104#define NIAGARA_DRAM_PIC1_SEL_SHIFT 0x0 105 106#define NIAGARA_DRAM_PIC0_SHIFT 0x20 107#define NIAGARA_DRAM_PIC0_MASK 0x7fffffff 108#define NIAGARA_DRAM_PIC1_SHIFT 0x0 109#define NIAGARA_DRAM_PIC1_MASK 0x7fffffff 110 111#if defined(NIAGARA2_IMPL) 112/* 113 * SPARC/DRAM performance counter register numbers for HV_NIAGARA2_GETPERF 114 * and HV_NIAGARA2_SETPERF for Niagara2 115 */ 116#define NIAGARA_DRAM_BANKS 0x4 117 118#define HV_NIAGARA_SPARC_CTL 0x0 119#define HV_NIAGARA_DRAM_CTL0 0x1 120#define HV_NIAGARA_DRAM_COUNT0 0x2 121#define HV_NIAGARA_DRAM_CTL1 0x3 122#define HV_NIAGARA_DRAM_COUNT1 0x4 123#define HV_NIAGARA_DRAM_CTL2 0x5 124#define HV_NIAGARA_DRAM_COUNT2 0x6 125#define HV_NIAGARA_DRAM_CTL3 0x7 126#define HV_NIAGARA_DRAM_COUNT3 0x8 127 128#elif defined(VFALLS_IMPL) 129/* 130 * SPARC/DRAM performance counter register numbers for HV_VFALLS_GETPERF 131 * and HV_VFALLS_SETPERF for Victoria Falls 132 * Support for 4-node configuration 133 */ 134#define NIAGARA_DRAM_BANKS 0x8 135 136#define HV_NIAGARA_SPARC_CTL 0x0 137#define HV_NIAGARA_L2_CTL 0x1 138#define HV_NIAGARA_DRAM_CTL0 0x2 139#define HV_NIAGARA_DRAM_COUNT0 0x3 140#define HV_NIAGARA_DRAM_CTL1 0x4 141#define HV_NIAGARA_DRAM_COUNT1 0x5 142#define HV_NIAGARA_DRAM_CTL2 0x6 143#define HV_NIAGARA_DRAM_COUNT2 0x7 144#define HV_NIAGARA_DRAM_CTL3 0x8 145#define HV_NIAGARA_DRAM_COUNT3 0x9 146#define HV_NIAGARA_DRAM_CTL4 0xa 147#define HV_NIAGARA_DRAM_COUNT4 0xb 148#define HV_NIAGARA_DRAM_CTL5 0xc 149#define HV_NIAGARA_DRAM_COUNT5 0xd 150#define HV_NIAGARA_DRAM_CTL6 0xe 151#define HV_NIAGARA_DRAM_COUNT6 0xf 152#define HV_NIAGARA_DRAM_CTL7 0x10 153#define HV_NIAGARA_DRAM_COUNT7 0x11 154 155#define ZAMBEZI_PIC0_SEL_SHIFT 0x0 156#define ZAMBEZI_PIC1_SEL_SHIFT 0x8 157 158#define ZAMBEZI_LPU_COUNTERS 0x10 159#define ZAMBEZI_GPD_COUNTERS 0x4 160#define ZAMBEZI_ASU_COUNTERS 0x4 161 162#define HV_ZAM0_LPU_A_PCR 0x12 163#define HV_ZAM0_LPU_A_PIC0 0x13 164#define HV_ZAM0_LPU_A_PIC1 0x14 165#define HV_ZAM0_LPU_B_PCR 0x15 166#define HV_ZAM0_LPU_B_PIC0 0x16 167#define HV_ZAM0_LPU_B_PIC1 0x17 168#define HV_ZAM0_LPU_C_PCR 0x18 169#define HV_ZAM0_LPU_C_PIC0 0x19 170#define HV_ZAM0_LPU_C_PIC1 0x1a 171#define HV_ZAM0_LPU_D_PCR 0x1b 172#define HV_ZAM0_LPU_D_PIC0 0x1c 173#define HV_ZAM0_LPU_D_PIC1 0x1d 174#define HV_ZAM0_GPD_PCR 0x1e 175#define HV_ZAM0_GPD_PIC0 0x1f 176#define HV_ZAM0_GPD_PIC1 0x20 177#define HV_ZAM0_ASU_PCR 0x21 178#define HV_ZAM0_ASU_PIC0 0x22 179#define HV_ZAM0_ASU_PIC1 0x23 180 181#define HV_ZAM1_LPU_A_PCR 0x24 182#define HV_ZAM1_LPU_A_PIC0 0x25 183#define HV_ZAM1_LPU_A_PIC1 0x26 184#define HV_ZAM1_LPU_B_PCR 0x27 185#define HV_ZAM1_LPU_B_PIC0 0x28 186#define HV_ZAM1_LPU_B_PIC1 0x29 187#define HV_ZAM1_LPU_C_PCR 0x2a 188#define HV_ZAM1_LPU_C_PIC0 0x2b 189#define HV_ZAM1_LPU_C_PIC1 0x2c 190#define HV_ZAM1_LPU_D_PCR 0x2d 191#define HV_ZAM1_LPU_D_PIC0 0x2e 192#define HV_ZAM1_LPU_D_PIC1 0x2f 193#define HV_ZAM1_GPD_PCR 0x30 194#define HV_ZAM1_GPD_PIC0 0x31 195#define HV_ZAM1_GPD_PIC1 0x32 196#define HV_ZAM1_ASU_PCR 0x33 197#define HV_ZAM1_ASU_PIC0 0x34 198#define HV_ZAM1_ASU_PIC1 0x35 199 200#define HV_ZAM2_LPU_A_PCR 0x36 201#define HV_ZAM2_LPU_A_PIC0 0x37 202#define HV_ZAM2_LPU_A_PIC1 0x38 203#define HV_ZAM2_LPU_B_PCR 0x39 204#define HV_ZAM2_LPU_B_PIC0 0x3a 205#define HV_ZAM2_LPU_B_PIC1 0x3b 206#define HV_ZAM2_LPU_C_PCR 0x3c 207#define HV_ZAM2_LPU_C_PIC0 0x3d 208#define HV_ZAM2_LPU_C_PIC1 0x3e 209#define HV_ZAM2_LPU_D_PCR 0x3f 210#define HV_ZAM2_LPU_D_PIC0 0x40 211#define HV_ZAM2_LPU_D_PIC1 0x41 212#define HV_ZAM2_GPD_PCR 0x42 213#define HV_ZAM2_GPD_PIC0 0x43 214#define HV_ZAM2_GPD_PIC1 0x44 215#define HV_ZAM2_ASU_PCR 0x45 216#define HV_ZAM2_ASU_PIC0 0x46 217#define HV_ZAM2_ASU_PIC1 0x47 218 219#define HV_ZAM3_LPU_A_PCR 0x48 220#define HV_ZAM3_LPU_A_PIC0 0x49 221#define HV_ZAM3_LPU_A_PIC1 0x4a 222#define HV_ZAM3_LPU_B_PCR 0x4b 223#define HV_ZAM3_LPU_B_PIC0 0x4c 224#define HV_ZAM3_LPU_B_PIC1 0x4d 225#define HV_ZAM3_LPU_C_PCR 0x4e 226#define HV_ZAM3_LPU_C_PIC0 0x4f 227#define HV_ZAM3_LPU_C_PIC1 0x50 228#define HV_ZAM3_LPU_D_PCR 0x51 229#define HV_ZAM3_LPU_D_PIC0 0x52 230#define HV_ZAM3_LPU_D_PIC1 0x53 231#define HV_ZAM3_GPD_PCR 0x54 232#define HV_ZAM3_GPD_PIC0 0x55 233#define HV_ZAM3_GPD_PIC1 0x56 234#define HV_ZAM3_ASU_PCR 0x57 235#define HV_ZAM3_ASU_PIC0 0x58 236#define HV_ZAM3_ASU_PIC1 0x59 237 238#define VFALLS_L2_CTL_MASK 0x3 239#define VFALLS_SL3_MASK 0x300 240 241#endif 242 243#ifndef _ASM 244/* 245 * prototypes for hypervisor interface to get/set SPARC and DRAM 246 * performance counters 247 */ 248extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val); 249extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val); 250#endif 251 252#ifdef __cplusplus 253} 254#endif 255 256#endif /* _SYS_NIAGARA2REGS_H */ 257