niagara2regs.h revision 4204:4e0ccf8619c3
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#ifndef _SYS_NIAGARA2REGS_H
27#define	_SYS_NIAGARA2REGS_H
28
29#pragma ident	"%Z%%M%	%I%	%E% SMI"
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
35#define	MB(n)	((n) * 1024 * 1024)
36
37#define	L2CACHE_SIZE		MB(4)
38#define	L2CACHE_LINESIZE	64
39#define	L2CACHE_ASSOCIATIVITY	16
40
41#define	NIAGARA2_HSVC_MAJOR	1
42#define	NIAGARA2_HSVC_MINOR	0
43
44#define	NIAGARA2_PREALLOC_BASE	MB(196)
45
46/* PIC overflow range is -16 to -1 */
47#define	PIC_IN_OV_RANGE(x)	(((uint32_t)x >= 0xfffffff0) ? 1 : 0)
48
49/*
50 * Niagara2 SPARC Performance Instrumentation Counter
51 */
52#define	PIC0_MASK	(((uint64_t)1 << 32) - 1)	/* pic0 in bits 31:0 */
53#define	PIC1_SHIFT	32				/* pic1 in bits 64:32 */
54
55/*
56 * Niagara2 SPARC Performance Control Register
57 */
58#define	CPC_NIAGARA2_PCR_PRIV_SHIFT	0
59#define	CPC_NIAGARA2_PCR_ST_SHIFT	1
60#define	CPC_NIAGARA2_PCR_UT_SHIFT	2
61
62#define	CPC_NIAGARA2_PCR_HT_SHIFT	3
63#define	CPC_NIAGARA2_PCR_HT		(1ull << CPC_NIAGARA2_PCR_HT_SHIFT)
64
65#define	CPC_NIAGARA2_PCR_TOE0_SHIFT	4
66#define	CPC_NIAGARA2_PCR_TOE1_SHIFT	5
67#define	CPC_NIAGARA2_PCR_TOE0		(1ull << CPC_NIAGARA2_PCR_TOE0_SHIFT)
68#define	CPC_NIAGARA2_PCR_TOE1		(1ull << CPC_NIAGARA2_PCR_TOE1_SHIFT)
69
70#define	CPC_NIAGARA2_PCR_PIC0_SHIFT	6
71#define	CPC_NIAGARA2_PCR_PIC1_SHIFT	19
72#define	CPC_NIAGARA2_PCR_PIC0_MASK	UINT64_C(0xfff)
73#define	CPC_NIAGARA2_PCR_PIC1_MASK	UINT64_C(0xfff)
74
75#define	CPC_NIAGARA2_PCR_OV0_SHIFT	18
76#define	CPC_NIAGARA2_PCR_OV1_SHIFT	30
77#define	CPC_NIAGARA2_PCR_OV0_MASK	UINT64_C(0x40000)
78#define	CPC_NIAGARA2_PCR_OV1_MASK	UINT64_C(0x80000000)
79
80#define	CPC_NIAGARA2_PCR_HOLDOV0_SHIFT  62
81#define	CPC_NIAGARA2_PCR_HOLDOV1_SHIFT  63
82#define	CPC_NIAGARA2_PCR_HOLDOV0	(1ull << CPC_NIAGARA2_PCR_HOLDOV0_SHIFT)
83#define	CPC_NIAGARA2_PCR_HOLDOV1	(1ull << CPC_NIAGARA2_PCR_HOLDOV1_SHIFT)
84
85/*
86 * Hypervisor FAST_TRAP API function numbers to get/set DRAM
87 * performance counters
88 */
89#define	HV_NIAGARA2_GETPERF		0x104
90#define	HV_NIAGARA2_SETPERF		0x105
91
92/*
93 * Niagara2 DRAM performance counters
94 */
95#define	NIAGARA_DRAM_BANKS		0x4
96
97#define	NIAGARA_DRAM_PIC0_SEL_SHIFT	0x4
98#define	NIAGARA_DRAM_PIC1_SEL_SHIFT	0x0
99
100#define	NIAGARA_DRAM_PIC0_SHIFT		0x20
101#define	NIAGARA_DRAM_PIC0_MASK		0x7fffffff
102#define	NIAGARA_DRAM_PIC1_SHIFT		0x0
103#define	NIAGARA_DRAM_PIC1_MASK		0x7fffffff
104
105/*
106 * SPARC/DRAM performance counter register numbers for HV_NIAGARA2_GETPERF
107 * and HV_NIAGARA2_SETPERF
108 */
109#define	HV_NIAGARA_SPARC_CTL		0x0
110#define	HV_NIAGARA_DRAM_CTL0		0x1
111#define	HV_NIAGARA_DRAM_COUNT0		0x2
112#define	HV_NIAGARA_DRAM_CTL1		0x3
113#define	HV_NIAGARA_DRAM_COUNT1		0x4
114#define	HV_NIAGARA_DRAM_CTL2		0x5
115#define	HV_NIAGARA_DRAM_COUNT2		0x6
116#define	HV_NIAGARA_DRAM_CTL3		0x7
117#define	HV_NIAGARA_DRAM_COUNT3		0x8
118
119#ifndef _ASM
120/*
121 * prototypes for hypervisor interface to get/set SPARC and DRAM
122 * performance counters
123 */
124extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val);
125extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val);
126#endif
127
128#ifdef __cplusplus
129}
130#endif
131
132#endif /* _SYS_NIAGARA2REGS_H */
133